TPS51116
`
`www.ti.com............................................................................................................................................................... SLUS609G–MAY 2004–REVISED JUNE 2008
`
`COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION
`SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE
`1FEATURES
`2• Synchronous Buck Controller (VDDQ)
`– Wide-Input Voltage Range: 3.0-V to 28-V
`– D−CAP™ Mode with 100-ns Load Step
`Response
`– Current Mode Option Supports Ceramic
`Output Capacitors
`– Supports Soft-Off in S4/S5 States
`– Current Sensing from RDS(on) or Resistor
`– 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
`1.5-V (DDR3) or Output Range 0.75-V to
`3.0-V
`– Equipped with Powergood, Overvoltage
`Protection and Undervoltage Protection
`• 3-A LDO (VTT), Buffered Reference (VREF)
`– Capable to Sink and Source 3 A
`– LDO Input Available to Optimize Power
`Losses
`– Requires only 20-m F Ceramic Output
`Capacitor
`– Buffered Low Noise 10-mA VREF Output
`– Accuracy 20 mV for both VREF and VTT
`– Supports High-Z in S3 and Soft-Off in S4/S5
`– Thermal Shutdown
`
`DESCRIPTION
`The TPS51116 provides a complete power supply for
`DDR/SSTL-2, DDR2/SSTL-18, and DDR3 memory
`systems. It integrates a synchronous buck controller
`with a 3-A sink/source tracking linear regulator and
`buffered low noise reference. The TPS51116 offers
`the lowest total solution cost in systems where space
`is at a premium. The TPS51116 synchronous
`controller
`runs
`fixed
`400kHz
`pseudo-constant
`frequency PWM with an adaptive on-time control that
`can be configured in D-CAP™ Mode for ease of use
`and fastest transient response or in current mode to
`support
`ceramic
`output
`capacitors.
`The
`3-A
`sink/source LDO maintains fast
`transient response
`only requiring 20-m F (2 × 10 m F) of ceramic output
`capacitance.
`In addition,
`the LDO supply input
`is
`available externally to significantly reduce the total
`power losses. The TPS51116 supports all of
`the
`sleep state controls placing VTT at high-Z in S3
`(suspend to RAM) and discharging VDDQ, VTT and
`VTTREF (soft-off)
`in S4/S5 (suspend to disk).
`TPS51116 has all of the protection features including
`thermal shutdown and is offered in both a 20-pin
`HTSSOP PowerPAD™ package and 24-pin 4״ QFN.
`APPLICATIONS
`• DDR/DDR2/DDR3 Memory Power Supplies
`• SSTL-2 SSTL-18 and HSTL Termination
`
`1
`
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
`Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`2D-CAP, PowerPAD are trademarks of Texas Instruments.
`
`PRODUCTION DATA information is current as of publication date.
`Products conform to specifications per the terms of
`the Texas
`Instruments standard warranty. Production processing does not
`necessarily include testing of all parameters.
`
`Copyright © 2004–2008, Texas Instruments Incorporated
`
`Ceramic
`0.1 m F
`
`C1
`
`24
`23
`VTT
`VLDOIN
`VTTGND
`
`22
`21
`20
`VBST DRVH LL
`
`19
`DRVL
`
`VTTSNS
`
`GND
`
`MODE
`
`VTTREF
`
`TPS51116RGE
`
`R1
`5.1 kW
`
`PGND
`
`18
`
`CS_GND
`
`17
`
`CS
`
`16
`
`V5IN
`
`15
`
`V5FILT
`
`14
`
`COMP
`VDDQSNS
`NC
`8
`7
`
`VDDQSET
`9
`
`S3
`10
`
`13
`
`PGOOD
`S5
`NC
`12
`11
`
`R2
`100 kW
`
`C7
`Ceramic
`1 m F
`
`S3
`
`S5
`
`M1
`IRF7821
`
`L1
`
`1 m H
`
`M2
`IRF7832
`
`VDDQ
`1.8 V
`10 A
`
`C6
`SP−CAP
`2y150 m F
`
`R3
`5.1 W
`
`VIN
`C5
`Ceramic
`2y10 m F
`
`5V_IN
`
`C2
`Ceramic
`1 m F
`
`PGOOD
`
`UDG−04153
`
`1 2 3 4 5 6
`
`VTT
`0.9 V
`2 A
`
`VREF
`0.9 V
`10 mA
`
`C3
`Ceramic
`2y10 m F
`
`C4
`
`Ceramic
`0.033 m F
`
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`

`TPS51116
`
`SLUS609G–MAY 2004–REVISED JUNE 2008............................................................................................................................................................... www.ti.com
`
`These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
`during storage or handling to prevent electrostatic damage to the MOS gates.
`
`TA
`
`PACKAGE
`
`-40°C to 85°C
`
`PLASTIC HTSSOP
`PowerPAD (PWP)
`
`PLASTIC QUAD FLAT
`PACK (QFN)
`
`ORDERING INFORMATION(1)
`
`ORDERABLE PART
`NUMBER
`
`PINS
`
`TPS51116PWP
`TPS51116PWPR
`TPS51116PWPRG4
`TPS51116RGE
`
`TPS51116RGER
`
`TPS51116RGET
`
`20
`
`24
`
`OUTPUT
`SUPPLY
`
`Tube
`Tape-and-reel
`Tape-and-reel
`Tube
`Large
`tape-and-reel
`Small
`tape-and-reel
`
`MINIMUM
`ORDER
`QUANTITY
`70
`2000
`2000
`90
`
`3000
`
`250
`
`(1) All packaging options have Cu NIPDAU lead/ball finish.
`
`ABSOLUTE MAXIMUM RATINGS(1)
`over operating free-air temperature range unless otherwise noted
`
`VIN
`
`Input voltage range
`
`VOUT Output voltage range
`
`VBST
`VBST wrt LL
`CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET,
`V5FILT
`PGND, VTTGND, CS_GND
`DRVH
`LL
`COMP, DRVL, PGOOD, VTT, VTTREF
`Operating ambient temperature range
`Storage temperature
`
`TPS51116
`-0.3 to 36
`-0.3 to 6
`
`-0.3 to 6
`
`-0.3 to 0.3
`-1.0 to 36
`-1.0 to 30
`-0.3 to 6
`-40 to 85
`-55 to 150
`
`UNITS
`
`V
`
`V
`
`°C
`
`TA
`Tstg
`(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
`only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
`conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
`values are with respect to the network ground terminal unless otherwise noted.
`
`DISSIPATION RATINGS
`
`PACKAGE
`
`20-pin PWP
`24-pin RGE
`
`TA < 25°C POWER RATING
`(W)
`
`2.53
`2.20
`
`DERATING FACTOR ABOVE TA =
`25°C
`(mW/°C)
`25.3
`22.0
`
`TA = 85°C POWER RATING
`(W)
`
`1.01
`0.88
`
`2
`
`Submit Documentation Feedback
`
`Copyright © 2004–2008, Texas Instruments Incorporated
`
`Product Folder Link(s): TPS51116
`
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`
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`

`TPS51116
`
`www.ti.com............................................................................................................................................................... SLUS609G–MAY 2004–REVISED JUNE 2008
`RECOMMENDED OPERATING CONDITIONS
`
`Supply voltage, V5IN, V5FILT
`
`Voltage range
`
`Operating free-air temperature, TA
`
`VBST, DRVH
`LL
`VLDOIN, VTT, VTTSNS, VDDQSNS
`VTTREF
`PGND, VTTGND, CS_GND
`S3, S5, MODE, VDDQSET, CS, COMP, PGOOD,
`DRVL
`
`MIN
`4.75
`-0.1
`-0.6
`-0.1
`-0.1
`-0.1
`
`-0.1
`
`-40
`
`UNIT
`V
`
`V
`
`MAX
`5.25
`34
`28
`3.6
`1.8
`0.1
`
`5.25
`
`85
`
`°C
`
`Copyright © 2004–2008, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`3
`
`Product Folder Link(s): TPS51116
`
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`TPS51116
`
`SLUS609G–MAY 2004–REVISED JUNE 2008............................................................................................................................................................... www.ti.com
`ELECTRICAL CHARACTERISTICS
`over operating free-air temperature range, VV5IN = 5 V(1), VLDOIN is connected to VDDQ output (unless otherwise noted)
`PARAMETER
`TEST CONDITIONS
`MIN
`TYP
`MAX
`UNIT
`SUPPLY CURRENT
`
`IV5IN1
`
`IV5IN2
`
`Supply current 1, V5IN(1)
`
`Supply current 2, V5IN(1)
`
`Supply current 3, V5IN(1)
`
`IV5IN3
`Shutdown current, V5IN(1)
`IV5INSDN
`Supply current 1, VLDOIN
`IVLDOIN1
`Supply current 2, VLDOIN
`IVLDOIN2
`Standby current, VLDOIN
`IVLDOINSDN
`VTTREF OUTPUT
`Output voltage, VTTREF
`VVTTREF
`
`VVTTREFTOL
`
`Output voltage tolerance
`
`VVTTREFSRC
`VVTTREFSNK
`VTT OUTPUT
`
`Source current
`Sink current
`
`TA = 25°C, No load, VS3 = VS5 = 5 V,
`COMP connected to capacitor
`TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
`COMP connected to capacitor
`TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
`VCOMP = 5 V
`TA = 25°C, No load, VS3 = VS5 = 0 V
`TA = 25°C, No load, VS3 = VS5 = 5 V
`TA = 25°C, No load, VS3 = 5 V, VS5 = 0 V,
`TA = 25°C, No load, VS3 = VS5 = 0 V
`
`0.8
`
`300
`
`240
`
`0.1
`1
`0.1
`0.1
`
`-10 mA < IVTTREF < 10 mA, VVDDQSNS = 2.5 V,
`Tolerance to VVDDQSNS/2
`-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.8 V,
`Tolerance to VVDDQSNS/2
`-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.5 V,
`Tolerance to VVDDQSNS/2
`VVDDQSNS = 2.5 V, VVTTREF = 0 V
`VVDDQSNS = 2.5 V, VVTTREF = 2.5 V
`
`-20
`
`-18
`
`-15
`
`-20
`20
`
`VVDDQSNS/2
`
`-40
`40
`
`2
`
`mA
`
`600
`
`500
`
`1.0
`10
`10
`1.0
`
`20
`
`18
`
`15
`
`-80
`80
`
`20
`30
`40
`20
`30
`40
`20
`30
`40
`
`6.0
`
`3.0
`
`6.0
`
`3.0
`10
`1
`1
`
`m A
`
`V
`
`mV
`
`mA
`
`V
`
`mV
`
`A
`
`m A
`
`mA
`
`VVTTSNS
`
`Output voltage, VTT
`
`VVTTTOL25
`
`VTT output voltage tolerance
`to VTTREF
`
`VVTTTOL18
`
`VTT output voltage tolerance
`to VTTREF
`
`VVTTTOL15
`
`VTT output voltage tolerance
`to VTTREF
`
`IVTTTOCLSRC
`
`Source current limit, VTT
`
`IVTTTOCLSNK
`
`Sink current limit, VTT
`
`IVTTLK
`IVTTBIAS
`IVTTSNSLK
`IVTTDisch
`
`Leakage current, VTT
`Input bias current, VTTSNS
`Leakage current, VTTSNS
`
`Discharge current, VTT
`
`VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V
`VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V
`VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.5 V
`VS3 = VS5 = 5 V, IVTT = 0 A
`VS3 = VS5 = 5 V, |IVTT| < 1.5 A
`VS3 = VS5 = 5 V, |IVTT| < 3 A
`VS3 = VS5 = 5 V, IVTT = 0 A
`VS3 = VS5 = 5 V, |IVTT| < 1 A
`VS3 = VS5 = 5 V, |IVTT| < 2 A
`VS3 = VS5 = 5 V, IVTT = 0 A
`VS3 = VS5 = 5 V, |IVTT| < 1 A
`VS3 = VS5 = 5 V, |IVTT| < 2 A
`VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS =
`1.19 V, PGOOD = HI
`VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V
`VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS =
`1.31 V, PGOOD = HI
`VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ
`VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2
`VS3 = 5 V, VVTTSNS = VVDDQSNS /2
`VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2
`TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,
`VVTT = 0.5 V
`(1) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.
`
`1.25
`0.9
`0.75
`
`3.8
`
`2.2
`
`3.6
`
`2.2
`
`-0.1
`
`17
`
`-20
`-30
`-40
`-20
`-30
`-40
`-20
`-30
`-40
`
`3.0
`
`1.5
`
`3.0
`
`1.5
`-10
`-1
`-1
`
`10
`
`4
`
`Submit Documentation Feedback
`
`Copyright © 2004–2008, Texas Instruments Incorporated
`
`Product Folder Link(s): TPS51116
`
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`

`www.ti.com............................................................................................................................................................... SLUS609G–MAY 2004–REVISED JUNE 2008
`ELECTRICAL CHARACTERISTICS (continued)
`over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
`PARAMETER
`TEST CONDITIONS
`MIN
`TYP
`MAX
`UNIT
`VDDQ OUTPUT
`
`TPS51116
`
`TA = 25°C, VVDDQSET = 0 V, No load
`0°C ≤ TA≤ 85°C, VVDDQSET = 0 V, No load (2)
`-40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load (2)
`TA = 25°C, VVDDQSET = 5 V, No load(2)
`0°C ≤ TA≤ 85°C, VVDDQSET = 5V, No load(2)
`-40°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2)
`-40°C ≤ TA ≤ 85°C, Adjustable mode, No
`load(2)
`TA = 25°C, Adjustable mode
`VDDQSET regulation voltage 0°C ≤ TA≤ 85°C, Adjustable mode
`-40°C ≤ TA ≤ 85°C, Adjustable mode
`VVDDQSET = 0 V
`Input impedance, VDDQSNS VVDDQSET = 5 V
`Adjustable mode
`VVDDQSET = 0.78 V, COMP = Open
`VVDDQSET = 0.78 V, COMP = 5 V
`VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
`VMODE = 0 V
`VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
`VMODE = 0.5 V
`
`Output voltage, VDDQ
`
`Input current, VDDQSET
`
`Discharge current, VDDQ
`
`Discharge current, VLDOIN
`
`IVLDOINDisch
`TRANSCONDUCTANCE AMPLIFIER
`gm
`Gain
`COMP maximum sink
`current
`COMP maximum source
`current
`
`VVDDQ
`
`VVDDQSET
`
`RVDDQSNS
`
`IVDDQSET
`
`IVDDQDisch
`
`ICOMPSNK
`
`ICOMPSRC
`
`2.465
`2.457
`2.440
`1.776
`1.769
`1.764
`
`0.75
`
`742.5
`740.2
`738.0
`
`10
`
`240
`
`1.31
`
`1.18
`
`-6
`
`2.535
`2.543
`2.550
`1.824
`1.831
`1.836
`
`3.0
`
`757.5
`759.8
`762.0
`
`360
`
`1.37
`
`1.24
`
`6
`
`6
`3
`6
`3
`
`2.500
`2.500
`2.500
`1.800
`1.800
`1.800
`
`750.0
`750.0
`750.0
`215
`180
`460
`-0.04
`-0.06
`
`40
`
`700
`
`300
`
`13
`
`-13
`
`1.34
`
`1.21
`
`520
`125
`100
`350
`
`0
`
`3
`0.9
`3
`0.9
`10
`20
`
`V
`
`mV
`
`kΩ
`
`m A
`
`mA
`
`m S
`
`m A
`
`V
`
`ns
`
`mV
`
`Ω
`
`ns
`
`TA = 25°C
`VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
`VVDDQSNS = 2.7 V, VCOMP = 1.28 V
`VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
`VVDDQSNS = 2.3 V, VCOMP = 1.28 V
`VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
`VVDDQSNS = 2.3 V, VCS = 0 V
`VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
`VVDDQSNS = 2.7 V, VCS = 0 V
`
`VIN = 12 V, VVDDQSET = 0 V
`VIN = 12 V, VVDDQSNS = 0 V
`TA = 25°C(2)
`TA = 25°C(2)
`
`Source, IDRVH = -100 mA
`Sink, IDRVH = 100 mA
`Source, IDRVL = -100 mA
`Sink, IDRVL = 100 mA
`LL-low to DRVL-on (2)
`DRVL-off to DRVH-on(2)
`
`VCOMPHI
`
`COMP high clamp voltage
`
`COMP low clamp voltage
`
`VCOMPLO
`DUTY CONTROL
`Operating on-time
`TON
`TON0
`Startup on-time
`TON(min)
`Minimum on-time
`TOFF(min)
`Minimum off-time
`ZERO CURRENT COMPARATOR
`Zero current comparator
`VZC
`offset
`OUTPUT DRIVERS
`
`RDRVH
`
`RDRVL
`
`TD
`
`DRVH resistance
`
`DRVL resistance
`
`Dead time
`
`(2) Ensured by design. Not production tested.
`
`Copyright © 2004–2008, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`5
`
`Product Folder Link(s): TPS51116
`
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`

`TPS51116
`
`SLUS609G–MAY 2004–REVISED JUNE 2008............................................................................................................................................................... www.ti.com
`ELECTRICAL CHARACTERISTICS (continued)
`over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
`PARAMETER
`TEST CONDITIONS
`MIN
`TYP
`MAX
`UNIT
`INTERNAL BST DIODE
`Forward voltage
`VFBST
`IVBSTLK
`PROTECTIONS
`
`VV5IN-VBST , IF = 10 mA, TA = 25°C
`VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V,
`TA = 25°C
`
`0.7
`
`0.8
`
`0.1
`
`0.9
`
`1.0
`
`V
`m A
`
`VBST leakage current
`
`VOCL
`
`ITRIP
`
`Current limit threshold
`
`Current sense sink current
`
`TCITRIP
`
`VOCL(off)
`
`TRIP current temperature
`coefficient
`Overcurrent protection
`COMP offset
`Current limit threshold setting
`VR(trip)
`range
`POWERGOOD COMPARATOR
`
`VPGND-CS , PGOOD = HI, VCS < 0.5 V
`VPGND-CS , PGOOD = LO, VCS < 0.5 V
`TA = 25°C, VCS > 4.5 V, PGOOD = HI
`TA = 25°C, VCS > 4.5 V, PGOOD = LO
`RDS(on) sense scheme, On the basis
`of TA = 25°C (3)
`(VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV,
`VCS > 4.5 V(3)
`(3)(4)
`VV5IN-CS
`
`50
`20
`9
`4
`
`-5
`
`30
`
`93%
`103%
`
`2.5
`80
`
`3.7
`0.2
`4.7
`
`0.08
`3.5
`2.2
`
`-1
`-1
`
`110%
`
`60
`30
`10
`5
`
`4500
`
`0
`
`95%
`105%
`5%
`7.5
`130
`
`4.0
`0.3
`
`0.15
`4.0
`
`0.2
`
`115%
`5%
`
`1.5
`
`70%
`10%
`
`32
`
`1007
`
`160
`10
`
`70
`40
`11
`6
`
`5
`
`150
`
`97%
`107%
`
`200
`
`4.3
`0.4
`
`0.1
`0.25
`4.5
`
`0.3
`
`1
`1
`
`120%
`
`mV
`
`m A
`
`ppm/°C
`
`mV
`
`mA
`m s
`
`V
`
`m A
`
`m s
`
`cycle
`
`°C
`
`VTVDDQPG
`
`VUVV5IN
`
`VTHMODE
`
`MODE threshold
`
`VTHVDDQSET
`
`VDDQSET threshold voltage
`
`PG in from lower
`VDDQ powergood threshold PG in from higher
`PG hysteresis
`VVTT = 0 V, VPGOOD = 0.5 V
`PGOOD sink current
`IPG(max)
`Delay for PG in
`PGOOD delay time
`TPG(del)
`UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD
`Wake up
`V5IN UVLO threshold
`voltage
`Hysteresis
`No discharge
`Non-tracking discharge
`2.5 V output
`1.8 V output
`S3, S5
`High-level input voltage
`VIH
`S3, S5
`Low-level input voltage
`VIL
`S3, S5
`Hysteresis voltage
`VIHYST
`S3, S5, MODE
`Logic input leakage current
`VINLEAK
`VDDQSET
`Input leakage/ bias current
`VINVDDQSET
`UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
`OVP detect
`VDDQ OVP trip threshold
`voltage
`Hysteresis
`VDDQ OVP propagation
`delay (3)
`
`VOVP
`
`TOVPDEL
`
`VUVP
`
`Output UVP trip threshold
`
`Output UVP propagation
`TUVPDEL
`delay(3)
`Output UVP enable delay(3)
`TUVPEN
`THERMAL SHUTDOWN
`
`TSDN
`
`Thermal SDN threshold (3)
`
`UVP detect
`Hysteresis
`
`Shutdown temperature
`Hysteresis
`
`(3) Ensured by design. Not production tested.
`(4) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.
`
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`TPS51116
`
`www.ti.com............................................................................................................................................................... SLUS609G–MAY 2004–REVISED JUNE 2008
`DEVICE INFORMATION
`
`TERMINAL
`
`NO.
`
`PWP
`
`RGE
`
`8
`
`15
`
`19
`17
`5
`-
`
`18
`
`6
`-
`
`16
`
`13
`
`11
`12
`14
`
`-
`
`20
`10
`
`9
`
`1
`2
`3
`7
`
`4
`
`6
`
`16
`
`21
`19
`3
`17
`
`20
`
`4
`7,12
`
`18
`
`13
`
`10
`11
`15
`
`14
`
`22
`9
`
`8
`
`23
`24
`1
`5
`
`2
`
`NAME
`
`COMP
`
`CS
`
`DRVH
`DRVL
`GND
`CS_GND
`
`LL
`
`MODE
`NC
`
`PGND
`
`PGOOD
`
`S3
`S5
`V5IN
`
`V5FILT
`
`VBST
`VDDQSET
`
`VDDQSNS
`
`VLDOIN
`VTT
`VTTGND
`VTTREF
`
`VTTSNS
`
`I/O
`
`I/O
`
`I/O
`
`O
`O
`-
`
`I/O
`
`I
`
`-
`
`O
`
`I
`I
`I
`
`I
`
`I/O
`I
`
`I/O
`
`I
`O
`-
`O
`
`I
`
`TERMINAL FUNCTIONS
`
`DESCRIPTION
`
`Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable
`gm amplifier and use D-CAP™ mode.
`Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip
`voltage setting input for RDS(on) current sense scheme if connected to V5IN (PWP), V5FILT
`(RGE) through the voltage setting resistor.
`Switching (top) MOSFET gate drive output.
`Rectifying (bottom) MOSFET gate drive output.
`Signal ground. Connect to minus terminal of the VTT LDO output capacitor.
`Current sense comparator input (+) and ground for powergood circuit.
`Switching (top) MOSFET gate driver return. Current sense comparator input (-) for RDS(on)
`current sense.
`Discharge mode setting pin. See VDDQ and VTT Discharge Control section.
`No connect.
`Ground for rectifying (bottom) MOSFET gate driver (PWP, RGE). Also current sense
`comparator input(+) and ground for powergood circuit (PWP).
`Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the
`target range.
`S3 signal input.
`S5 signal input.
`5-V power supply input for internal circuits (PWP) and MOSFET gate drivers (PWP, RGE).
`Filtered 5-V power supply input for internal circuits. Connect R-C network from V5IN to
`V5FILT.
`Switching (top) MOSFET driver bootstrap voltage input.
`VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.
`VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge
`current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for
`VDDQ output if VDDQSET pin is connected to V5IN or GND.
`Power supply for the VTT LDO.
`Power output for the VTT LDO.
`Power ground output for the VTT LDO.
`VTTREF buffered reference output.
`Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output
`capacitor.
`
`Copyright © 2004–2008, Texas Instruments Incorporated
`
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`TPS51116
`
`SLUS609G–MAY 2004–REVISED JUNE 2008............................................................................................................................................................... www.ti.com
`
`8
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`
`Product Folder Link(s): TPS51116
`
`RGE PACKAGE
`(BOTTOM VIEW)
`
`COMP
`
`VTTREF
`
`MODE
`
`GND
`
`VTTSNS
`
`VTTGND
`
`NC
`
`VDDQSNS
`
`VDDQSET
`
`7 8 9
`
`2
`
`3
`
`4
`
`5
`
`6
`
`1
`24
`
`23
`
`22
`
`21
`
`20
`
`10
`
`11
`
`S3
`
`S5
`
`NC
`
`19
`12
`18 17 16 15 14 13
`
`PGOOD
`
`V5FILT
`
`V5IN
`
`CS
`
`CS_GND
`
`PGND
`
`PWP PACKAGE
`(TOP VIEW)
`
`20
`19
`18
`17
`16
`15
`14
`13
`12
`11
`
`VBST
`DRVH
`LL
`DRVL
`PGND
`CS
`V5IN
`PGOOD
`S5
`S3
`
`VTT
`
`VLDOIN
`
`VBST
`
`DRVH
`
`LL
`
`DRVL
`
`1 2 3 4
`
`
`
`5 6 7 8 9 1
`
`0
`
`VLDOIN
`VTT
`VTTGND
`VTTSNS
`GND
`MODE
`VTTREF
`COMP
`VDDQSNS
`VDDQSET
`
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`www.ti.com............................................................................................................................................................... SLUS609G–MAY 2004–REVISED JUNE 2008
`
`FUNCTIONAL BLOCK DIAGRAM (PWP)
`
`TPS51116
`
`Copyright © 2004–2008, Texas Instruments Incorporated
`
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`TPS51116
`
`SLUS609G–MAY 2004–REVISED JUNE 2008............................................................................................................................................................... www.ti.com
`
`FUNCTIONAL BLOCK DIAGRAM (RGE)
`
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`TPS51116
`
`www.ti.com............................................................................................................................................................... SLUS609G–MAY 2004–REVISED JUNE 2008
`DETAILED DESCRIPTION
`The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a
`10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin
`HTSSOP package or a 24-pin QFN package. Each of these rails generates VDDQ, VTTREF and VTT that
`required with DDR/DDR2/DDR3 memory systems. The switch mode power supply (SMPS) portion employs
`external N-channel MOSFETs to support high current for DDR/DDR2/DDR3 memory’s VDD/VDDQ. The preset
`output voltage is selectable from 2.5 V or 1.8 V. User defined output voltage is also possible and can be
`adjustable from 0.75 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS runs an adaptive
`on-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiency
`down to several mA. Current sensing scheme uses either RDS(on) of the external rectifying MOSFET for a
`low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying MOSFET for more
`accurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate one-half VDDQ for the
`10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT LDO can source and sink
`up to 3-A peak current with only 20-m F (two 10-m F in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2
`within 1% of VDDQ. VTT output tracks VTTREF within 20 mV at no load condition while 40 mV at full load. The
`LDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin. This
`helps reducing power dissipation in sourcing phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2
`specifications at S3/S5 sleep state (see Table 2). The part has two options of output discharge function when
`both VTT and VDDQ are disabled. The tracking discharge mode discharges VDDQ and VTT outputs through the
`internal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking
`discharge mode discharges outputs using internal discharge MOSFETs which are connected to VDDQSNS and
`VTT. The current capability of these discharge FETs are limited and discharge occurs more slowly than the
`tracking discharge. These discharge functions can be disabled by selecting non-discharge mode.
`
`VDDQ SMPS, Dual PWM Operation Modes
`The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller.
`It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ mode
`uses internal compensation circuit and is suitable for low external component count configuration with an
`appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external
`compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as
`ceramic or specialty polymer capacitors.
`These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN,
`TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage is
`monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the
`output of
`the internal resistor divider inside VDDQSNS pin.
`If an external resistor divider is connected to
`VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section).
`At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET
`is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by VIN and
`VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (see
`PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedback
`information indicates insufficient output voltage and inductor current information indicates below the overcurrent
`limit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or
`the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifying
`MOSFET is turned off when inductor current information detects zero level. This enables seamless transition to
`the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load
`current.
`level
`the transconductance amplifier generates a target current
`In the current mode control scheme,
`corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During
`the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and
`when the inductor current signal comes lower than the target current level, the comparator provides SET signal
`to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support
`various types of output MOSFETs and capacitors. In the D-CAP™ mode, the transconductance amplifier is
`disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference
`during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides
`SET signal to initiate the next ON state.
`
`Copyright © 2004–2008, Texas Instruments Incorporated
`
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`TPS51116
`
`SLUS609G–MAY 2004–REVISED JUNE 2008............................................................................................................................................................... www.ti.com
`VDDQ SMPS, Light Load Condition
`TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This
`reduction of
`frequency is achieved smoothly and without
`increase of VOUTripple or load regulation. Detail
`operation is described as follows. As the output current decreases from heavy load condition, the inductor current
`is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary
`between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when
`this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous
`conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next
`ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current
`increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor
`current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the
`threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1:
`
`(1)
`
`where
`•
`f is the PWM switching frequency (400 kHz)
`Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
`decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is 40 kHz at
`IOUT(LL)/10 and 4 kHz at IOUT(LL)/100.
`Low-Side Driver
`The low-side driver is designed to drive high-current, low-RDS(on), N-channel MOSFET(s). The drive capability is
`represented by its internal resistance, which are 3 Ω for V5IN to DRVL and 0.9 Ω for DRVL to PGND. A
`dead-time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and
`bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drive
`current is supplied by an input capacitor connected between V5IN and GND. The average drive current is equal
`to the gate charge at VGS = 5 V times switching frequency. This gate drive current as well as the high-side gate
`drive current times 5 V makes the driving power which needs to be dissipated from TPS51116 package.
`
`High-Side Driver
`The high-side driver is designed to drive high-current, low-RDS(on) N-channel MOSFET(s). When configured as a
`floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the
`gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied by the flying
`capacitor between VBST and LL pins. The drive capability is represented by its internal resistance, which are 3 Ω
`for VBST to DRVH and 0.9 Ω for DRVH to LL.
`
`Current Sensing Scheme
`In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor
`sensing and MOSFET RDS(on) sensing. For resistor sensing scheme, an appropriate current sensing resistor
`should be connected between the source terminal of the bottom MOSFET and PGND. CS pin is connected to the
`MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin.
`For RDS(on) sensing scheme, CS pin should be connected to V5IN (PWP), or V5FILT (RGE) through the trip
`voltage setting resistor, RTRIP. In this scheme, CS terminal sinks 10-m A ITRIP current and the trip level is set to the
`voltage across the RTRIP. The inductor current is monitored by the voltage between PGND pin and LL pin so that
`LL pin should be connected to the drain terminal of the bottom MOSFET. ITRIP has 4500ppm/°C temperature
`slope to compensate the temperature dependency of the RDS(on). In either scheme, PGND is used as the positive
`current sensing node so that PGND should be connected to the proper current sensing device, i.e. the sense
`resistor or the source terminal of the bottom MOSFET.
`
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`
`IOUT(LL) +
`
`1
`2 L f
`
`
`
`(VIN * VOUT) VOUT
`VIN
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`www.ti.com............................................................................................................................................................... SLUS609G–MAY 2004–REVISED JUNE 2008
`PWM Frequency and Adaptive On-Time Control
`TPS51116 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.
`However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output
`voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and
`proportional to the output voltage so that the duty ratio is kept as VOUT/VIN technically with the same cycle time.
`Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during
`the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In
`order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output
`becomes 750 mV or larger.
`
`VDDQ Output Voltage Selection
`TPS51116 can be used for both of DDR (VVDDQ = 2.5 V) and DDR2 (VVDDQ = 1.8 V) power supply and adjustable
`output voltage (0.75 V < VVDDQ < 3 V) by connecting VDDQSET pin as shown in Table 1. Use adjustable output
`voltage scheme for DDR3 application.
`
`VDDQSET
`GND
`V5IN
`FB Resistors
`RUP= RDOWN=75 kΩ
`FB Resistors
`
`Table 1. VDDQSET and Output Voltages
`VDDQ (V)
`VTTREF and VTT
`2.5
`VVDDQSNS/2
`1.8
`VVDDQSNS/2
`1.5
`VVDDQSNS/2
`
`NOTE
`DDR
`DDR2
`DDR3
`
`Adjustable
`
`VVDDQSNS/2
`
`0.75 V < VVDDQ < 3 V(1)
`
`VTT Linear Regulator and VTTREF
`TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking
`current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic
`capacitors are enough to keep tracking the VTTREF within 40 mV at all conditions including fast load transient.
`To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should
`be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable
`operation, total capacitance of the VTT output terminal can be equal to or greater than 20 m F. It is recommended
`to attach two 10-m F ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output
`capacitor is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input to achieve loop
`stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by
`the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator
`also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-m F ceramic capacitor for
`stable operation.
`
`Outputs Management by S3, S5 Control
`In the DDR/DDR2/DDR3 memory applications, it is important to keep VDDQ always higher than VTT/VTTREF
`including both start-up and shutdown. TPS51116 provides this management by simply connecting both S3 and
`S5 terminals to the sleep-mode signals such as SLP_S3 and SLP_S5 in the not