FBDIMM
`
`DDR2 SDRAM
`
`DDR2 Fully Buffered DIMM
`
`240pin FBDIMMs based on 1Gb C-die
`
`60FBGA with Lead-Free
`(RoHS compliant)
`
`INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
`AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
`CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
`WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
`OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
`GUARANTEE OR WARRANTY OF ANY KIND.
`
`1. For updates or additional information about Samsung products, contact your nearest Samsung office.
`
`2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
`applications where Product failure could result in loss of life or personal or physical harm, or any military or
`defense application, or any governmental procurement to which special terms or provisions may apply.
`
`* Samsung Electronics reserves the right to change products or specification without notice.
`
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`

`FBDIMM
`
`Table of Contents
`
`DDR2 SDRAM
`
`1.0 FEATURES .....................................................................................................................................4
`2.0 FBDIMM GENERALS .....................................................................................................................5
`2.1 FB-DIMM Operation Overview ..........................................................................................................5
`2.2 FB-DIMM Channel Frequency Scaling ...............................................................................................6
`2.3 FB-DIMM Clocking Scheme .............................................................................................................7
`2.4 FB-DIMM Protocol ..........................................................................................................................7
`2.5 Southbound Command Delivery ......................................................................................................8
`2.6 Basic Timing Diagram .....................................................................................................................9
`2.7 Advanced Memory Buffer Block Diagram ........................................................................................11
`2.8 Interfaces ....................................................................................................................................12
`3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE ...............12
`3.1 DDR2 Channel .............................................................................................................................12
`3.2 SMBus Slave Interface ..................................................................................................................12
`3.3 FBD Channel Latency ...................................................................................................................13
`3.4 Peak Theoretical Throughput .........................................................................................................13
`3.5 Hot-add .......................................................................................................................................13
`3.6 Hot remove ..................................................................................................................................13
`3.7 Hot replace ..................................................................................................................................13
`4.0 PIN CONFIGUREATION ..............................................................................................................14
`5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM ...............................................................................16
`5.1 2GB, 256Mx72 Module - M395T5663CZ4 ........................................................................................16
` 5.2 4GB, 512Mx72 Module - M395T5160CZ4.........................................................................................17
`6.0 ELECTRICAL CHARACTERISTICS ............................................................................................18
`7.0 CHANNEL INITIALIZATION ........................................................................................................24
`
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`FBDIMM
`
`Revision History
`Revision
`Month
`1.0
`March
`1.1
`April
`1.2
`April
`1.3
`April
`1.4
`June
`1.5
`November
`1.52
`April
`
`DDR2 SDRAM
`
`Year
`2007
`2007
`2007
`2007
`2007
`2007
`2008
`
`History
`
` - First Released.
` - Added 2GB density
` - Changed AMB device operation temperature symbol(Tj to Tcase)
` - Corrected Typo
` - Added 800 FBD
` - Changed Ordering Information and Added AL Feature
` - Corrected mechanical Dimension
`
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`FBDIMM
`
`1.0 FEATURES
`- 240pin fully buffered dual in-line memory module (FB-
`DIMM)
`- 3.2Gb/s, 4.0Gb/s, 4.8Gb/s link transfer rate
`- 1.8V +/- 0.1V Power Supply for DRAM VDD/VDDQ
`- 1.5V +0.075/-0.045V Power Supply for AMB VCC
`- 3.3V +/- 0.3V Power Supply for VDDSPD
`- Buffer Interface with high-speed differential point-to-
`point Link at 1.5 volt
`- Channel error detection & reporting
`- Channel fail over mode support
`
`DDR2 SDRAM
`
`- Serial presence detect with EEPROM
`- 8 Banks
`- Posted CAS
`- Programmable CAS Latency: 3, 4, 5, 6
`- Programmable Additive Latency: 0, 1, 2, 3, 4, 5
`- Automatic DDR2 DRAM bus and channel calibration
`- MBIST and IBIST Test functions
`- Hot add-on and Hot Remove Capability
`- Transparent mode for DRAM test support
`
`Table 1 : Ordering Information
`
`Part Number
`
`Density Organization
`
`Component Composition
`
`Number
`of Rank
`
`AMB
`
`Type of
`Heat
`Spreader
`
`Height
`
`2GB
`
`256M x 72
`
`M395T5663CZ4-CD56/E66
`M395T5663CZ4-CD51/E61
`M395T5160CZ4-CD56/E66/F76
`M395T5160CZ4-CD55/E65
`M395T5160CZ4-CD51/E61
`Note :
`1. “Z” of Part number(11th digit) stands for Lead-free products.
`2. The last digit stands for AMB.
`
`4GB
`
`512M x 72
`
`128Mx8(K4T1G084QC) *18EA
`
`256Mx4(K4T1G044QC) *36EA
`
`2
`
`2
`
`IDT C1
`IDT A1.5
`IDT C1
`Intel D1
`IDT A1.5
`
`Full Module
`
`30.35mm
`
`Table 2 : Performance range
`F7(DDR2-800)
`800
`6-6-6
`
`DDR2 DRAM Speed
`CL-tRCD-tRP
`
`E6(DDR2-667)
`667
`5-5-5
`
`D5(DDR2-533)
`533
`4-4-4
`
`Unit
`Mbps
`CK
`
`Table 3 : Address Configuration
`Organization
`128Mx8(1Gb) based Module
`256Mx4(1Gb) based Module
`
`Row Address
`A0-A13
`A0-A13
`
`Column Address
`A0-A9
`A0-A9, A11
`
`Bank Address
`BA0-BA2
`BA0-BA2
`
`Auto Precharge
`A10
`A10
`
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`FBDIMM
`
`2.0 FBDIMM GENERALS
`
`2.1 FB-DIMM Operation Overview
`
`DDR2 SDRAM
`
`FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth and
`scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited
`density build-up as channel speeds increase with memory system having the stub-bus architecture. FB-DIMM solution is intended to
`eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be connected serially to
`a given channel.
`
`Memory system architecture perspective, FB-DIMM is fully differentiated from Registered DIMM and Unbuffered DIMM. A lot of new
`technologies are integrated into this solution in order to achieve this scalable higher speed memory solution. Serial link interface with
`packet data format and dedicated read/write paths are key attribute in FB-DIMM protocol. Point to Point interconnect with fully differential
`signaling and de-emphasis scheme are key attribute in FBD channel link. Clock recovery by using data stream is key attribute in FBD
`clocking. FB-DIMM supports both clock resync and resampling mode options. CRC (Cyclic Redundancy Check) bits are transferred with
`data stream for reliability at high speed data transaction. Failover mechanism supports system running with dynamic IO failure. Finally all
`FB-DIMM is connected in daisy chain manner. Thus, every interconnection between AMB (advanced memory buffer) to AMB, AMB to
`Host and AMB to DRAM, is point to point interconnection which allows higher data transfer bandwidth.
`
`Figure 1 shows a lot of new technologies integrated with FBD solution.
`
`Figure 1 : FB-DIMM Memory System Overview
`
`Two unidirectional links
`- Northbound
`- Southbound
`
`Protocol Packet
`ADDR.CMD, DATA
`
`Host
`
`SB (ADDR, CMD, Wdata)
`
`NB(Rdata)
`
`DRAM
`
`DRAM
`
`DQs ADDR
`CMD
`AMB
`
`Rx
`Tx
`
`CLK
`
`Tx
`Rx
`
`Clk_Ref
`
`P2P Interconnect
`- LVDS
`- De-Emphasis
`
`Reliability
`- CRC fail-over Clock Recovery
`
`Clock
`
`DRAM
`
`DRAM
`
`FIFO
`Buffer
`
`Rx
`Tx
`
`DQs
`
`Tx
`Rx
`
`AMB
`ADDR
`CMD CLK
`
`Daisy Chain
`Connection
`Upto 8 AMB
`
`DIMM Topology
`Fly-by CLK, CMD
`
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`
`2.2 FB-DIMM Channel Frequency Scaling
`
`DDR2 SDRAM
`
`There are many frequency parameters including reference clock frequency, DRAM clock frequency, DRAM data transfer rate, channel
`transfer rate and channel unit interval. All of frequency parameters are scaled with a certain gear ratio. External clock source provides
`reference clock input to AMB and Host. External clock source is relatively slower than channel and DRAM frequency. Thus, AMB dou-
`bles external clock input and generates clock inputs to DRAMs. DRAM use clock input from AMB which is two times faster than refer-
`ence clock for DRAM operation. DRAM data transfer rate is two times faster than DRAM clock input with nature of double data rate
`operation and four times faster than external clock source. Channel speed is represented by unit interval - average time interval between
`voltage transitions of a signal in the FBD channel. It is six times faster than DRAM data transfer rate. For example, external clock source
`gives 6ns clock (166MHz), AMB doubles it and gives 3ns clock (333MHz) to DRAM and FBD channel communicate with unit interval -
`250ps (4.0Gbps transfer rate).
`
` Figure 2 shows frequency scale ratio over frequency parameters in FBD memory system.
`
`Figure 2 : FB-DIMM Speed Scaling
`DDR667 Ex.
`
`6ns
`
`3ns
`
`CLK_REF
`
`CLK_DRAM
`
`250ps
`
`Packet T/F
`
`12 UIs in one CLK_DRAM
`
`SB (ADDR, CMD, Wdata)
`
`Host
`
`NB(Rdata)
`
`Reference CLK
`
`Reference CLK
`
`Clock
`
`DRAM
`
`DRAM
`
`DQs ADDR
`CMD
`AMB
`
`Rx
`Tx
`
`CLK
`
`Tx
`Rx
`
`Clk_Ref
`
`DRAM
`
`DRAM
`
`DDR2-533
`DDR2-667
`DDR2-800
`
`UI
`312.5ps
`250ps
`208.33ps
`
`CLK_DRAM
`266MHz
`333MHz
`400MHz
`
`CLK_REF
`133MHz
`166MHz
`200MHz
`
`Frequency
`3.2Gb/s
`4.0Gb/s
`4.8Gb/s
`
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`
`2.3 FB-DIMM Clocking Scheme
`
`DDR2 SDRAM
`
`In FB-DIMM platform design, phase adjustment among reference clock inputs to each individual AMB and host is not taken account.
`Thus, clock synchronization is made by using both external reference clock and channel data stream in FB-DIMM memory system. Host
`and each individual AMB has a each individual IO basis clock recovery circuitry for channel data communication. It runs with inputs from
`PLL inside chip and data stream from the other AMB or Host. Because data stream itself involves data communication process, no sig-
`naling switching or data communication may loss clock synchronization between transmitter and receiver. Thus, min transition density is
`defined for this purpose. In FBD channel, a density of 6 transitions within 512 transfers or unit intervals (UI) on the channel is required for
`interpolator training.
`Figure 3 : FB-DIMM Clocking
`
`Min. Transition Density
`6 Transitions
`
`512 Transfers
`
`Using Reference CLK (Not in Phase)
`Adjust edge/phase by; Min. Transition Density
`
`Host
`
`SB (ADDR, CMD, Wdata)
`
`NB(Rdata)
`
`DRAM
`
`DRAM
`
`DQs ADDR
`CMD
`AMB
`
`Rx
`Tx
`
`CLK
`
`Tx
`Rx
`
`Clk_Ref
`
`Clock
`Recovery
`
`DRAM
`
`DRAM
`
`Reference CLK
`
`Clock
`
`2.4 FB-DIMM Protocol
`
`FB-DIMM channel has two unidirectional communication paths - south bound and north bound. South bound and north bound use phys-
`ically different signal path. South and north mean direction of signal transaction. Southbound means direction of signals running from the
`host controller toward the DIMMs. North is the opposite of south. Due to nature of memory operation, southbound carries information
`including command to DRAM, address to DRAM and write data to DRAM, while north bound carries read data from DRAM. In channel
`protocol point of view, southbound and northbound have different data frame formats and frame format size is optimized to ratio of read
`and write. Data transfer perspective, read data transfer rate of north bound is twice faster than write data transfer. Higher channel utiliza-
`tion achieves with asymmetric read and write data transfer rate.
`
`Figure 4 : Southbound / Northbound Frame format
`Sout bound
`
`Command (with Address)
`
`A CMD
`
`Command (with Address)
`or Write Data in
`
`B CMD
`
`Northbound
`
`R_Data(x72bits)
`
`Command (with Address)
`or Write Data in
`
`C CMD
`
`R_Data(x72bits)
`
`Southbound consists of 10 differential signal pairs (lane), physically 20 signaling line. Southbound Format has 10x12 (10 IO (or Lane) x
`12 IO switching) frame format, which deliver 10x12 bit information per one DRAM clock. One south bound frame is divided into three
`command slot. See figure 5. Command slot A delivers command (with address). Command slot B and C delivers command (with
`address) or write data into DRAM.
`
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`FBDIMM
`
`DDR2 SDRAM
`
`CLK_REF
`
`CLK_DRAM
`
`Packet T/F
`
`A CMD
`
`B CMD
`
`C CMD
`
`x10 bits
`
`12 transfers
`
`Figure 5 : FBDIMM Command Encoding & SB Frame
`Southbound Command Frame Format*
`Bit
`
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`aE0 aE7 aE8 F0=0 aC20 aC16 aC12 aC8 aC4 aC0
`0
`1
`aE1 aE6 aE9 F1=0 aC21 aC17 aC13 aC9 aC5 aC1
`2
`aE2 aE5 aE10 aE13 aC22 aC18 aC14 aC10 aC6 aC2
`3
`aE3 aE4 aE11 aE12 aC23 aC19 aC15 aC11 aC7 aC3
`4 FE21
`0
`0
`0
`bC20 bC16 bC12 bC8 bC4 bC0
`5 FE20
`0
`0
`0
`bC21 bC17 bC13 bC9 bC5 bC1
`6 FE19
`0
`0
`0
`bC22 bC18 bC14 bC10 bC6 bC2
`7 FE18
`0
`0
`0
`bC23 bC19 bC15 bC11 bC7 bC3
`8 FE17
`0
`0
`0
`cC20 cC16 cC12 cC8 cC4 cC0
`9 FE16
`0
`0
`0
`cC21 cC17 cC13 cC9 cC5 cC1
`10 FE15
`0
`0
`0
`cC22 cC18 cC14 cC10 cC6 cC2
`11 FE14
`0
`0
`0
`cC23 cC19 cC15 cC11 cC7 cC3
`
`Transfer
`
`FE0 FE7 FE11
`FE1 FE6 FE10
`FE2 FE5 FE9 FE13
`FE3 FE4 FE8 FE12
`
`Note :
`1. aE[0~12] : CRC Checksum of the A Command
`2. F[0~1] : Frame Type
`3. FE[0~21] : CRC Checksum of 72bit data
`4. CRC : Cyclic Redundancy Check
`
`16
`
`15
`
`14
`
`13
`
`12
`
`11
`
`10
`
`DRAM Cmnds
`
`21
`22
`23
`DS2 DS1 DS0
`DS2 DS1 DS0
`DS2 DS1 DS0
`DS2 DS1 DS0
`DS2 DS1 DS0
`DS2 DS1 DS0
`DS2 DS1 DS0
`
`DS2 DS1 DS0
`
`20
`1
`0
`0
`0
`0
`0
`0
`
`0
`
`17
`18
`19
`DRAM Addr RS
`1
`1
`RS
`1
`0
`RS
`0
`1
`RS
`0
`1
`RS
`0
`1
`RS
`0
`1
`RS
`
`0
`
`1
`
`RS
`
`7
`8
`9
`DRAM Bank & Address
`DRAM Bank & Address
`DRAM Bank & Address
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`
`X
`
`X
`X
`
`X
`
`X
`X
`
`X
`
`X
`X
`
`6
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`X
`X
`X
`X
`
`X
`
`X
`X
`
`X
`X
`X
`X
`
`X
`
`X
`X
`
`X
`X
`X
`X
`
`X
`
`X
`X
`
`X
`X
`X
`X
`
`X
`
`X
`X
`
`X
`X
`X
`X
`
`X
`
`X
`X
`
`X
`X
`X
`X
`
`X
`
`X
`X
`
`X
`X
`X
`X
`
`X
`
`X
`X
`
`1
`0
`1
`0
`
`1
`
`0
`X
`
`Activate
`Write
`Read
`Precharge All
`Precharge Single
`Auto (CBR) Refresh
`Enter Self Refresh
`Exit Self Refresh/
`Exit Power Down
`1
`0
`X
`X
`X
`X
`RS
`1
`0
`0
`DS2 DS1 DS0
`Enter Power Down
`reserved
`X
`X
`X
`0
`0
`1
`X
`X
`X
`X
`X
`0
`0
`Note : The values in “ X” fields in non-reserved commands above may be driven onto the DRAM device pins.
`
`X
`
`X
`X
`
`X
`
`X
`X
`DRAM Bank
`X
`X
`X
`X
`
`X
`
`X
`
`X
`
`X
`X
`
`X
`
`1
`1
`1
`1
`
`0
`
`1
`1
`0
`0
`
`1
`
`2.5 Southbound Command Delivery
`
`A DRAM command located in the "A" command may be delivered to the DRAM devices as soon as the 14-bit (10-bits in fail-over) CRC
`is checked. This minimizes DRAM access latency by allowing the command to be delivered after the first 4 transfers of the frame have
`been received. The "A" command is transferred immediately to the DRAM pins with minimum delay whereas the "B" and "C" command
`are delivered one DRAM clock later. To minimize memory access latency the read related Activate, Read (if the page is open) and
`explicit Precharge commands to a rank of DRAM devices should be placed in the "A" command, if possible. Figure 6 illustrates the deliv-
`ery of the three potential commands in a frame to three separate DRAM channels.
`
`Command "A" is delivered in this case to the DRAM devices on DIMM 3 as soon as the command can traverse the AMB buffer. The "B"
`and "C" commands are delayed and presented to two other DRAM channels on the following clock. See below figure7~10 for Basic
`Read & Write Operations
`
`Northbound consists of 14 differential signal pairs (lane), physically 28 signaling line. Southbound Format has 14x12 (14 IO (or Lane) x
`12 IO switching) frame format, which deliver 14x12 bit information per one DRAM clock. One north bound frame is divided into two. Both
`frame deliver read data from DRAM
`
`Figure 6 : FBDIMM Command Delivery Rules
`1
`2
`3
`4
`
`5
`
`FBD southbound
`cmd/data
`DIMM 1 cmd
`
`“A”
`“B”
`“C”
`
`DIMM 2 cmd
`
`DIMM 3 cmd
`
`DIMM 4 cmd
`FBD northbound
`cmd/data
`
`“A”
`
`“C”
`
`“B”
`
`1. CMD A transferred immediately
`2. CMD A, B, C cannot target the same DIMM
`3. Host is responsible for scheduling CMD
`
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`FBDIMM
`
`2.6 Basic Timing Diagram
`
`DDR2 SDRAM
`
`Figure 7 : Basic DRAM Read Data Transfers on FBD
`1
`2
`3
`4
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`FBD southbound
`cmd/data
`
`ACT1
`NOP
`NOP
`
`RD1
`NOP
`NOP
`
`ACT1
`
`RD1
`
`DIMM 1 cmd
`
`DIMM 1 data
`
`DIMM 2 cmd
`
`DIMM 2 data
`FBD northbound
`data
`
`Figure 8 : Back to Back DRAM Read Data Transfers
`
`11
`
`22
`
`33
`
`44
`
`55
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`FBD southbound
`cmd/data
`
`ACT1
`NOP
`NOP
`
`ACT2
`NOP
`NOP
`
`RD1
`NOP
`NOP
`
`RD2
`NOP
`NOP
`
`ACT1
`
`RD1
`
`ACT2
`
`RD2
`
`DIMM 1 cmd
`
`DIMM 1 data
`
`DIMM 2 cmd
`
`DIMM 2 data
`FBD northbound
`data
`
`No Bubble
`
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`FBDIMM
`
`DDR2 SDRAM
`
`Figure 9 : Basic DRAM Write Data Transfers on FBD
`
`
`
`11
`
`
`
`22
`
`
`
`33
`
`
`
`44
`
`
`
`55
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`FBD southbound
`cmd/data
`
`ACT1
`NOP
`NOP
`
`NOP
`Wdata
`Wdata
`
`WR1
`Wdata
`Wdata
`
`NOP
`Wdata
`Wdata
`
`NOP
`Wdata
`Wdata
`
`SYNC
`1010
`0101
`
`DIMM 1 cmd
`
`DIMM 1 data
`
`DIMM 2 cmd
`
`DIMM 2 data
`FBD northbound
`data
`
`ACT1
`
`WR1
`
`Fixed fall through time
`
`Status
`
`Figure 10 : Simultaneous RD / WR Data Transfers
`
`11
`
`22
`
`33
`
`44
`
`55
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`FBD southbound
`cmd/data
`
`ACT1
`Wdata
`Wdata
`
`ACT2
`Wdata
`Wdata
`
`ACT3
`Wdata
`Wdata
`
`RD1
`Wdata
`Wdata
`
`WR2
`NOP
`NOP
`
`RD3
`NOP
`NOP
`
`SYNC
`1010
`0101
`
`ACT1
`
`ACT3
`
`RD1
`
`RD3
`
`ACT2
`
`WR2
`
`DIMM 1 cmd
`
`DIMM 1 data
`
`DIMM 2 cmd
`
`DIMM 2 data
`FBD northbound
`data
`
`Status
`
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`FBDIMM
`
`2.7 Advanced Memory Buffer Block Diagram
`
`Figure 11 : Advanced Memory Buffer Block Diagram
`
`Advance Memory Buffer
`Block Dlagram
`
`NORTH
`
`10x2
`Southbound
`Data In
`
`10x2
`Southbound
`Data Out
`
`DDR2 SDRAM
`
`1x2
`
`Ref Clock
`
`PLL
`
`Reset#
`
`Reset
`Control
`
`demux
`
`10*2
`
`Re-Time
`
`Re-synch
`
`Link Init SM
`and Control
`and CSRs
`
`Data Merge
`
`10*2
`
`PISO
`
`mux
`
`lnit
`patterns
`
`IBIST - RX
`
`IBIST - TX
`
`Command
`Decoder &
`CRC Check
`
`failover
`
`LAI Logic
`
`Thermal
`Sensor
`
`Core Control
`and CSRs
`
`LAI
`Controller
`
`Data CRC Gen
`& Read FIFO
`
`DRAM Cmd
`
`DDR State
`Controller
`and CSRs
`
`36
`deep
`Write
`Data
`FIFO
`
`External MEMBIST
`DDR calibration &
`DDR IOBIST/DFX
`
`Sync & ldie
`Pattern
`Generator
`
`NB LAI Buffer
`
`IBIST -TX
`
`IBIST - RX
`
`4
`
`4
`
`29
`
`29
`
`DRAM Clock
`
`DRAM Clock #
`
`DRAM Address /
`Command Copy 1
`
`DRAM Address /
`Command Copy 2
`
`72 + 18x2
`
`DRAM
`Data / strobe
`
`IOs
`DDR
`
`Cmd Out
`
`Data Out
`
`Data In
`
`mux
`
`mux
`
`SMbus
`
`SMbus
`Controller
`
`mux
`
`failover
`
`14*6*2
`
`PISO
`
`Data Merge
`
`Link lnit SM
`and Control
`and CSRs
`
`Re-synch
`
`Re-Time
`
`14*12
`
`demux
`
`Northbound
`Data Out
`
`14x2
`
`14x2
`
`Northbound
`Data In
`
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`FBDIMM
`
`DDR2 SDRAM
`
`2.8 Interfaces
`Figure12 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FBD links, one DDR2 channel and an SM-
`Bus interface. Each FBD link connects the Advanced Memory Buffer to a host memory controller or an adjacent FBD. The DDR2 channel
`supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM
`
`Figure 12 : Advanced Memory Buffer Interface Block Diagram
`
`MEMORY INTERFACE
`
`CHANNEL
`
`DDR2
`
`to optional next FBD
`
`econdary or
`
`SB FBD
`Out Link S
`
`AMB
`
`NB FBD
`In Link
`
`SMB
`
`NB FBD
`Out Link
`
`SB FBD
`In Link
`
`Host Direction
`
`Primary or
`
`The FBDIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel.
`The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound
`data path each DIMM receives the data and again redrives the data to the next DIMM until the last DIMM receives the data. The last DIMM
`in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). On the northbound data path each DIMM
`receives the data and re-drives the data to the next DIMM until the host is reached.
`
`3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE
`The Advanced Memory Buffer supports one FBD Channel consisting of two bidirectional link interfaces using high-speed differential point-
`to-point electrical signaling.
`The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM
`in the host direction. The southbound output link forwards this same data to the next FBD.
`The northbound input link is 14 lanes wide and carries read return data or status information from the next FBDIMM in the chain back
`towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or
`status information that is generated internally.
`
`3.1 DDR2 Channel
`The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two
`ranks of eight banks with 16 row/column request, 64 data signals, and eight check-bit signals. There are two copies of address and com-
`mand signals to support DIMM routing and electrical requirements. Four-transfer bursts are driven on the data and check-bit lines at 800
`MHz.
`Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware
`state machines using write/read trial and error (or equivalent implementation). Hardware aligns the read data and check-bits to a single
`core clock.
`The Advanced Memory Buffer provides four copies of the command clock phase references (CLK[3:0]) and write data/check-bit .
`
`3.2 SMBus Slave Interface
`The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration registers independent of the FBD
`link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100
`kHz. SMBus access to the Advanced Memory Buffer may be a requirement to boot a system. This provides a mechanism to set link
`strength, frequency and other parameters needed to insure robust operation given platform specific configurations. It is also required for
`diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the Advanced Memory
`Buffer to get its unique ID.
`
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`FBDIMM
`
`DDR2 SDRAM
`
`3.3 FBD Channel Latency
`FBD channel latency is measured from the time a read request is driven on the FBD channel pins to the time when the first 16 bytes (2nd
`chunk) of read completion data is sampled by the memory controller.
`When not using the Variable Read Latency capability, the latency for a specific FBDIMM on an FBD channel is always equal to the latency
`for any other FBDIMM on that channel. However, the latency for each FBDIMM in a specific configuration with some number of FBDIMMs
`installed may not be equal to the latency for each FBDIMM in a configuration with some different number of FBDIMMs installed.
`As more DIMMs are added to the FBD channel, additional latency is required to read from each DIMM on the channel. Because the FBD
`channel is based on the point-to-point interconnection of buffer components between DIMMs, memory requests are required to travel
`through N-1 buffers before reaching the Nth buffer. The result is that a four DIMM channel configuration will have greater idle read latency
`compared to a one DIMM channel configuration.
`The Variable Read Latency capability can be used to reduce latency for DIMMs closer to the host.
`The idle latencies listed in this section are representative of what might be achieved in typical AMB designs. Actual implementations with
`latencies less than the values listed will have higher application performance and vice versa.
`
`3.4 Peak Theoretical Throughput
`An FBD channel transfers read completion data on the FBD Northbound data connection. 144 bits of data are transferred for every FBD
`Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst
`of 8 from a single channel or a DRAM burst of four from two lock-stepped channels provides a total of 72 bytes of data (64 bytes plus 8
`bytes ECC).
`The FBD frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FBD channel clock to the DRAM command
`clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput as a single DRAM channel. For exam-
`ple, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data connection is 4.267 GB/sec.
`Write data is transferred on the FBD Southbound command and data connection, via Command+Wdata frames. 72 bits of data are trans-
`ferred for every FBD Command+Wdata frame. Two Command+Wdata frames match the 18-byte data transfer of an ECC DDR DRAM in
`a single DRAM command clock. A DRAM burst of 8 transfers from a single channel, or a burst of 4 from two lock-step channels provides
`a total of 72 bytes of data (64 bytes plus 8 bytes ECC).
`When the FBD frame rate matches the DRAM command clock, the Southbound command and data connection will exhibit one half the
`peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of
`the Southbound command and data connection is 2.133 GB/sec.
`The total peak theoretical throughput for a single FBD channel is defined as the sum of the peak theoretical throughput of the Northbound
`data connection and the Southbound command and data connection. When the FBD frame rate matches the DRAM command clock, this
`is equal to 1.5 times the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak
`theoretical throughput of a DDR2 533 channel would be 4.267 GB/sec, while the peak theoretical throughput of an FBD-533 channel would
`be 6.4 GB/sec
`
`3.5 Hot-add
`The FBDIMM channel does not provide a mechanism to automatically detect and report the addition of a new FBDIMM south of the cur-
`rently active last FBDIMM. It is assumed the system will be notified through some means of the addition of one or more new FBDIMMs so
`that specific commands can be sent to the host controller to initialize the newly added FBDIMM(s) and perform a hot-add reset to bring
`them into the channel timing domain. It should be noted that the power to the FBDIMM socket must be removed before a hot-add FBDIMM
`is inserted or removed. Applying or removing the power to a FBDIMM socket is a system platform function.
`
`3.6 Hot remove
`In order to accomplish removal of FBDIMMs, the host must perform a fast reset sequence targeted at the last FBDIMM that will be retained
`on the channel. The fast reset re-establishes the appropriate last FBDIMM so that the southbound transmission outputs of the last active
`FBDIMM and the southbound and northbound outputs of the FBDIMMs beyond the last active FBDIMM are disabled. Once the appropriate
`outputs are disabled, the system can coordinate the procedure to remove power in preparation for physical removal of the FBDIMM if need-
`ed. Note that the power to the FBDIMM socket must be removed before a hot-add FBDIMM is inserted or removed. Applying or removing
`the power to a FBDIMM socket is a system platform function.
`
`3.7 Hot replace
`Hot replace of FBDIMM is accomplished through combining the hot-remove and hotadd processes
`
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`

`FBDIMM
`
`4.0 PIN CONFIGUREATION
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`122
`
`123
`
`124
`
`125
`
`126
`
`127
`
`128
`
`32
`
`33
`
`34
`
`35
`
`36
`
`37
`
`38
`
`PN3
`VSS
`PN4
`
`PN4
`VSS
`PN5
`
`SN3
`VSS
`SN4
`
`SN4
`VSS
`SN5
`
`152
`
`153
`
`154
`
`155
`
`156
`
`157
`
`158
`
`62
`
`63
`
`64
`
`65
`
`66
`
`67
`
`68
`
`PN10
`VSS
`PN11
`
`PN11
`VSS
`
`DDR2 SDRAM
`
`Pin
`181
`
`182
`
`183
`
`184
`
`185
`
`186
`
`187
`
`188
`
`Back
`SN9
`VSS
`SN10
`
`SN10
`VSS
`SN11
`
`SN11
`VSS
`
`Pin
`91
`
`92
`
`93
`
`94
`
`95
`
`96
`
`97
`
`98
`
`99
`
`Front
`PS9
`VSS
`PS5
`
`PS5
`VSS
`PS6
`
`Pin
`211
`
`212
`
`213
`
`214
`
`215
`
`216
`
`217
`
`218
`
`219
`
`Back
`SS9
`VSS
`SS5
`
`SS5
`VSS
`SS6
`
`Table 4 : DDR2 240 Pin FBDIMM Configurations (Front side/Back side)
`Pin
`Front
`Pin
`Back
`Pin
`Front
`Pin
`Back
`Pin
`Front
`VDD
`VDD
`1
`121
`31
`PN3
`151
`SN3
`61
`PN9
`VDD
`VDD
`VSS
`VDD
`VDD
`PN10
`VSS
`VSS
`VDD
`VDD
`VDD
`VDD
`VDD
`VDD
`VSS
`VSS
`VCC
`VCC
`VCC
`VCC
`VSS
`VSS
`VCC
`VCC
`VCC
`VCC
`VSS
`VSS
`VTT
`VTT
`VID1
`VID0
`
`SN5
`VSS
`SN13
`
`SN13
`VSS
`VSS
`RFU*
`
`159
`
`160
`
`161
`
`162
`
`163
`
`164
`
`165
`
`166
`
`69
`
`70
`
`71
`
`72
`
`73
`
`74
`
`75
`
`KEY
`
`189
`
`190
`
`191
`
`192
`
`193
`
`194
`
`195
`
`VSS
`SS0
`
`SS0
`VSS
`SS1
`
`100
`
`101
`
`102
`
`103
`
`104
`
`105
`
`106
`
`PS6
`VSS
`PS7
`
`PS7
`VSS
`PS8
`
`PS8
`VSS
`RFU**
`
`SS6
`VSS
`SS7
`
`SS7
`VSS
`SS8
`
`SS8
`VSS
`RFU**
`
`220
`
`221
`
`222
`
`223
`
`224
`
`225
`
`226
`
`VSS
`PS0
`
`PS0
`VSS
`PS1
`
`129
`
`130
`
`131
`
`132
`
`133
`
`134
`
`135
`
`136
`
`PN5
`VSS
`PN13
`
`PN13
`VSS
`VSS
`RFU*
`
`39
`
`40
`
`41
`
`42
`
`43
`
`44
`
`45
`
`46
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`RESET
`VSS
`RFU**
`
`RFU**
`VSS
`PN0
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`DNU/M_Test
`VSS
`RFU**
`
`RFU**
`VSS
`SN0
`
`137
`
`138
`
`139
`
`140
`
`141
`
`142
`
`143
`
`144
`
`47
`
`48
`
`49
`
`50
`
`51
`
`52
`
`53
`
`54
`
`RFU*
`VSS
`VSS
`PN12
`
`PN12
`VSS
`PN6
`
`RFU*
`VSS
`VSS
`SN12
`
`SN12
`VSS
`SN6
`
`PS1
`VSS
`PS2
`
`PS2
`VSS
`PS3
`
`PS3
`VSS
`PS4
`
`196
`
`197
`
`198
`
`199
`
`200
`
`201
`
`202
`
`203
`
`SS1
`VSS
`SS2
`
`SS2
`VSS
`SS3
`
`SS3
`VSS
`SS4
`
`107
`
`108
`
`109
`
`110
`
`111
`
`112
`
`113
`
`114
`
`76
`
`77
`
`78
`
`79
`
`80
`
`81
`
`82
`
`83
`
`167
`
`168
`
`169
`
`170
`
`171
`
`172
`
`173
`
`174
`
`RFU**
`VSS
`SCK
`
`227
`
`228
`
`229
`
`230
`
`231
`
`232
`
`233
`
`234
`
`PN0
`VSS
`PN1
`
`PN1
`VSS
`PN2
`
`PN2
`VSS
`
`24
`
`25
`
`26
`
`27
`
`28
`
`29
`
`30
`
`SN0
`VSS
`SN1
`
`SN1
`VSS
`SN2
`
`SN2
`VSS
`
`145
`
`146
`
`147
`
`148
`
`149
`
`150
`
`55
`
`56
`
`57
`
`58
`
`59
`
`60
`
`PN6
`VSS
`PN7
`
`PN7
`VSS
`PN8
`
`PN8
`VSS
`PN9
`
`SN6
`VSS
`SN7
`
`SN7
`VSS
`SN8
`
`SN8
`VSS
`SN9
`
`175
`
`176
`
`177
`
`178
`
`179
`
`180
`
`PS4
`VSS
`VSS
`RFU*
`
`RFU*
`VSS
`VSS
`PS9
`
`204
`
`205
`
`206
`
`207
`
`208
`
`209
`
`210
`
`SS4
`VSS
`VSS
`RFU*
`
`RFU*
`VSS
`VSS
`SS9
`
`84
`
`85
`
`86
`
`87
`
`88
`
`89
`
`90
`
`115
`
`116
`
`117
`
`118
`
`119
`
`120
`
`RFU = Reserved Future Use.
`* These pin positions are reserved for forwarded clocks to be used in future module implementations
`** These pin positions are reserved for future architecture flexibility
`
`RFU**
`VSS
`VDD
`VDD
`VSS
`VDD
`VDD
`VDD
`VSS
`VDD
`VDD
`VTT
`SA2
`
`SDA
`
`SCL
`
`SCK
`VSS
`VDD
`VDD
`VDD
`VSS
`VDD
`VDD
`VTT
`VDDSPD
`SA0
`
`SA1
`
`235
`
`236
`
`237
`
`238
`
`239
`
`240
`
`1. The following signals are CRC bits and thus appear out of the normal sequence : PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN12, PS9/PS9, SS9/SS9.
`
` 14 of 28
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`
`

`

`FBDIMM
`Table 5 : Pin Description
`Pin Name
`Type
`SCK
`Input
`SCK
`Input
`PN[13:0]
`Output
`PN[13:0]
`Output
`PS[9:0]
`Input
`PS[9:0]
`Input
`
`Pin Description
`System Clock Input, positive line
`System Clock Input, negative line
`Primary northbound Data, positive lines
`Primary northbound Data, negative lines
`Primary Southbound Data, positive lines
`Primary Southbound Data, negative lines
`
`SN[13:0]
`
`Output
`
`Secondary Northbound Data, positive lines
`
`SN[13:0]
`
`Output
`
`Secondary Northbound Data, negative lines
`
`Secondary Southbound Data, positive lines
`Secondary Southbound Data, negative lines
`Serial Presence Detect (SPD) Clock Input
`SPD Data Input / Output
`SPD Address Inputs, also used to slelect the DIMM number in
`the AMB
`Voltage ID : These pins must be unconnected for DDR2 -
`based Fully Buffered DIMMs
`VID[0] is VDD value : OPEN = 1.8 V, GND = 1.5 V ; VID[1] is
`VCC value : OPEN = 1.5V, GND = 1.2V
`AMB reset signal
`
`Reserved for Future Use
`
`SS[9:0]
`SS[9:0]
`SCL
`SDA
`
`SA[2:0]
`
`VID[1:0]
`
`RESET
`
`RFU
`
`VCC
`
`VDD
`
`VTT
`VDDSPD
`
`Input
`Input
`Input
`Input
`
`Input
`
`NC
`
`Input
`
`RFU
`
`PWR
`
`PWR
`
`PWR
`PWR
`
`VSS
`
`GND
`
`DNU/M_Test
`
`DNU
`
`DDR2 SDRAM
`
`Pin Numbers
`
`228
`229
`22, 25, 28, 31, 34, 37, 40, 48, 51, 54, 57, 60, 63, 66
`23, 26, 29, 32, 35, 38, 41, 49, 52, 55, 58, 61, 64, 67
`70, 73, 76, 79, 82, 90, 93, 96, 99, 102
`71, 74, 77, 80, 83, 91, 94, 97, 100, 103
`142, 145, 148, 151, 154, 157, 160, 168, 171, 174, 177,
`180, 183, 186
`143, 146, 149, 152, 155, 1