JEDEC Standard No. 21C
`Page 4.20.11-1
`
`4.20.11 - 200-Pin DDR2 SDRAM Unbuffered SO-DIMM Design
`Specification
`
`PC2-6400/PC2-5300/PC2-4200/PC2-3200
`DDR2 Unbuffered SO-DIMM
`Reference Design Specification
`Revision 2.5
`July, 2008
`
`Netlist Inc.
`
`Release 18
`
`Revision 2.5
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`Downloaded by Marwan Fawal (mfawal@netlist.com) on Mar 21, 2023, 11:37 am PDT
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`

`JEDEC Standard No. 21C
`Page 4.20.11-2
`
`Contents
`
`Product Description ...................................................................................................................................4
`Product Family Attributes .......................................................................................................................4
`Raw Card Summary...............................................................................................................................5
`
`Environmental Requirements....................................................................................................................6
`Absolute Maximum Ratings ...................................................................................................................6
`
`Architecture.................................................................................................................................................6
`Pin Description .......................................................................................................................................6
`Input/Output Functional Description.......................................................................................................7
` DDR2 SDRAM SO-DIMM Pinout ..........................................................................................................8
`Block Diagram: Raw Card Version A, G(Populated as 2 ranks of x16 SDRAMs)..................................9
`Block Diagram: Raw Card Version B(Populated as 1 rank of x8 SDRAMs) ........................................10
`Block Diagram: Raw Card Version C, H(Populated as 1 rank of x16 SDRAMs) .................................11
`Block Diagram: Raw Card Version D(Populated as 2 ranks of x8 stacked SDRAMs).........................12
`Block Diagram: Raw Card Version E(Populated as 2 ranks of x8 SDRAMs) ......................................13
`Block Diagram: Raw Card Version F(Populated as 2 ranks of x8 SDRAMs).......................................14
`
`Netlist Inc.
`
`Component Details...................................................................................................................................15
`SO-DIMM Common landing pattern for x8 and x16 .............................................................................15
`x8 Ballout for 256 Mb, 512 Mb, 1 Gb, 2 Gb and 4 Gb DDR2 SDRAMs (Top View).............................17
`x16 Ballout for 256 Mb, 512 Mb, 1 Gb, 2 Gb and 4 Gb DDR2 SDRAMs (Top View)...........................17
`DDR2 SDRAM FBGA Component Specifications................................................................................ 18
`x16 Ballout for 256 Mb, 512 Mb, 1 Gb, 2 Gb and 4 Gb DDR2 SDRAMs (Top View)...........................18
`
`Unbuffered SO-DIMM Details...................................................................................................................19
`DDR2 SDRAM Module Configurations (Reference Designs) ..............................................................19
`Input Loading Matrix.............................................................................................................................20
`DDR2 SO-DIMM Gerber File Releases ............................................................................................... 21
`Example Raw Card Component Placement.........................................................................................22
`
`SO-DIMM Wiring Details...........................................................................................................................24
`Signal Groups ...................................................................................................................................... 24
`General Net Structure Routing Guidelines........................................................................................... 24
`Explanation of Net Structure Diagrams................................................................................................ 24
`Differential Clock Net Structures .......................................................................................................... 25
`Clock Net Wiring CK[1:0], CK[1:0] (Raw Cards A, G and B)................................................................25
`Clock Net Wiring CK[1:0], CK[1:0] (Raw Card C, H)............................................................................26
`Clock Net Wiring CK[1:0], CK[1:0] (Raw Card D) ................................................................................27
`Clock Net Wiring CK[1:0], CK[1:0] (Raw Card E).................................................................................28
`Clock Net Wiring CK[1:0], CK[1:0] (Raw Card F).................................................................................29
`Data Net Structures.............................................................................................................................. 30
`Data Net Structures DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw cards A, E, F, G)......................... 30
`Data Net Structures DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw cards B, C, D, H) ........................ 31
`
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`JEDEC Standard No. 21C
`Page 4.20.11-3
`
`Control Net Structures S[1:0], CKE[1:0], ODT[1:0] (Raw cards A, G and C, H) .................................. 32
`Control Net Structures S[0], CKE[0], ODT[0] (Raw card B) ................................................................. 33
`Control Net Structures S[1:0], CKE[1:0], ODT[1:0] (Raw card D)........................................................ 34
`Control Net Structures S[1:0], CKE[1:0], ODT[1:0] (Raw card E) ........................................................ 35
`Control Net Structures S[1:0], CKE[1:0], ODT[1:0] (Raw card F) ........................................................ 36
`Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw cards A, G and B) ....................... 37
`Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card C, H) ................................... 38
`Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card D)........................................ 39
`Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card E) ........................................ 40
`Address/Command Net Structures Ax, BAx, RAS, CAS, WE (Raw card F) ........................................ 41
`Cross Section Recommendations........................................................................................................ 42
`
`Test Points ................................................................................................................................................ 44
`
`Serial Presence Detect Definition ........................................................................................................... 55
`Serial Presence Detect Data Example................................................................................................. 55
`
`Product Label............................................................................................................................................ 58
`
`SO-DIMM Mechanical Specifications...................................................................................................... 60
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`JEDEC Standard No. 21C
`Page 4.20.11-4
`
`1. Product Description
`This reference specification defines the electrical and mechanical requirements for the PC2-6400 memory
`module, a 200-pin, 400MHz clock (800 MT/s data rate), 64-bit wide, Unbuffered Synchronous Double Data
`Rate 2 (DDR2) DRAM Small Outline Dual In-Line Memory Module (DDR2 SDRAM SO-DIMMs). It also
`defines slower versions, the PC2-5300, PC2-4200 and PC2-3200 with a 333MHz 267MHz and 200MHz clock
`(667 MT/s, 533 MT/s and 400 MT/s data rate) DDR2 SDRAMs. These DDR2 SDRAM SO-DIMMs are
`intended for use as main memory when installed in systems such as mobile personal computers.
`
`Reference design examples are included which provide an initial basis for Unbuffered SO-DIMM designs.
`Any modifications to these reference designs must meet all system timing, signal integrity and thermal
`requirements for 333MHz clock rate support. Other designs are acceptable, and all Unbuffered DDR2 SO-
`DIMM implementations must use simulations and lab verification to ensure proper timing requirements and
`signal integrity in the design.
`
`Product Family Attributes
`
`Attribute:
`
`Values:
`
`Notes:
`
`SO-DIMM Organization
`
`x 64
`
`30.0 mm high, 67.60 mm wide / MO-224 variation CB
`25.4 mm high, 67.60 mm wide / MO-224 variation AB
`
`Unbuffered
`
`200
`
`256 Mb, 512 Mb, 1 Gb, 2 Gb, 4 Gb
`
`128 MB, 256 MB, 512 MB, 1 GB, 2GB, 4 GB, 8 GB
`
`Consistent with JEDEC latest Rev.
`
`Netlist Inc.
`
`Dimensions (nominal)
`
`SO-DIMM Types Supported
`
`Pin Count
`
`SDRAMs Supported
`
`Capacity
`
`Serial Presence Detect
`
`Voltage Options, Nominal
`
`1.8 V VDD
`1.8 V VDDQ
`1.8 V to 3.3 V VDDSPD
`
`1, 2
`
`Interface
`
`SSTL_18
`
`Note 1: VDDSPD is not tied to VDD or VDDQ on the DDR2 SO-DIMM.
`Note 2: SO-DIMMs that include an optional temperature sensor may require a restricted VDDSPD operating
`voltage range for proper operation of the temperature sensor. Refer to the thermal sensor specification for
`details regarding the supported voltage range. All other functions of the SO-DIMM SPD are supported across
`the full VDDSPD range.
`
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`JEDEC Standard No. 21C
`Page 4.20.11-5
`
`Raw Card Summary
`
`Raw Card
`
`Number of DDR2 SDRAMs
`
`SDRAM Organization
`
`Number of Ranks
`
`Comments
`
`A, G
`
`B
`
`C, H
`
`D
`
`E
`
`F
`
`8
`
`8
`
`4
`
`16
`
`16
`
`16
`
`x16
`
`x8
`
`x16
`
`x8
`
`x8
`
`x8
`
`2
`
`1
`
`1
`
`2
`
`2
`
`2
`
`G is low profile version(maximum
`DRAM size, W x L) 11.0 mm x 13.0mm
`
`H is low profile version(maximum
`DRAM size, W x L) 11.0 mm x 13.0mm
`
`Uses stacked memory
`
`Planar (maximum DRAM size, W x L)
`12.0 mm x 11.5 mm
`
`Planar (maximum DRAM size, W x L)
`11.0 mm x 13.65 mm
`
`Netlist Inc.
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`JEDEC Standard No. 21C
`Page 4.20.11-6
`
`2. Environmental Requirements
`PC2-6400 DDR2 SDRAM Unbuffered SO-DIMMs are intended for use in mobile computing environments
`that have limited capacity for heat dissipation.
`
`Absolute Maximum Ratings
`
`Symbol
`
`TOPR
`
`Parameter
`
`Operating Temperature (ambient)
`
`Rating
`
` 0 to +65
`
`Units
`
`°C
`
`Notes
`
`1
`
`1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
`operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods
`may affect reliability.
`
`3. Architecture
`
`Pin Description
`
`CK[1:0]
`CK[1:0]
`
` Clock Inputs, positive line
`Clock inputs, negative line
`
`CKE[1:0]
`
`Clock Enables
`
`RAS
`CAS
`
`WE
`
` Row Address Strobe
`Column Address Strobe
`
` Write Enable
`
`S[1:0]
`
` Chip Selects
`
`A[9:0],A[11:15] Address Inputs
`
`2
`2
`
`2
`
`1
`1
`
`1
`
`2
`
`15
`
`A10/AP
`
`BA[2:0]
`
`Address Input/Autoprecharge 1
`
` SDRAM Bank Address
`
`3
`
`ODT[1:0]
`
`On-die termination control
`
`SCL
`
` SDA
`
`Serial Presence Detect (SPD)
`and Thermal sensor Clock
`Input
`
`SPD and TS Data Input/Out-
`put
`
`2
`
`1
`
`1
`
`Netlist Inc.
`
`Core and I/O Power
`
` Ground
`
`VDD
`VSS
`VREF
`VDDSPD SPD and TS Power
`
` DQ[63:0]
`DM[7:0]
`
` Data Input/Output
` Data Masks
`
`DQS[7:0] Data strobes
`
`DQS[7:0] Data strobes complement
`
`TEST
`
`Logic Analyzer specific test pin (No connect
`on SO-DIMM)
`
` Input/Output Reference
`
`Event Pin Reserved for optional hardware temperature
`sensing
`
` NC
`
` Reserved for future use
`
`64
`8
`
`8
`
`8
`
`1
`
`12
`
`57
`
`1
`
`1
`
`1
`
`3
`
`2
`SPD and TS address
`SA[1:0]
`Note: 4 rank SO-DIMM specific signals(RESET, S2, S3) are not included in this table.
`
`Total: 200
`
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`

`JEDEC Standard No. 21C
`Page 4.20.11-7
`
`Input/Output Functional Description
`Symbol
`Type
`Polarity
`
`Function
`
`CK0/CK0,
`CK1/CK1
`
`Input
`
`CKE[1:0]
`
`Input
`
`Cross
`point
`
`The system clock inputs. All address and command lines are sampled on the cross point of the
`rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the
`clock inputs and output timing for read operations is synchronized to the input clock.
`Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By
`deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
`
`Active Low
`
`Enables the associated DDR2 SDRAM command decoder when low and disables the com-
`mand decoder when high. When the command decoder is disabled, new commands are
`ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1.
`Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK and CAS,
`RAS, and WE define the operation to be executed by the SDRAM.
`
`—
`Selects which DDR2 SDRAM internal bank of four or eight is activated.
`Active High Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2
`SDRAM mode register.
`
`S[1:0]
`
`Input
`
`RAS, CAS,
`WE
`
`BA[2:0]
`
`ODT[1:0]
`
`A[9:0],
`A10/AP,
`A[15:11]
`
`Input
`
`Input
`
`Input
`
`Input
`
`DQ[63:0]
`
`In/Out
`
`—
`
`—
`
`DM[7:0]
`
`Input
`
`Active High
`
`DQS[7:0],
`DQS[7:0]
`
`In/Out
`
`Cross
`point
`
`Netlist Inc.
`
`During a Bank Activate command cycle, defines the row address when sampled at the cross
`point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle,
`defines the column address when sampled at the cross point of the rising edge of CK and fall-
`ing edge of CK. In addition to the column address, AP is used to invoke autoprecharge opera-
`tion at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and
`BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a
`Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to
`precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
`inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
`
`Data Input/Output pins.
`
`The data write masks, associated with one data byte. In Write mode, DM operates as a byte
`mask by allowing input data to be written if it is low but blocks the write operation if it is high. In
`Read mode, DM lines have no effect.
`
`The data strobes, associated with one data byte, sourced with data transfers. In Write mode,
`the data strobe is sourced by the controller and is centered in the data window. In Read mode,
`the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data
`window. DQS signals are complements, and timing is relative to the crosspoint of respective
`DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals
`must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed
`appropriately.
`
`VDD, VDDSPD,
`VSS
`VREF
`
`Supply
`
`Supply
`
`SDA
`
`In/Out
`
`Input
`
`Input
`
`SCL
`
`SA[1:0]
`
`TEST
`
`Event
`
`Release 18
`
`—
`
`—
`
`—
`
`—
`
`—
`
`Power supplies for core, I/O, Serial Presence Detect, Thermal sensor, and ground for the mod-
`ule.
`
`Reference voltage for SSTL18 inputs.
`
`This is a bidirectional pin used to transfer data into or out of the SPD EEPROM or Thermal
`sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar
`to act as a pull up.
`
`This signal is used to clock data into and out of the SPD EEPROM and Thermal sensor.
`
`Address pins used to select the Serial Presence Detect base address.
`
`—
`
`In/Out
`
`The TEST pin is reserved for bus analysis tools and is not connected on normal memory mod-
`ules (SO-DIMMs).
`Wire-
`OR Out Active Low The optional EVENT pin is reserved for use to flag critical module temperatures and is used in
`conjuction with a SPD temperture sensing option.
`
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`

`Back
`Side
`
`DM2
`VSS
`DQ22
`
`Pin
`#
`
`101
`
`103
`
`105
`
`107
`
`Front
`Side
`
`Pin
`#
`
`102
`
`A1
`VDD
`A10/AP 106
`
`104
`
`BA0
`
`108
`
`Back
`Side
`
`A0
`VDD
`BA1
`
`RAS
`
`Pin
`#
`
`151
`
`153
`
`155
`
`157
`
`Front
`Side
`
`DQ42
`
`DQ43
`VSS
`DQ48
`
`Back
`Side
`
`DQ46
`
`DQ47
`VSS
`DQ52
`
`Pin
`#
`
`152
`
`154
`
`156
`
`158
`
`160
`
`JEDEC Standard No. 21C
`Page 4.20.11-8
`
`2
`
`4
`
`6
`
`.
`
`1
`
`3
`
`5
`
`DDR2 SDRAM SO-DIMM Pinout
`Pin
`Front
`Pin
`Back
`Pin
`Front
`Pin
`#
`Side
`#
`Side
`#
`Side
`#
`VREF
`VSS
`VSS
`DQ4
`DQ0
`
`51
`
`53
`
`55
`
`DQS2
`VSS
`DQ18
`
`52
`
`54
`
`56
`
`7
`
`8
`
`57
`
`58
`
`DQ1
`VSS
`DQS0
`DQS0
`VSS
`DQ2
`
`DQ3
`
`9
`
`11
`13
`15
`
`17
`
`19
`
`21
`
`23
`25
`27
`
`10
`
`12
`14
`16
`
`18
`
`20
`
`22
`
`24
`26
`28
`
`DQ5
`VSS
`DM0
`VSS
`DQ6
`DQ7
`VSS
`
`DQ12
`
`59
`
`61
`63
`65
`
`71
`
`73
`75
`77
`
`DQ23
`VSS
`DQ28
`DQ29
`VSS
`DQS3
`
`DQS3
`
`109
`
`111
`113
`115
`
`117
`
`119
`
`121
`
`123
`125
`127
`
`60
`
`62
`64
`66
`
`68
`
`70
`
`72
`
`74
`76
`78
`
`DQ49
`S0
`VSS
`VDD
`162
`161
`112
`163 NC,TEST 164
`ODT0
`114
`VSS
`116 NC / A13 165
`166
`VDD
`DQS6
`
`DQ53
`VSS
`CK1
`CK1
`VSS
`
`DM6
`
`168
`
`110
`
`159
`
`118
`
`167
`
`120
`
`122
`
`124
`126
`128
`
`NC/S3
`
`169
`
`DQS6
`
`171
`
`173
`175
`177
`
`170
`
`172
`
`174
`176
`178
`
`DQ19
`VSS
`DQ24
`DQ25
`VSS
`67
`DM3
`69 NC/RE
`SET
`VSS
`DQ26
`DQ27
`VSS
`
`DQ13
`VSS
`DM1
`VSS
`
`CK0
`
`79
`
`CKE0
`
`81
`
`VDD
`NC/S2
`83
`85 NC/BA2
`VDD
`87
`A12
`
`89
`
`VSS
`DQ8
`DQ9
`VSS
`
`DQS1
`
`29
`
`31
`
`33
`35
`37
`
`39
`
`30
`
`32
`
`34
`36
`38
`
`40
`
`VSS
`DQ30
`DQ31
`VSS
`NC /
`CKE1
`VDD
`84 NC / A15
`86 NC / A14
`VDD
`88
`A11
`
`80
`
`82
`
`WE
`VDD
`CAS
`NC/ S1
`VDD
`NC /
`ODT1
`VSS
`DQ32
`DQ33
`VSS
`
`DQS4
`
`130
`
`132
`
`134
`136
`138
`
`129
`
`131
`
`133
`135
`137
`
`Netlist Inc.
`
`90
`
`139
`
`141
`
`140
`
`142
`
`VSS
`DQ54
`DQ55
`VSS
`
`DQ60
`
`VSS
`DQ36
`DQ37
`VSS
`
`DM4
`
`VSS
`DQ38
`DQ39
`VSS
`DQ44
`
`179
`
`181
`
`183
`185
`187
`
`189
`
`191
`
`VSS
`DQ50
`DQ51
`VSS
`
`DQ56
`
`DQ57
`VSS
`DM7
`VSS
`DQ58
`
`180
`
`182
`
`184
`186
`188
`
`190
`
`192
`
`DQS1
`VSS
`DQ10
`DQ11
`VSS
`VSS
`DQ16
`
`41
`
`43
`
`42
`
`44
`
`CK0
`VSS
`DQ14
`DQ15
`VSS
`VSS
`DQ20
`
`91
`
`93
`
`45
`
`47
`
`46
`
`48
`
`50
`
`DQ21
`VSS
`Event
`
`95
`
`97
`
`99
`
`DQS4
`VSS
`DQ34
`DQ35
`VSS
`DQ40
`
`A7
`
`A6
`VDD
`A4
`
`A2
`
`143
`
`145
`
`147
`
`149
`
`DQ41
`VSS
`DM5
`VSS
`
`144
`
`146
`
`148
`
`150
`
`A9
`
`A8
`VDD
`A5
`
`A3
`
`92
`
`94
`
`96
`
`98
`
`100
`
`DQ61
`VSS
`DQS7
`DQS7
`VSS
`DQ62
`
`DQ63
`VSS
`SA0
`
`SA1
`
`DQ45
`VSS
`DQS5
`
`DQS5
`VSS
`
`DQ59
`VSS
`SDA
`
`193
`
`195
`
`194
`
`196
`
`198
`SCL
`197
`199 VDDSPD 200
`
`DQ17
`VSS
`49
`DQS2
`Note:
`1. NC = No Connect; NC,TEST(pin 163) is for bus analysis tool and is not connected on normal memory modules.
`2. Pins 69, 83, 120 used by 4 rank DDR2 SO-DIMMs.
`
`Revision 2.5
`
`Release 18
`
`Downloaded by Marwan Fawal (mfawal@netlist.com) on Mar 21, 2023, 11:37 am PDT
`
`Netlist Ex 2046
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Block Diagram: Raw Card Version A, G (Populated as 2 ranks of x16 SDRAMs)
`
`JEDEC Standard No. 21C
`Page 4.20.11-9
`
`ODT
`
`CKE
`
`CS
`
`D0
`
`3 Ω ± 5%
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`ODT1
`ODT0
`CKE1
`CKE0
`
`S1
`S0
`
`DQS0
`DQS0
`DM0
`
`DQS1
`DQS1
`DM1
`
`DQS2
`DQS2
`DM2
`
`DQS3
`DQS3
`DM3
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`DQS4
`DQS4
`DM4
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`DQS5
`DQS5
`DM5
`
`ODT
`
`CKE
`
`CS
`
`D4
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQS6
`DQS6
`DM6
`
`DQS7
`
`Netlist Inc.
`
`ODT
`
`CKE
`
`CS
`
`D5
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`
`ODT
`
`CKE
`
`CS
`
`D1
`
`ODT
`
`CKE
`
`CS
`
`ODT
`
`CKE
`
`CS
`
`D2
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`ODT
`
`CKE
`
`CS
`
`D3
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`
`D6
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`ODT
`
`CKE
`
`CS
`
`D7
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`
`
`DQS7
`DM7
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`SCL
`SA0
`SA1
`SA2
`
`3 Ω ± 5%
`
`SDRAMS D0-D7
`SDRAMS D0-D7
`SDRAMS D0-D7
`SDRAMS D0-D7
`SDRAMS D0-D7
`
`4 loads
`
`4 loads
`
`VDDSPD
`VREF
`
`VDD
`
`VSS
`
`BA0-BA2
`A0-AN
`RAS
`CAS
`WE
`
`CK0
`CK0
`
`CK1
`CK1
`
`Release 18
`
`SCL
`A0
`A1
`A2
`
`Serial Presence
`Detect (SPD)
`
`Event/WP
`
`SDA
`
`Note:
`For normal operation only R(WP) is placed.
`For the SPD temperture sensor option
`only R(Event) is placed.
`
`R(WP) = 0 Ω
`
`R(Event) = 0 Ω
`
`WP
`
`Event
`
`SPD, Thermal sensor
`SDRAMS D0-D7
`
`SDRAMS D0-D7,
`
`VDD and VDDQ
`
`SDRAMS D0-D7, SPD, Thermal sensor
`
`#Unless otherwise noted, resistor values
`are 22 Ω ± 5% DQ wiring may differ from
`that described in this drawing; described
`in this drawing; however, DQ/DM/DQS/DQS
`relationships are maintained as shown
`
`Revision 2.5
`
`Downloaded by Marwan Fawal (mfawal@netlist.com) on Mar 21, 2023, 11:37 am PDT
`
`Netlist Ex 2046
`Samsung v Netlist
`IPR2022-00996
`
`

`

`JEDEC Standard No. 21C
`Page 4.20.11-10
`
`Block Diagram: Raw Card Version B(Populated as 1 rank of x8 SDRAMs)
`
`S1
`ODT1
`CKE1
`
`N.C.
`N.C.
`N.C.
`
`3 Ω ± 5%
`
`CSODT CKE
`
`D0
`
`CSODT CKE
`
`D1
`
`CSODT CKE
`
`D2
`
`CSODT CKE
`
`D3
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`DQS4
`DQS4
`DM4
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`DQS5
`DQS5
`DM5
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`DQS6
`DQS6
`DM6
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQS7
`DQS7
`DM7
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`Netlist Inc.
`
`CSODT CKE
`
`D4
`
`CSODT CKE
`
`D5
`
`CSODT CKE
`
`D6
`
`CSODT CKE
`
`D7
`
`CKE0
`ODT0
`S0
`DQS0
`DQS0
`DM0
`
`DQS1
`DQS1
`DM1
`
`DQS2
`DQS2
`DM2
`
`DQS3
`DQS3
`DM3
`
`BA0-BA2
`A0-AN
`RAS
`CAS
`WE
`
`CK0
`CK0
`
`CK1
`CK1
`
`3 Ω ± 5%
`
`SDRAMS D0-D7
`SDRAMS D0-D7
`SDRAMS D0-D7
`SDRAMS D0-D7
`SDRAMS D0-D7
`
`
`
`Note:
`For normal operation only R(WP) is placed.
`For the SPD temperture sensor option
`only R(Event) is placed.
`
`SCL
`A0
`A1
`A2
`
`Serial Presence
`Detect (SPD)
`
`Event/WP
`
`SDA
`
`WP
`
`Event
`
`SA0
`SA1
`SA2
`
`R(WP) = 0 Ω
`
`R(Event) = 0 Ω
`
`4 loads
`
`4 loads
`
`VDDSPD
`VREF
`VDD
`
`VSS
`
`SPD, Thermal sensor
`SDRAMS D0-D7
`
`SDRAMS D0-D7,
`
`VDD and VDDQ
`
`SDRAMS D0-D7, SPD, Thermal sensor
`
`#Unless otherwise noted, resistor values
`are 22 Ω ± 5% DQ wiring may differ from
`that described in this drawing; described
`in this drawing; however, DQ/DM/DQS/DQS
`relationships are maintained as shown
`
`Revision 2.5
`
`Release 18
`
`Downloaded by Marwan Fawal (mfawal@netlist.com) on Mar 21, 2023, 11:37 am PDT
`
`Netlist Ex 2046
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Block Diagram: Raw Card Version C, H (Populated as 1 rank of x16 SDRAMs)
`
`JEDEC Standard No. 21C
`Page 4.20.11-11
`
`3 Ω ± 5%
`
`S1
`ODT1
`CKE1
`
`N.C.
`N.C.
`N.C.
`
`CS
`
`ODT
`
`CKE
`
`D0
`
`ODT
`CS
`
`CKE
`
`D1
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`LDQS
`
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`3 Ω ± 5%
`
`DQS4
`DQS4
`DM4
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`DQS5
`DQS5
`DM5
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQS6
`DQS6
`DM6
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`DQS7
`DQS7
`DM7
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`CS
`
`ODT
`
`CKE
`
`D2
`
`CS
`
`ODT
`
`CKE
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`LDQS
`LDQS
`LDM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`UDQS
`
`Netlist Inc.
`
`D3
`
`UDQS
`UDM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`CKE0
`ODT0
`S0
`
`DQS0
`DQS0
`DM0
`
`DQS1
`DQS1
`DM1
`
`DQS2
`DQS2
`DM2
`
`DQS3
`DQS3
`DM3
`
`BA0-BA2
`A0-AN
`RAS
`CAS
`WE
`
`CK0
`CK0
`
`CK1
`CK1
`
`Release 18
`
`SDRAMS D0-D3
`SDRAMS D0-D3
`SDRAMS D0-D3
`SDRAMS D0-D3
`SDRAMS D0-D3
`
`2 loads
`
`2 loads
`
`VDDSPD
`VREF
`
`VDD
`VSS
`
`
`
`Note:
`For normal operation only R(WP) is placed.
`For the SPD temperture sensor option
`only R(Event) is placed.
`
`SCL
`A0
`A1
`A2
`
`Serial Presence
`Detect (SPD)
`
`Event/WP
`
`SDA
`
`WP
`
`Event
`
`SA0
`SA1
`SA2
`
`R(WP) = 0 Ω
`
`R(Event) = 0 Ω
`
`SPD, Thermal sensor
`SDRAMS D0-D3
`
`SDRAMS D0-D3,
`
`VDD and VDDQ
`
`SDRAMS D0-D3, SPD, Thermal sensor
`
`#Unless otherwise noted, resistor values
`are 22 Ω ± 5% DQ wiring may differ from
`that described in this drawing; described
`in this drawing; however, DQ/DM/DQS/DQS
`relationships are maintained as shown
`
`Revision 2.5
`
`Downloaded by Marwan Fawal (mfawal@netlist.com) on Mar 21, 2023, 11:37 am PDT
`
`Netlist Ex 2046
`Samsung v Netlist
`IPR2022-00996
`
`

`

`JEDEC Standard No. 21C
`Page 4.20.11-12
`
`Block Diagram: Raw Card Version D (Populated as 2 rank of x8 SDRAMs)
`3 Ω ± 5%
`
`CKE1
`ODT1
`S1
`CKE0
`ODT0
`S0
`DQS0
`DQS0
`DM0
`
`DQS1
`DQS1
`DM1
`
`DQS2
`DQS2
`DM2
`
`DQS3
`DQS3
`DM3
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS0 ODT0 CKE0
`
`CS1 ODT1 CKE1
`
`D0, D8 (Stacked)
`
`CS0 ODT0 CKE0
`
`CS1 ODT1 CKE1
`
`D1, D9 (Stacked)
`
`Netlist Inc.
`
`CS0 ODT0 CKE0
`
`CS1 ODT1 CKE1
`
`D2, D10 (Stacked)
`
`CS0 ODT0 CKE0
`
`CS1 ODT1 CKE1
`
`D3, D11 (Stacked)
`
`DQS4
`DQS4
`DM4
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`DQS5
`DQS5
`DM5
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`DQS6
`DQS6
`DM6
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQS7
`DQS7
`DM7
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`CS0 ODT0 CKE0
`
`CS1 ODT1 CKE1
`
`D4, D12 (Stacked)
`
`CS0 ODT0 CKE0
`
`CS1 ODT1 CKE1
`
`D5, D13 (Stacked)
`
`CS0 ODT0 CKE0
`
`CS1 ODT1 CKE1
`
`D6, D14 (Stacked)
`
`CS0 ODT0 CKE0
`
`CS1 ODT1 CKE1
`
`D7, D15 (Stacked)
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`BA0-BA2
`A0-AN
`RAS
`CAS
`WE
`
`CK0
`CK0
`
`CK1
`CK1
`
`10 Ω ± 5%
`
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`
`5.6pF
`
`8 loads
`
`5.6pF
`
`8 loads
`
`VDDSPD
`VREF
`
`VDD
`
`VSS
`
`
`
`Note:
`For normal operation only R(WP) is placed.
`For the SPD temperture sensor option
`only R(Event) is placed.
`
`SCL
`A0
`A1
`A2
`
`Serial Presence
`Detect (SPD)
`
`Event/WP
`
`SDA
`
`WP
`
`Event
`
`SA0
`SA1
`SA2
`
`R(WP) = 0 Ω
`
`R(Event) = 0 Ω
`
`SPD, Thermal sensor
`SDRAMS D0-D15
`
`#Unless otherwise noted, resistor values
`are 22 Ω ± 5% DQ wiring may differ from
`that described in this drawing; described
`in this drawing; however, DQ/DM/DQS/DQS
`relationships are maintained as shown
`SDRAMS D0-D15, SPD, Thermal sensor
`
`SDRAMS D0-D15,
`
`VDD and VDDQ
`
`Revision 2.5
`
`Release 18
`
`Downloaded by Marwan Fawal (mfawal@netlist.com) on Mar 21, 2023, 11:37 am PDT
`
`Netlist Ex 2046
`Samsung v Netlist
`IPR2022-00996
`
`

`

`CKE1
`ODT1
`S1
`CKE0
`ODT0
`S0
`DQS0
`DQS0
`DM0
`
`DQS1
`DQS1
`DM1
`
`DQS2
`DQS2
`DM2
`
`DQS3
`DQS3
`DM3
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`CS0 ODT0 CKE0
`
`D1
`
`CS0 ODT0 CKE0
`
`D3
`
`CS0 ODT0 CKE0
`
`D5
`
`CS0 ODT0 CKE0
`
`D7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS4
`DQS4
`DM4
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`DQS5
`DQS5
`DM5
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`DQS6
`DQS6
`DM6
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQS7
`DQS7
`DM7
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`CS1 ODT1 CKE1
`
`D9
`
`CS1 ODT1 CKE1
`
`D11
`
`CS1 ODT1 CKE1
`
`D13
`
`CS1 ODT1 CKE1
`
`D15
`
`
`
`Netlist Inc.
`
`CS0 ODT0 CKE0
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS CS0 ODT0 CKE0
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS CS0 ODT0 CKE0
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS CS0 ODT0 CKE0
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D2
`
`D4
`
`D6
`
`D8
`
`CS1 ODT1 CKE1
`
`D10
`
`CS1 ODT1 CKE1
`
`D12
`
`CS1 ODT1 CKE1
`
`D14
`
`CS1 ODT1 CKE1
`
`D16
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`SCL
`A0
`A1
`A2
`
`Serial Presence
`Detect (SPD)
`
`Event/WP
`
`SDA
`
`WP
`
`Event
`
`SA0
`SA1
`SA2
`
`R(WP) = 0 Ω
`
`R(Event) = 0 Ω
`
`Block Diagram: Raw Card Version E (populated as 2 rank of x8 SDRAMs)
`3 Ω ± 5%
`
`JEDEC Standard No. 21C
`Page 4.20.11-13
`
`BA0-BA2
`A0-AN
`RAS
`CAS
`WE
`
`10 Ω ± 5%
`
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`
`Note:
`For normal operation only R(WP) is placed.
`For the SPD temperture sensor option
`only R(Event) is placed.
`
`CK0
`
`CK0
`CK1
`
`CK1
`
`5.6 pF
`
`8 loads
`
`5.6 pF
`
`8 loads
`
`VDDSPD
`VREF
`
`VDD
`
`VSS
`
`SPD, Thermal sensor
`SDRAMS D0-D15
`
`SDRAMS D0-D15,
`
`VDD and VDDQ
`
`SDRAMS D0-D15, SPD, Thermal sensor
`
`#Unless otherwise noted, resistor values
`are 22 Ω ± 5% DQ wiring may differ from
`that described in this drawing; described
`in this drawing; however, DQ/DM/DQS/DQS
`relationships are maintained as shown
`
`Release 18
`
`Revision 2.5
`
`Downloaded by Marwan Fawal (mfawal@netlist.com) on Mar 21, 2023, 11:37 am PDT
`
`Netlist Ex 2046
`Samsung v Netlist
`IPR2022-00996
`
`

`

`CKE1
`ODT1
`S1
`CKE0
`ODT0
`S0
`DQS0
`DQS0
`DM0
`
`DQS1
`DQS1
`DM1
`
`DQS2
`DQS2
`DM2
`
`DQS3
`DQS3
`DM3
`
`BA0-BA2
`A0-AN
`RAS
`CAS
`WE
`
`CK0
`
`CK0
`CK1
`
`CK1
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS0 ODT0 CKE0
`
`D0
`
`CS0 ODT0 CKE0
`
`D1
`
`CS0 ODT0 CKE0
`
`D10
`
`CS0 ODT0 CKE0
`
`D11
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`10 Ω ± 5%
`
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`SDRAMS D0-D15
`
`5.6 pF
`
`8 loads
`
`5.6 pF
`
`8 loads
`
`VDDSPD
`VREF
`
`VDD
`
`VSS
`
`DQS4
`DQS4
`DM4
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`DQS5
`DQS5
`DM5
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`DQS6
`DQS6
`DM6
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQS7
`DQS7
`DM7
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`CS1 ODT1 CKE1
`
`D8
`
`CS1 ODT1 CKE1
`
`D9
`
`CS1 ODT1 CKE1
`
`D2
`
`CS1 ODT1 CKE1
`
`D3
`
`
`
`Netlist Inc.
`
`CS1 ODT1 CKE1
`
`D12
`
`CS1 ODT1 CKE1
`
`D13
`
`CS1 ODT1 CKE1
`
`D6
`
`CS1 ODT1 CKE1
`
`D7
`
`SDA
`
`CS0 ODT0 CKE0
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS CS0 ODT0 CKE0
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS CS0 ODT0 CKE0
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`DQS CS0 ODT0 CKE0
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D4
`
`D5
`
`D14
`
`D15
`
`DQS
`DQS
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`