256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Features
`
`Figure 1: 240-Pin RDIMM (MO-237
`R/C A, Nonparity; R/C F, Parity)
`
`Module height: 30mm (1.18in)
`
`DDR2 SDRAM RDIMM
`MT9HTF3272Y – 256MB
`MT9HTF6472PY – 512MB
`MT9HTF12872PY – 1GB
`
`Features
`• 240-pin, registered dual in-line memory module
`• Fast data transfer rates: PC2-3200, PC2-4200,
`PC2-5300, or PC2-6400
`• 256MB (32 Meg x 72), 512MB (64 Meg x 72), or
`1GB (128 Meg x 72)
`• Supports ECC error detection and correction
`• VDD = VDDQ = 1.8V
`• VDDSPD = 1.7–3.6V
`• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
`• Differential data strobe (DQS, DQS#) option
`• 4n-bit prefetch architecture
`• Multiple internal device banks for concurrent
`operation
`• Programmable CAS# latency (CL)
`• Posted CAS# additive latency (AL)
`• WRITE latency = READ latency - 1 tCK
`• Programmable burst lengths (BL): 4 or 8
`• Adjustable data-output drive strength
`• 64ms, 8192-cycle refresh
`• On-die termination (ODT)
`• Serial presence-detect (SPD) with EEPROM
`• Single rank
`• Gold edge contacts
`
`Table 1: Key Timing Parameters
`
`Marking
`P
`
`None
`I
`
`Options
`• Parity
`• Operating temperature
`– Commercial (0°C ≤ TA ≤ +70°C)
`– Industrial (–40°C ≤ TA ≤ +85°C)1
`• Package
`– 240-pin DIMM (lead-free)
`• Frequency/CL2
`– 2.5ns @ CL = 5 (DDR2-800)3
`– 2.5ns @ CL = 6 (DDR2-800)3
`– 3.0ns @ CL = 5 (DDR2-667)
`– 3.75ns @ CL = 4 (DDR2-533)
`– 5.0ns @ CL = 3 (DDR2-400)
`1. Contact Micron for industrial temperature
`Notes:
`module offerings.
`2. CL = CAS (READ) latency; registered mode
`will add one clock cycle to CL.
`3. Not available in 256MB module density.
`
`Y
`
`-80E
`-800
`-667
`-53E
`-40E
`
`Speed
`Grade
`-80E
`-800
`-667
`-53E
`-40E
`
`Industry
`Nomenclature
`PC2-6400
`PC2-6400
`PC2-5300
`PC2-4200
`PC2-3200
`
`CL = 6
`800
`800
`–
`–
`–
`
`Data Rate (MT/s)
`CL = 5
`CL = 4
`800
`533
`667
`533
`667
`553
`–
`553
`–
`400
`
`CL = 3
`400
`400
`400
`400
`400
`
`tRCD
`(ns)
`12.5
`15
`15
`15
`15
`
`tRP
`(ns)
`12.5
`15
`15
`15
`15
`
`tRC
`(ns)
`55
`55
`55
`55
`55
`
`1
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`PDF: 09005aef82250868
`© 2003 Micron Technology, Inc. All rights reserved.
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`Products and specifications discussed herein are subject to change by Micron without notice.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Features
`
`Table 2: Addressing
`
`Parameter
`Refresh count
`Row address
`Device bank address
`Device configuration
`Column address
`Module rank address
`
`256MB
`8K
`8K A[12:0]
`4 BA[1:0]
`256Mb (32 Meg x 8)
`1K A[9:0]
`S0#
`
`512MB
`8K
`16K A[13:0]
`4 BA[1:0]
`512Mb (64 Meg x 8)
`1K A[9:0]
`S0#
`
`1GB
`8K
`16K A[13:0]
`8 BA[2:0]
`1Gb (128 Meg x 8)
`1K A[9:0]
`S0#
`
`Table 3: Part Numbers and Timing Parameters – 256MB
`
`Base device: MT47H32M8,1 256Mb DDR2 SDRAM
`Module
`Density
`256MB
`256MB
`256MB
`
`Part Number2
`MT9HTF3272(I)Y-667__
`MT9HTF3272(I)Y-53E__
`MT9HTF3272(I)Y-40E__
`
`Configuration
`32 Meg x 72
`32 Meg x 72
`32 Meg x 72
`
`Module
`Bandwidth
`5.3 GB/s
`4.3 GB/s
`3.2 GB/s
`
`Memory Clock/
`Data Rate
`3.0ns/667 MT/s
`3.75ns/533 MT/s
`5.0ns/400 MT/s
`
`Clock Cycles
`(CL-tRCD-tRP)
`5-5-5
`4-4-4
`3-3-3
`
`Table 4: Part Numbers and Timing Parameters – 512MB
`
`Base device: MT47H64M8,1 512Mb DDR2 SDRAM
`Module
`Density
`512MB
`512MB
`512MB
`512MB
`512MB
`
`Part Number2
`MT9HTF6472P(I)Y-80E__
`MT9HTF6472P(I)Y-800__
`MT9HTF6472P(I)Y-667__
`MT9HTF6472P(I)Y-53E__
`MT9HTF6472P(I)Y-40E__
`
`Configuration
`64 Meg x 72
`64 Meg x 72
`64 Meg x 72
`64 Meg x 72
`64 Meg x 72
`
`Table 5: Part Numbers and Timing Parameters – 1GB
`
`Base device: MT47H128M8,1 1Gb DDR2 SDRAM
`Module
`Density
`1GB
`1GB
`1GB
`1GB
`1GB
`
`Part Number2
`MT9HTF12872P(I)Y-80E__
`MT9HTF12872P(I)Y-800__
`MT9HTF12872P(I)Y-667__
`MT9HTF12872P(I)Y-53E__
`MT9HTF12872P(I)Y-40E__
`
`Configuration
`128 Meg x 72
`128 Meg x 72
`128 Meg x 72
`128 Meg x 72
`128 Meg x 72
`
`Module
`Bandwidth
`6.2 GB/s
`6.2 GB/s
`5.3 GB/s
`4.3 GB/s
`3.2 GB/s
`
`Memory Clock/
`Data Rate
`2.5ns/800 MT/s
`2.5ns/800 MT/s
`3.0ns/667 MT/s
`3.75ns/533 MT/s
`5.0ns/400 MT/s
`
`Clock Cycles
`(CL-tRCD-tRP)
`5-5-5
`6-6-6
`5-5-5
`4-4-4
`3-3-3
`
`Module
`Bandwidth
`6.2 GB/s
`6.2 GB/s
`5.3 GB/s
`4.3 GB/s
`3.2 GB/s
`
`Memory Clock/
`Data Rate
`2.5ns/800 MT/s
`2.5ns/800 MT/s
`3.0ns/667 MT/s
`3.75ns/533 MT/s
`5.0ns/400 MT/s
`
`Clock Cycles
`(CL-tRCD-tRP)
`5-5-5
`6-6-6
`5-5-5
`4-4-4
`3-3-3
`
`Notes:
`
`1. Data sheets for the base device can be found on Micron’s Web site.
`2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Con-
`sult factory for current revision codes. Example: MT9HTF6472Y-667D2.
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`2
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Pin Assignments
`
`Pin Assignments
`
`Table 6: Pin Assignments
`
`240-Pin RDIMM Back
`240-Pin RDIMM Front
`Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
`1
`31
`DQ19
`61
`A4
`91
`121
`151
`181
`211
`DM5/
`VREF
`VSS
`VSS
`VSS
`VDDQ
`DQS14
`NC/
`DQS14#
`VSS
`DQ46
`DQ47
`
`2
`
`3
`4
`5
`
`VSS
`
`DQ0
`DQ1
`VSS
`
`32
`
`33
`34
`35
`
`VSS
`
`DQ24
`DQ25
`VSS
`
`62
`
`63
`64
`65
`
`VDDQ
`
`A2
`VDD
`VSS
`
`93
`94
`95
`
`DQS5
`VSS
`DQ42
`
`123
`124
`125
`
`92 DQS5#
`
`122
`
`DQ4
`
`152 DQ28
`
`182
`
`A3
`
`212
`
`6
`
`7
`8
`
`9
`10
`11
`12
`13
`
`14
`
`DQS0#
`
`36
`
`DQS3#
`
`DQS0
`VSS
`
`DQ2
`DQ3
`VSS
`DQ8
`DQ9
`
`VSS
`
`37
`38
`
`39
`40
`41
`42
`43
`
`44
`
`DQS3
`VSS
`
`DQ26
`DQ27
`VSS
`CB0
`CB1
`
`VSS
`
`66
`
`67
`68
`
`69
`70
`71
`72
`73
`
`74
`
`VSS
`
`VDD
`NC/
`Par_In2
`VDD
`A10
`BA0
`VDDQ
`WE#
`
`96
`
`97
`98
`
`99
`100
`101
`102
`103
`
`DQ43
`
`126
`
`127
`128
`
`VSS
`DQ48
`
`DQ49
`VSS
`SA2
`NC
`VSS
`
`DQ7
`129
`VSS
`130
`131 DQ12
`132 DQ13
`133
`VSS
`
`159 DQ31
`160
`VSS
`161
`CB4
`162
`CB5
`163
`VSS
`
`CAS#
`
`104 DQS6#
`
`134
`
`164
`
`194
`
`VDDQ
`
`224
`
`DQ5
`VSS
`DM0/
`DQS9
`NC/
`DQS9#
`VSS
`DQ6
`
`153 DQ29
`154
`VSS
`155
`DM3/
`DQS12
`NC/
`DQS12#
`VSS
`157
`158 DQ30
`
`156
`
`183
`184
`185
`
`A1
`VDD
`CK0
`
`213
`214
`215
`
`186
`
`CK0#
`
`216
`
`VSS
`
`DQ52
`DQ53
`
`187
`188
`
`189
`190
`191
`192
`193
`
`VDD
`A0
`
`VDD
`BA1
`VDDQ
`RAS#
`S0#
`
`217
`218
`
`219
`220
`221
`222
`223
`
`VDDQ
`
`105 DQS6
`
`S1#
`ODT1
`VDDQ
`VSS
`DQ32
`DQ33
`VSS
`
`VSS
`106
`107 DQ50
`108 DQ51
`109
`VSS
`110 DQ56
`111 DQ57
`112
`VSS
`
`135
`
`DM1/
`DQS10
`NC/
`DQS10#
`VSS
`136
`RFU
`137
`RFU
`138
`VSS
`139
`140 DQ14
`141 DQ15
`142
`VSS
`
`DQS4#
`
`113 DQS7#
`
`143 DQ20
`
`DQS4
`VSS
`
`114 DQS7
`115
`VSS
`
`144 DQ21
`145
`VSS
`
`195 ODT0
`
`225
`
`DM8/
`DQS17
`NC/
`DQS17#
`VSS
`CB6
`CB7
`VSS
`VDDQ
`CKE1
`VDD
`
`165
`
`166
`167
`168
`169
`170
`171
`172
`
`196 NC/A133 226
`197
`227
`VDD
`198
`VSS
`228
`199 DQ36
`229
`200 DQ37
`230
`201
`VSS
`231
`202
`DM4/
`232
`DQS13
`NC/
`DQS13#
`174 NC/A144 204
`VSS
`175
`205 DQ38
`VDDQ
`
`173 NC/A154 203
`
`233
`
`234
`235
`
`VSS
`RFU
`RFU
`VSS
`DM6/
`DQS15
`NC/
`DQS15#
`VSS
`
`DQ54
`DQ55
`VSS
`DQ60
`DQ61
`VSS
`DM7/
`DQS16
`NC/
`DQS16#
`VSS
`DQ62
`
`15 DQS1#
`
`45
`
`DQS8#
`
`DQS1
`16
`VSS
`17
`18 RESET#
`19
`NC
`20
`VSS
`21
`DQ10
`22
`DQ11
`
`23
`
`24
`25
`
`26
`
`VSS
`
`DQ16
`DQ17
`
`VSS
`
`46
`47
`48
`49
`50
`51
`52
`
`53
`
`DQS8
`VSS
`CB2
`CB3
`VSS
`VDDQ
`CKE0
`
`VDD
`
`54 NC/BA2
`NC/1
`55
`Err_Out#
`VDDQ
`
`56
`
`27 DQS2#
`
`57
`
`A11
`
`28
`
`DQS2
`
`58
`
`A7
`
`75
`
`76
`77
`78
`79
`80
`81
`82
`
`83
`
`84
`85
`
`86
`
`87
`
`88
`
`DQ34
`
`116 DQ58
`
`DQ35
`
`117 DQ59
`
`VSS
`
`118
`
`VSS
`
`147
`
`146 DM2/
`DQS11
`NC/
`DQS11#
`VSS
`
`148
`
`176
`
`A12
`
`206 DQ39
`
`236
`
`DQ63
`
`177
`
`A9
`
`207
`
`VSS
`
`237
`
`VSS
`
`178
`
`VDD
`
`208 DQ44
`
`238 VDDSPD
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`3
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Pin Assignments
`
`Table 6: Pin Assignments (Continued)
`
`240-Pin RDIMM Back
`240-Pin RDIMM Front
`Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
`29
`59
`89
`DQ40
`119
`SDA
`149 DQ22
`179
`A8
`209 DQ45
`239
`SA0
`VSS
`VDD
`30
`DQ18
`60
`A5
`90
`DQ41
`120
`SCL
`150 DQ23
`180
`A6
`210
`VSS
`240
`SA1
`
`Notes:
`
`1. Pin 55 is NC for nonparity and Err_Out# for parity.
`2. Pin 68 is NC for nonparity and Par_In for parity.
`3. Pin 196 is NC for 256MB or A13 for 512MB, 1GB, and parity.
`4. Pin 173 and 174 are NC or A15 and A14 for parity.
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`4
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Pin Descriptions
`
`Pin Descriptions
`
`The pin description table below is a comprehensive list of all possible pins for all DDR2
`modules. All pins listed may not be supported on this module. See Pin Assignments for
`information specific to this module.
`
`Table 7: Pin Descriptions
`
`Symbol
`Ax
`
`Type
`Input
`
`BAx
`
`Input
`
`CKx,
`CK#x
`CKEx
`
`DMx,
`
`Input
`
`Input
`
`Input
`
`ODTx
`
`Input
`
`Par_In
`RAS#, CAS#, WE#
`
`RESET#
`
`S#x
`
`SAx
`
`SCL
`
`CBx
`DQx
`DQSx,
`DQS#x
`
`Input
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`I/O
`I/O
`I/O
`
`Description
`Address inputs: Provide the row address for ACTIVE commands, and the column ad-
`dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
`out of the memory array in the respective bank. A10 sampled during a PRECHARGE
`command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
`selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
`during a LOAD MODE command. See the Pin Assignments Table for density-specific
`addressing information.
`Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
`PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
`MR2, and MR3) is loaded during the LOAD MODE command.
`Clock: Differential clock inputs. All control, command, and address input signals are
`sampled on the crossing of the positive edge of CK and the negative edge of CK#.
`Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
`try and clocks on the DDR2 SDRAM.
`Data mask (x8 devices only): DM is an input mask signal for write data. Input data
`is masked when DM is sampled HIGH, along with that input data, during a write ac-
`cess. Although DM pins are input-only, DM loading is designed to match that of the
`DQ and DQS pins.
`On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
`nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
`ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
`will be ignored if disabled via the LOAD MODE command.
`Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
`Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
`entered.
`Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
`signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
`Chip select: Enables (registered LOW) and disables (registered HIGH) the command
`decoder.
`Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
`bus.
`Serial clock for SPD EEPROM: Used to synchronize communication to and from the
`SPD EEPROM on the I2C bus.
`Check bits. Used for system error detection and correction.
`Data input/output: Bidirectional data bus.
`Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
`troller. Output with read data; input with write data for source synchronous opera-
`tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
`MODE command.
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`5
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Pin Descriptions
`
`Table 7: Pin Descriptions (Continued)
`
`Symbol
`SDA
`
`RDQSx,
`RDQS#x
`
`Type
`I/O
`
`Output
`
`Err_Out#
`
`VDD/VDDQ
`
`Output
`(open drain)
`Supply
`
`VDDSPD
`VREF
`VSS
`NC
`NF
`NU
`RFU
`
`Supply
`Supply
`Supply
`–
`–
`–
`–
`
`Description
`Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
`the I2C bus.
`Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
`MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
`is output with read data only and is ignored during write data. When RDQS is disa-
`bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
`and differential data strobe mode is enabled.
`Parity error output: Parity error found on the command and address bus.
`
`Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
`ule VDD.
`SPD EEPROM power supply: 1.7–3.6V.
`Reference voltage: VDD/2.
`Ground.
`No connect: These pins are not connected on the module.
`No function: These pins are connected within the module, but provide no functionality.
`Not used: These pins are not used in specific module configurations/operations.
`Reserved for future use.
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`6
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Functional Block Diagram
`
`Functional Block Diagram
`
`Figure 2: Functional Block Diagram – Raw Card A, Nonparity
`
`DQS4
`DQS4#
`DM4/DQS13
`NC/DQS13#
`
`DQS5
`DQS5#
`DM5/DQS14
`NC/DQS14#
`
`DQS6
`DQS6#
`DM6/DQS15
`NC/DQS15#
`
`DQS7
`DQS7#
`DM7/DQS16
`NC/DQS16#
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`
`
`RS0#
`
`DQS0
`DQS0#
`DM0/DQS9
`NC/DQS9#
`
`DQS1
`DQS1#
`DM1/DQS10
`NC/DQS10#
`
`DQS2
`DQS2#
`DM2/DQS11
`NC/DQS11#
`
`DQS3
`DQS3#
`DM3/DQS12
`NC/DQS12#
`
`DQS8
`DQS8#
`DM8/DQS17
`NC/DQS17#
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`CB0
`CB1
`CB2
`CB3
`CB4
`CB5
`CB6
`CB7
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U1
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U2
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U3
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U4
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U5
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U10
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U11
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U12
`
`SCL
`
`U7
`SPD EEPROM
`A0
`A1 A2
`WP
`
`VSS
`
`SA0 SA1 SA2
`
`SDA
`
`VDDSPD
`
`VDD/VDDQ
`VREF
`
`VSS
`
`SPD EEPROM
`
`DDR2 SDRAM
`
`DDR2 SDRAM
`
`DDR2 SDRAM
`
`RS0#: DDR2 SDRAM
`RBA[2/1:0]: DDR2 SDRAM
`RA[13/12:0]: DDR2 SDRAM
`RRAS#: DDR2 SDRAM
`RCAS#: DDR2 SDRAM
`RWE#: DDR2 SDRAM
`RCKE0: DDR2 SDRAM
`RODT0: DDR2 SDRAM
`
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`Register
`
`U6
`
`R
`e
`g
`i
`
`st
`
`
`
`er
`
`U8
`
`PLL
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U9
`
`S0#
`BA[2/1:0]
`A[13/12:0]
`RAS#
`CAS#
`WE#
`CKE0
`ODT0
`
`RESET#
`
`CK0
`CK0#
`
`RESET#
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`7
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Functional Block Diagram
`
`Figure 3: Functional Block Diagram – Raw Card F, Parity
`
`Err_Out#
`RS0#: DDR2 SDRAM
`RBA[2/1:0]: DDR2 SDRAM
`RA[13/12:0]: DDR2 SDRAM
`RRAS#: DDR2 SDRAM
`RCAS#: DDR2 SDRAM
`RWE#: DDR2 SDRAM
`RCKE0: DDR2 SDRAM
`RODT0: DDR2 SDRAM
`
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM
`Register
`
`U6
`
`R
`e
`g
`i
`
`st
`
`
`
`er
`
`U12
`
`PLL
`
`SCL
`
`U7
`SPD EEPROM
`A0
`A1 A2
`WP
`
`VSS
`
`SA0 SA1 SA2
`
`SDA
`
`SPD EEPROM
`
`DDR2 SDRAM
`
`DDR2 SDRAM
`
`DDR2 SDRAM
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U10
`
`VDDSPD
`
`VDD/VDDQ
`VREF
`
`VSS
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U11
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U8
`
`Par_In
`S0#
`BA[2:0]
`A[15:0]
`RAS#
`CAS#
`WE#
`CKE0
`ODT0
`RESET#
`
`CK0
`CK0#
`
`RESET#
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U9
`
`DQS4
`DQS4#
`DM4/DQS13
`NC/DQS13#
`
`DQS5
`DQS5#
`DM5/DQS14
`NC/DQS14#
`
`DQS6
`DQS6#
`DM6/DQS15
`NC/DQS15#
`
`DQS7
`DQS7#
`DM7/DQS16
`NC/DQS16#
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`
`
`RS0#
`
`DQS0
`DQS0#
`DM0/DQS9
`NC/DQS9#
`
`DQS1
`DQS1#
`DM1/DQS10
`NC/DQS10#
`
`DQS2
`DQS2#
`DM2/DQS11
`NC/DQS11#
`
`DQS3
`DQS3#
`DM3/DQS12
`NC/DQS12#
`
`DQS8
`DQS8#
`DM8/DQS17
`NC/DQS17#
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`CB0
`CB1
`CB2
`CB3
`CB4
`CB5
`CB6
`CB7
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U1
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U2
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U3
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U4
`
`DM/ NU/ CS# DQS DQS#
`RDQS RDQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U5
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`8
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`General Description
`
`General Description
`DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
`ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
`modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
`essentially a 4n-prefetch architecture with an interface designed to transfer two data
`words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
`module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
`internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
`fers at the I/O pins.
`
`DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
`and CK# to capture commands, addresses, and control signals. Differential clocks and
`data strobes ensure exceptional noise immunity for these signals and provide precise
`crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-
`mitted externally, along with data, for use in data capture at the receiver. DQS is a
`strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
`troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
`with data for WRITEs.
`
`DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
`CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
`mands (address and control signals) are registered at every positive edge of CK. Input
`data is registered on both edges of DQS, and output data is referenced to both edges of
`DQS, as well as to both edges of CK.
`
`Serial Presence-Detect EEPROM Operation
`DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
`256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
`ule type and various SDRAM organizations and timing parameters. The remaining 128
`bytes of storage are available for use by the customer. System READ/WRITE operations
`between the master (system logic) and the slave EEPROM device occur via a standard
`I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
`(WP) is connected to VSS, permanently disabling hardware write protection.
`
`Register and PLL Operation
`DDR2 SDRAM modules operate in registered mode, where the command/address input
`signals are latched in the registers on the rising clock edge and sent to the DDR2
`SDRAM devices on the following rising clock edge (data access is delayed by one clock
`cycle). A phase-lock loop (PLL) on the module receives and redrives the differential
`clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize
`system and clock loading. PLL clock timing is defined by JEDEC specifications and en-
`sured by use of the JEDEC clock reference board. Registered mode will add one clock
`cycle to CL.
`
`Parity Operations
`
`The registering clock driver can accept a parity bit from the system’s memory control-
`ler, providing even parity for the control, command, and address bus. Parity errors are
`flagged on the Err_Out# pin. Systems not using parity are expected to function without
`issue if Par_In and Err_Out# are left as no connects (NC) to the system.
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`9
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`Electrical Specifications
`
`Electrical Specifications
`Stresses greater than those listed may cause permanent damage to the module. This is a
`stress rating only, and functional operation of the module at these or any other condi-
`tions outside those indicated in each device's data sheet is not implied. Exposure to
`absolute maximum rating conditions for extended periods may adversely affect reliability.
`
`Table 8: Absolute Maximum Ratings
`
`Symbol
`VDD/VDDQ
`VIN, VOUT
`II
`
`Parameter
`VDD/VDDQ supply voltage relative to VSS
`Voltage on any pin relative to VSS
`Input leakage current; Any input 0V ≤ VIN ≤
`VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other
`pins not under test = 0V)
`
`IOZ
`
`IVREF
`1
`TC
`
`TA
`
`Output leakage current; 0V ≤ VOUT ≤ VDDQ;
`DQs and ODT are disabled
`VREF leakage current; VREF = Valid VREF level
`DDR2 SDRAM device operating case
`temperature2
`
`Module ambient operating temperature
`
`Notes:
`
`Command/Address, RAS#,
`CAS#, WE# S#, CKE, ODT, BA
`CK, CK#
`DM
`DQ, DQS, DQS#
`
`Min
`–0.5
`–0.5
`–5
`
`–250
`–5
`–5
`
`Max
`2.3
`2.3
`5
`
`250
`5
`5
`
`Units
`V
`V
`µA
`
`µA
`
`µA
`°C
`
`°C
`
`–36
`36
`Commercial
`0
`85
`Industrial
`–40
`95
`Commercial
`0
`70
`Industrial
`–40
`85
`1. The refresh rate is required to double when TC exceeds 85°C < TC ≤ 95°C.
`2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
`able on Micron’s Web site.
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`10
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`DRAM Operating Conditions
`
`DRAM Operating Conditions
`Recommended AC operating conditions are given in the DDR2 component data sheets.
`Component specifications are available on Micron's Web site. Module speed grades cor-
`relate with component speed grades.
`
`Table 9: Module and Component Speed Grades
`
`DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
`Module Speed Grade
`Component Speed Grade
`-1GA
`-187E
`-80E
`-25E
`-800
`-25
`-667
`-3
`-53E
`-37E
`-40E
`-5E
`
`Design Considerations
`Simulations
`
`Micron memory modules are designed to optimize signal integrity through carefully de-
`signed terminations, controlled board impedances, routing topologies, trace length
`matching, and decoupling. However, good signal integrity starts at the system level. Mi-
`cron encourages designers to simulate the signal characteristics of the system's memo-
`ry bus to ensure adequate signal integrity of the entire memory system.
`
`Power
`
`Operating voltages are specified at the DRAM, not at the edge connector of the module.
`Designers must account for any system voltage drops at anticipated power levels to en-
`sure the required supply voltage is maintained.
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`11
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`IDD Specifications
`
`IDD Specifications
`
`Table 10: DDR2 IDD Specifications and Conditions – 256MB
`
`Symbol
`IDD0
`
`-667
`810
`
`-53E
`720
`
`-40E Units
`675
`mA
`
`IDD1
`
`900
`
`810
`
`765
`
`mA
`
`Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
`component data sheet
`Parameter
`Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
`(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid com-
`mands; Address bus inputs are switching; Data bus inputs are switching
`Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4,
`CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
`tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
`bus inputs are switching; Data pattern is same as IDD4W
`Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE
`is LOW; Other control and address bus inputs are stable; Data bus inputs are
`floating
`Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
`CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
`bus inputs are floating
`Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
`HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
`bus inputs are switching
`Active power-down current: All device banks open; tCK =
`tCK (IDD); CKE is LOW; Other control and address bus inputs
`are stable; Data bus inputs are floating
`
`IDD2P
`
`45
`
`45
`
`45
`
`mA
`
`IDD2Q
`
`360
`
`315
`
`225
`
`mA
`
`IDD2N
`
`360
`
`315
`
`270
`
`mA
`
`IDD3P
`
`270
`
`225
`
`180
`
`mA
`
`54
`
`54
`
`54
`
`IDD3N
`
`450
`
`360
`
`270
`
`mA
`
`IDD4W
`
`1710
`
`1440
`
`1125
`
`mA
`
`IDD4R
`
`1620
`
`1350
`
`1035
`
`mA
`
`IDD5
`
`1620
`
`1530
`
`1485
`
`mA
`
`IDD6
`
`45
`
`45
`
`45
`
`mA
`
`Fast PDN exit
`MR[12] = 0
`Slow PDN exit
`MR[12] = 1
`Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
`MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
`Other control and address bus inputs are switching; Data bus inputs are switch-
`ing
`Operating burst write current: All device banks open; Continuous burst
`writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP
`= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
`inputs are switching; Data bus inputs are switching
`Operating burst read current: All device banks open; Continuous burst
`read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
`MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
`Address bus inputs are switching; Data bus inputs are switching
`Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
`interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
`address bus inputs are switching; Data bus inputs are switching
`Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
`dress bus inputs are floating; Data bus inputs are floating
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`12
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`IDD Specifications
`
`Table 10: DDR2 IDD Specifications and Conditions – 256MB (Continued)
`
`Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
`component data sheet
`Parameter
`Operating bank interleave read current: All device banks interleaving
`reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK =
`tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S#
`is HIGH between valid commands; Address bus inputs are stable during dese-
`lects; Data bus inputs are switching
`
`Symbol
`IDD7
`
`-667
`2250
`
`-53E
`2160
`
`-40E Units
`2070
`mA
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`13
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`IDD Specifications
`
`Table 11: DDR2 IDD Specifications and Conditions – 512MB
`
`Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
`component data sheet
`
`Parameter
`Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
`tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
`commands; Address bus inputs are switching; Data bus inputs are switching
`Operating one bank active-read-precharge current: IOUT = 0mA; BL =
`4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
`(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
`Address bus inputs are switching; Data pattern is same as IDD4W
`Precharge power-down current: All device banks idle; tCK = tCK (IDD);
`CKE is LOW; Other control and address bus inputs are stable; Data bus
`inputs are floating
`Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
`CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
`Data bus inputs are floating
`Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
`HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
`ta bus inputs are switching
`Active power-down current: All device banks open; tCK
`= tCK (IDD); CKE is LOW; Other control and address bus in-
`puts are stable; Data bus inputs are floating
`
`Fast PDN exit
`MR[12] = 0
`Slow PDN ex-
`it MR[12] = 1
`Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
`tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
`mands; Other control and address bus inputs are switching; Data bus
`inputs are switching
`Operating burst write current: All device banks open; Continuous
`burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
`(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
`Address bus inputs are switching; Data bus inputs are switching
`Operating burst read current: All device banks open; Continuous burst
`read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
`MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
`mands; Address bus inputs are switching; Data bus inputs are switching
`Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
`(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
`trol and address bus inputs are switching; Data bus inputs are switching
`Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
`address bus inputs are floating; Data bus inputs are floating
`
`Symbol
`IDD0
`
`-80E/
`800
`900
`
`-667
`810
`
`-53E
`720
`
`-40E Units
`720
`mA
`
`IDD1
`
`1035
`
`945
`
`855
`
`810
`
`mA
`
`IDD2P
`
`63
`
`63
`
`63
`
`63
`
`mA
`
`IDD2Q
`
`450
`
`405
`
`360
`
`315
`
`mA
`
`IDD2N
`
`495
`
`450
`
`405
`
`360
`
`mA
`
`IDD3P
`
`360
`
`315
`
`270
`
`225
`
`mA
`
`108
`
`108
`
`108
`
`108
`
`IDD3N
`
`630
`
`585
`
`495
`
`405
`
`mA
`
`IDD4W
`
`1755
`
`1530
`
`1260
`
`1035 mA
`
`IDD4R
`
`1845
`
`1620
`
`1305
`
`1035 mA
`
`IDD5
`
`2070
`
`1620
`
`1530
`
`1485 mA
`
`IDD6
`
`63
`
`63
`
`63
`
`63
`
`mA
`
`PDF: 09005aef82250868
`htf9c32_64_128x72.pdf - Rev. F 3/10 EN
`
`14
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2003 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2044
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
`IDD Specifications
`
`Table 11: DDR2 IDD Specifications and Conditions – 512MB (Continued)
`
`Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
`component data sheet
`
`Parameter
`Operating bank interleave read current: All device banks interleaving
`reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK
`= tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
`HIGH, S# is HIGH between valid commands; Address bus inputs are stable