`
`Presented by:
`AgigA Tech, Netlist, SMART
`
`PRESENTATION TITLE GOES HERE
`Flash Memory Summit 2014
`August 5-6, 2014
`
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`Hands-On Lab
`Acknowledgements
`
`Participating Companies:
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`Thanks to our Infrastructure Sponsors:
`
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`Agenda
`
`Part I
`NVDIMMs – Overview of how they work
`
`
`Part II
`NVDIMM Demonstration
`
`
`Part III
`Ultracapacitors – Overview of how they work
`
`
`Part IV
`Ultracapacitor Demonstration
`
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`NVDIMM – How it Works
`
`NVDIMM combines DRAM and Flash onto a single DIMM
`
`Operates as standard DRAM RDIMM
`
`Fast, low latency performance.
`
`Host only addresses the DRAM and has no
`
`direct access to the flash (NVDIMM-N classification)
`
`NVDIMM contains switches to switch control
`
`back and forth between host and NVDIMM controller
`
`NVDIMM controller moves data from DRAM
`
`to flash upon power loss or other trigger;
`
`can back up portions or all of DRAM upon command
`
`NVDIMM
`
`If power fails, Supercaps (or other power source)
`X86
`CPU
`provide back up power while DRAM is backed up to Flash
`
`Supercap Pack
`
`MRC (Memory Reference Code) configures NVDIMM controller to move data back from
`
`Flash to DRAM when recovery is needed
`
`All the benefits of SSD with none of the performance limitations and best endurance
`
`SMBus
`
`Host Interface
`
`DRAM
`
`NVDIMM
`Controller
`
`Quick
`Switches
`
`Flash
`
`DRAM
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`NVDIMM Application Scenario
`
`CPU
`
`~100 ms / 10ms
`
`~100 ns
`
`CPU
`
`NVDIMM
`
`Working DATA saved to
`slow SSD / HDD
`
`~100 ms /10ms
`
`SSD /
`HDD
`
`SSD
`
`Working DATA saved
`to fast NVDIMM,
`moved SSD later
`
`SSD/HDD has high latency
`
`> 1000X lower latency for persistent data access
`
`SSD/HDD has low throughput
`
`> 10X higher throughput for persistent data access
`
`Software Overhead slows effective performance
`
`No software overhead. Runs at HW speeds
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`NVDIMM Interface
`
`System Memory Map
`Mapping NVM into application
`BIOS table created at POST (Power on Self Test). This allows the driver to
`be made available
`
`Data Access Method
`Byte: Direct access to NVM, no driver layer required
`
`Block/File: port ramdisk or file system to NVM
`
`Other considerations (when the BIOS is set up some choices can be made)
`Processor cache policy for NV space
`
`Processor memory consistency model
`
`Impact of reduced data access time
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`Switching control to/from
`NVDIMM Controller
`
`• NVDIMM Controllers typically run the DRAM at the lower
`speed than the host
`• Saves power allowing smaller Supercap pack
`
`• The only way to switch clocks speeds or clock sources is
`to first put the DRAM into self-refresh
`
`• Upon power loss or other entry condition, the host must
`insure that DIMMs are placed in self-refresh
`
`• Main methods of putting the DIMMs in self-refresh
`• Standard ADR (see next page)
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`Intel ADR
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`• Asynchronous DRAM Refresh
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`• Hardware method for placing the DIMMs in self-refresh
`
`• No software involvement
`
`• Takes < 150us, removing the need for extra bulk
`capacitance
`
`• Pros
`• Simplest self-refresh entry method
`
`• Hardware controlled. Not impacted by software hangs
`
`• Cons
`• CPU caches are not flushed. Certain I/O buffers are not flushed either
`
`• Requires modifications to run-time software to implement fencing
`requirements
`
`
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`NVDIMM training slides provided by Intel
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`NVDIMM Entry Process using ADR
`
`A B
`
`C
`
`D
`
`E
`
`F
`
`G
`
`• Letters correspond to the timing diagram on the next page
`
`Detects A/C
`Power Loss
`
`Asserts ADR
`
`Shutdown down
`all power rails
`and clocks
`
`Flushes ADR
`protected
`buffers
`
`Puts all DIMMs
`in Self-Refresh
`
`Asserts
`ADR_COMPLETE
`
`Isolates DRAM
`from host and
`switches to
`Supercap power
`
`Copies DRAM to
`Flash
`
`Turns off
`Supercap
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`Board Logic
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`CPU/Chipset
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`NVDIMM
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`SAVE Operation
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`Source: Viking NVDIMM tutorial for SNIA
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`NVDIMM Restore/Recovery MRC Flow
`
`NVDIMM training slides provided by Intel
`
` Configure Memory
`Controller to drive
`CKE low
`
`Configure NVDIMM
`to Start Restore
`
`No
`
`Is Restore Complete?
`
`Yes
`
`Note Restore Status
`in MRC Output
`Structure
`
`Rewrite RC registers
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`MRC Start
`
`Yes
`
`Save in Progress?
`
`No
`
`Yes
`
`Train all
`DIMMs(including
`NVDIMMs) like
`standard DIMM
`
`Does NVDIMM contain
`valid Data?
`
`No
`
`End of Restore
`Process
`
`Run MemTest and
`MemInit on all
`DIMMs that didn’t
`have a successful
`restore
`
`Assert CKE
`
`Rewrite MRS
`Registers
`
`Did the NVDIMM Log
`an error?
`
`Yes
`
`Note Error in output
`Structure
`
`No
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`Population Rules
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`• There are no NVDIMM specific population rules
`
`• Normal DIMM population rules still apply(ex RDIMMs and LRDIMMs can’t be
`mixed)
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`• NVDIMMs and normal DIMMs may be mixed in the same channel
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`• NVDIMMs from different vendors may be mixed in the same system and even
`the same channel.
`
`• How the DIMMs are installed in a system will affect performance, so thought
`should be put into how DIMMs are populated
`
`• NVDIMM population tips
`
`•
`
`•
`
`•
`
`Interleaving DIMMs within a channel provides a very small performance benefit
`
`Interleaving DIMMS across a channel provides a very large performance
`benefit
`
`Two DIMMs of the same type should not be installed in the same channel
`unless all other channels in the system have at least one of that type DIMM.
`
`NVDIMM training slides provided by Intel
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`Memory Map
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`• MRC interleave code will insure that NVDIMMs are not
`interleaved with normal DIMMs while maintaining optimal
`interleaving
`
`• General Memory map assuming NUMA is enabled
`(Non Uniform memory Architecture)
`
`• All normal DIMM from Socket 0 interleaved together
`
`• All NVDIMMs from Socket 0 interleaved together
`
`• All normal DIMM from Socket 1 interleaved together
`
`• All NVDIMMs from Socket 1 interleaved together
`
`NVDIMM training slides provided by Intel
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`Example Optimal Interleaves
`
`4GB NVDIMM
`
`4GB NVDIMM
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`8GB DIMM
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`CH0
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`CH2
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`8GB DIMM
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`CH3
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`CPU
`
`CH1
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`8GB DIMM
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`8GB DIMM
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`4GB NVDIMM
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`4GB NVDIMM
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`Has a 4-way Interleave between normal DIMMs, and
`optionally a 4-way interleave between the NVDIMMs
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`4GB NVDIMM
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`4GB NVDIMM
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`CH3
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`CH0
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`CH2
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`CPU
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`CH1
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`8GB DIMM
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`8GB DIMM
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`Has a 2-way Interleave between normal DIMMs, and
`optionally a 2-way interleave between the NVDIMMs
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`NVDIMM training slides provided by Intel
`
`Empty
`
`Empty
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`8GB DIMM
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`CH0
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`CH2
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`8GB DIMM
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`CH3
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`CPU
`
`CH1
`
`8GB DIMM
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`8GB DIMM
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`4GB NVDIMM
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`Empty
`
`Has a 4-way Interleave between normal DIMMs
`
`4GB NVDIMM
`
`Empty
`
`8GB DIMM
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`CH0
`
`CH2
`
`8GB DIMM
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`CH3
`
`CPU
`
`CH1
`
`8GB DIMM
`
`8GB DIMM
`
`4GB NVDIMM
`
`Empty
`
`Has a 4-way Interleave between normal DIMMs, and
`optionally a 2-way interleave between the NVDIMMs
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`Industry Standardization
`
`NVDIMM gaining support from ecosystem
`Intel DDR4 NVDIMM support for Grantley
`
`Supermicro DDR4 NVDIMM support
`
`JEDEC Hybrid Memory Task Group
`12V and SAVE_n pins added to DDR4 DIMM socket
`
`12V in DDR4 socket will simplify NVDIMM power circuitry and
`cable routing
`
`SNIA NVDIMM SIG
`Established in 2013 to promote adoption of NVDIMMs
`
`
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`Part II NVDIMM Demonstration
`PRESENTATION TITLE GOES HERE
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`Goals
`
`Explain the hardware and software configuration
`
`
`Demonstrate interoperability among NVDIMM vendors
`
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`Show how the system recognizes the NVDIMM
`
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`Perform a Backup/Restore cycle with data validation
`
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`Configure the NVDIMM memory as a RAM Drive
`
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`Answer any questions about NVDIMM functionality
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`Configuration
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`Hardware
`System: Supermicro X9DRH-iF-NV
`
`BIOS: Supermicro 06/27/2104
`Erase/Arm in BIOS
`
`Processor: Intel Ivy Bridge
`Xeon E5-2690 V2 3.00GHz
`
`Installed Memory Configuration
`4GB RDIMM (standard)
`
`4GB Agigatech NVDIMM
`
`4GB Netlist NVDIMM
`
`4GB SMART NVDIMM
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`Software
`Operating System: CentOS 6.5 x86_64
`
`Kernel Version: 3.14 with Intel Storage Patch
`3.14.0-stor4.2
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`BIOS Settings
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`NVDIMM Configuration Menu
`Advance – Chipset Configuration – North Bridge
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`Interoperability and Recognition
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`Boot the system
`Observe no issues
`
`Display the E820 Memory Map Table
`Observe all 12 GB of NVDIMM RAM grouped as (protected)
`
`Defined as Type 12 (0xC) memory by Intel
`
`
`
`
`
`[ 0.000000] e820: BIOS-provided physical RAM map:
`[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000008efff] usable
`[ 0.000000] BIOS-e820: [mem 0x000000000008f000-0x000000000009ffff] reserved
`[ 0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved
`[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000733d4fff] usable
`[ 0.000000] BIOS-e820: [mem 0x00000000733d5000-0x000000007dd02fff] reserved
`[ 0.000000] BIOS-e820: [mem 0x000000007dd03000-0x000000007df34fff] ACPI NVS
`[ 0.000000] BIOS-e820: [mem 0x000000007df35000-0x000000007e619fff] reserved
`[ 0.000000] BIOS-e820: [mem 0x000000007e61a000-0x000000007e713fff] ACPI NVS
`[ 0.000000] BIOS-e820: [mem 0x000000007e714000-0x000000007f353fff] reserved
`[ 0.000000] BIOS-e820: [mem 0x000000007f354000-0x000000007f7fffff] ACPI NVS
`[ 0.000000] BIOS-e820: [mem 0x0000000080000000-0x000000008fffffff] reserved
`[ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed3ffff] reserved
`[ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
`[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000017fffffff] usable
`[ 0.000000] BIOS-e820: [mem 0x0000000180000000-0x000000047fffffff] (protected)
`[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
`[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
`[ 0.000000] e820: last_pfn = 0x480000 max_arch_pfn = 0x400000000
`[ 0.000000] e820: last_pfn = 0x733d5 max_arch_pfn = 0x400000000
`[ 0.000000] e820: [mem 0x90000000-0xfed1bfff] available for PCI devices
`[ 0.846932] e820: reserve RAM buffer [mem 0x0008f000-0x0008ffff]
`[ 0.846934] e820: reserve RAM buffer [mem 0x733d5000-0x73ffffff]
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`Backup / Restore and Verify
`
`Write a data pattern to the protected RAM
`
`Verify the data pattern
`
`Shut off system power
`
`Observe Backup operation
`
`Restore system power
`
`Observe Restore and Erase operations
`
`Verify the data pattern
`
`
`
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`Configure a RAM Drive
`
`Add the ADR driver to the kernel
`Modprobe
`
`
`Create and format a drive partition
`Fdisk
`
`
`Create a mount point and mount the drive
`Mount
`
`
`Display the newly mounted drive
`df
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`Part III Ultracapacitors
`Overview of how they work
`PRESENTATION TITLE GOES HERE
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`What is an Ultracapacitor?
`
`(also known as supercaps)
`
`Invented in U.S. by Robert A. Rightmire of SOHIO Company.
`
`U.S. Patent 3,288,641 “ELECTRICAL ENERGY STORAGE APPARATUS: This invention relates generally to the
`
`utilization of an electrostatic field across the interphase boundary between an electron conductor and an ion
`
`conductor to promote the storage of energy by ionic adsorption at the interphase boundary.” Nov. 29, 1966
`
`
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`
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`Electrochemical storage batteries and capacitors have been in existence for over 2000
`
`years (Baghdad battery BC), Volta “pile” 1800, to Ben Franklin 1848 who coined the term
`
`“battery”.
`
`Battery stores energy in chemical bonds that follow reduction-oxidation (REDOX) reactions. Mass transfer is
`
`involved.
`
`Capacitors store energy in electrostatic fields between ions in solution and a material. No mass transfer involved
`
`– hence no electrochemical wear out.
`
`Source: Joel Schindall, “Concept and Status of Nano-sculpted Capacitor Battery,” Presented at 16th Annual Seminar on Double Layer
`Capacitors and Hybrid Energy Storage Devices December 4-6, Deerfield Beach, Florida
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`Capacitor Terminology
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`Electrolyte: An ionic conducting liquid , type varies for each type of electrochemical capacitor.
`
`
`
`Separator: Porous paper, polymer or ceramic that prevents EC electrodes from shorting
`
`together. Must be ion conducting (porous) and electron blocking.
`
`
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`Current collectors: Metal foils used in each electrode to which the carbon electrode films are
`
`laminated. Typically aluminum foil.
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`
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`Charge: Ionic molecules in solution, electrons in conducting medium.
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`What is an EDLC Ultracapacitor?
`
`Electrochemical double layer capacitors (EDLCs) or ultracapacitors are electrochemical
`
`capacitors that have an unusually high energy density when compared to common
`
`capacitors, typically several orders of magnitude greater than a high-capacity
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`electrolytic capacitor.
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`
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`Schematic construction of a wound
`Ultracapacitor
`
`1.Terminals
`2.Safety vent
`3.Sealing disc
`4.Aluminum can
`5.Positive pole
` 6.Separator
` 7.Carbon electrode
` 8.Collector
` 9.Carbon electrode
`10.Negative pole
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`Construction of a wound Ultracapacitor
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`Layman example for difference
`between:
`
`Ultracapacitor
`
`Battery
`
`More power required for small
`time interval in 200 m race
`
`Constant but less power
`required for large time in 20
`km race
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`Ultracapacitors
`
`Advantages:
`
`High energy storage. This is a result of using a porous activated carbon electrode to achieve a high
`
`surface area.
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`Low Equivalent Series Resistance (ESR). Compared to batteries, EDLCs have a low internal
`
`resistance, hence providing high power density capability.
`
`Wide Temperature range. Capable of delivering energy down to -40°C with minimal effect on
`efficiency and can operate up 65°C and withstand storage up to 85°C
`
`Fast charge/discharge. Since EDLCs achieve charging and discharging through the absorption and
`
`release of ions and coupled with its low ESR, high current charging and discharging is achievable
`
`without any damage to the parts.
`
`
`
`Disadvantages:
`
`Low per cell voltage. EDLC cells have a typical voltage of 2.7V. Since, for most applications a higher
`
`voltage is needed, the cells have to be connected in series.
`
`
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`Ultracapacitor Safety
`
`U.S. DEPARTMENT OF TRANSPORTATION:
`
`This product is NOT classified as dangerous goods, per U.S. DOT regulations,
`under (see §173,176). Ultracapacitors as articles are not specifically listed
`nor exempted from hazardous materials regulations (HMR). The materials
`comprising the ultracapacitors are “…in a quantity and form that does not
`pose a hazard in transportation”. Therefore, the ultracapacitors are not
`subject to the HMR.
`
`Ultracap nail puncture test
`
`Battery nail puncture test
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`Ultracapacitor Equations
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`Energy = P x ∆t
`
`2 – Vmin
`Energy = ½ C (Vmax
`
`2)
`
`2 (P x ∆t)
`C =
`
`(Vmax2 – Vmin
`
`2)
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`Cell Balancing
`
`2.86V
`
`2.24V
`
`~2.55V
`
`~2.55V
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`Operating Life Range
`
`Lifetime vs Temperature
`
`Ultracapacitor
`Voltage
`
`2.0
`
`2.1
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`2.2
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`2.3
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`2.4
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`2.5
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`2.6
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`2.7
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`Temperature
`
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`34
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`45.00
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`40.00
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`35.00
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`30.00
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`25.00
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`20.00
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`15.00
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`10.00
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`5.00
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`0.00
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`Lifetime in Years
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`Ultracapacitor Testing
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`Ultracapacitor Testing
`
`Datasheet EOL
`1000 hrs @ 70%
`
`100.00%
`
`90.00%
`
`80.00%
`
`70.00%
`
`60.00%
`
`50.00%
`
`40.00%
`
`30.00%
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`20.00%
`
`10.00%
`
`0.00%
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`1 10 19 28 37 46 55 64 73 82 91 100 109 118 127 136 145 154 163 172 181 190 199
`
`Days
`
`Vendor A
`
`Vendor B
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`Vendor C
`
`Failed
`
`
`Not all
`Ultracaps
`are created
`equal!!
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`Ultracapacitor Testing
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`Ultracapacitor Module Form Factors
`
`PCI Express Card
`
`DIMM
`
`Fan
`Mount
`
`2.5” Drive
`
`Size will be dictated by:
`• Form Factor Constraints
`(x, y, z)
`• NVDIMM Density/Power
`• Backup Time
`• Lifetime Requirements
`• Max Temperature
`
`Other Form
`Factors
`
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`Part IV Ultracapacitor Demonstration
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`NVDIMM Lab Sponsor’s
`Company Profiles
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`Headquarters: San Diego, CA
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`Company History: Early technology development began in
`2006 as part of Simtek (acquired by Cypress in 2008),
`Cypress now sole investor
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`Sole focus since company inception has been on Non-
`Volatile RAM technology (better known today as NVDIMM)
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`Contact Us: info@agigatech.com
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`Visit Us: www.agigatech.com
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`Established: 2000
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`Headquarters: Irvine, CA
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`NASDAQ Symbol: NLST
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`Memory IP: 81 Patents (issued and pending)
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`“24x7, 18 month power cycling
`without single bit error”
`– Jeff Rabe, Dell Compellent
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`Contact Information: vault@netlist.com
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`Visit Us: www.netlist.com
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`Established: 1988
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`Headquarters: Newark, CA
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`Wide portfolio of memory products
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`Vertically integrated from wafer to final product
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`Worldwide footprint to support OEM customers
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`Helping to drive the adoption and standardization of NVDIMMs
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`SMART provides a variety of NVDIMM and supercap module form
`factors
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`Contact Information: info@smartm.com
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`Visit Us: www.smartm.com
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`Thank You!
`PRESENTATION TITLE GOES HERE
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