Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 1 of 35 PageID #: 9417
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`NETLIST, INC.,
`
`Plaintiff,
`
`v.
`
`SAMSUNG ELECTRONICS CO., LTD.,
`SAMSUNG ELECTRONICS AMERICA,
`INC., and SAMSUNG SEMICONDUCTOR,
`INC.,
`
`Defendants.
`
`§
`§
`§
`§
`§
`§ CIVIL ACTION NO. 2:21-CV-00463-JRG
`§
`§
`§
`§
`§
`§
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`CLAIM CONSTRUCTION ORDER
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`Netlist asserts claims from six patents relating to computer memory against Samsung
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`Electronics Co., Ltd., Samsung Electronics America, Inc., and Samsung Semiconductor, Inc.
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`(together, “Samsung”). U.S. Patent 10,949,339, entitled “Memory Module with Controlled Byte-
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`Wise Buffers,” relates to improving the performance and memory capacity of memory subsystems.
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`’339 Patent at 1:18–23. U.S. Patent 10,860,506, entitled “Memory Module With Timing-
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`Controlled Data Buffering,” generally concerns “multi-rank memory modules and methods of
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`operation.” ’506 Patent at 1:37–39. U.S. Patents 11,016,918 and 11,232,054, which are related and
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`share a common specification, concern computer memory devices that use different types of
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`memory. ’918 Patent at 1:66–2:2; see also ’054 Patent at 1:66–2:2. Finally, U.S. Patents 8,787,060
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`and 9,318,160, which are related and share a common specification, concern “systems and methods
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`for reducing the load of drivers of memory packages included on memory modules.” ’060 Patent
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`at 1:19–21; see also ’160 Patent at 1:21–23.
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 2 of 35 PageID #: 9418
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`The parties dispute the proper constructions of fourteen terms from the patents. Having
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`considered the parties’ briefing, along with arguments of counsel during the November 4, 2022
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`Markman Hearing, the Court resolves the disputes as follows.
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`I.
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`LEGAL STANDARDS
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`A.
`
`Generally
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`“‘[T]he claims of a patent define the invention to which the patentee is entitled the right to
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`exclude.’” Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005) (en banc) (quoting In-
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`nova/Pure-Water, Inc. v. Safari Water Filtration Sys., Inc., 381 F.3d 1111, 1115 (Fed. Cir. 2004)).
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`As such, if the parties dispute the scope of the claims, the court must determine their meaning. See,
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`e.g., Verizon Servs. Corp. v. Vonage Holdings Corp., 503 F.3d 1295, 1317 (Fed. Cir. 2007); see
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`also Markman v. Westview Instruments, Inc., 517 U.S. 370, 390 (1996), aff’g, 52 F.3d 967, 976
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`(Fed. Cir. 1995) (en banc).
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`Claim construction, however, “is not an obligatory exercise in redundancy.” U.S. Surgical
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`Corp. v. Ethicon, Inc., 103 F.3d 1554, 1568 (Fed. Cir. 1997). Rather, “[c]laim construction is a
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`matter of [resolving] disputed meanings and technical scope, to clarify and when necessary to
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`explain what the patentee covered by the claims . . . .” Id. A court need not “repeat or restate every
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`claim term in order to comply with the ruling that claim construction is for the court.” Id.
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`When construing claims, “[t]here is a heavy presumption that claim terms are to be given
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`their ordinary and customary meaning.” Aventis Pharm. Inc. v. Amino Chems. Ltd., 715 F.3d 1363,
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`1373 (Fed. Cir. 2013) (citing Phillips, 415 F.3d at 1312–13). Courts must therefore “look to the
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`words of the claims themselves . . . to define the scope of the patented invention.” Id. (citations
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`omitted). “[T]he ordinary and customary meaning of a claim term is the meaning that the term
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`would have to a person of ordinary skill in the art in question at the time of the invention, i.e., as
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 3 of 35 PageID #: 9419
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`of the effective filing date of the patent application.” Phillips, 415 F.3d at 1313. This “person of
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`ordinary skill in the art is deemed to read the claim term not only in the context of the particular
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`claim in which the disputed term appears, but in the context of the entire patent, including the
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`specification.” Id.
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`Intrinsic evidence is the primary resource for claim construction. See Power-One, Inc. v.
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`Artesyn Techs., Inc., 599 F.3d 1343, 1348 (Fed. Cir. 2010) (citing Phillips, 415 F.3d at 1312). For
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`certain claim terms, “the ordinary meaning of claim language as understood by a person of skill in
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`the art may be readily apparent even to lay judges, and claim construction in such cases involves
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`little more than the application of the widely accepted meaning of commonly understood words.”
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`Phillips, 415 F.3d at 1314; see also Medrad, Inc. v. MRI Devices Corp., 401 F.3d 1313, 1319 (Fed.
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`Cir. 2005) (“We cannot look at the ordinary meaning of the term . . . in a vacuum. Rather, we must
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`look at the ordinary meaning in the context of the written description and the prosecution history.”).
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`But for claim terms with less-apparent meanings, courts consider “‘those sources available to the
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`public that show what a person of skill in the art would have understood disputed claim language
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`to mean[,] [including] the words of the claims themselves, the remainder of the specification, the
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`prosecution history, and extrinsic evidence concerning relevant scientific principles, the meaning
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`of technical terms, and the state of the art.’” Phillips, 415 F.3d at 1314 (quoting Innova, 381 F.3d
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`at 1116).
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`II.
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`THE LEVEL OF ORDINARY SKILL IN THE ART
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`The level of ordinary skill in the art is the skill level of a hypothetical person who is pre-
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`sumed to have known the relevant art at the time of the invention. In re GPAC, 57 F.3d 1573, 1579
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`(Fed. Cir. 1995). In resolving the appropriate level of ordinary skill, courts consider the types of
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`and solutions to problems encountered in the art, the speed of innovation, the sophistication of the
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 4 of 35 PageID #: 9420
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`technology, and the education of workers active in the field. Id. Importantly, “[a] person of ordinary
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`skill in the art is also a person of ordinary creativity, not an automaton.” KSR Int’l Co. v. Teleflex
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`Inc., 550 U.S. 398, 421 (2007).
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`Here, neither party proffers a level of ordinary skill in the art in its briefing. Elsewhere,
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`however, Samsung asserted:
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`[a] POSITA in the field of the 054 Patent in 2008 would have had an ad-
`vanced degree in electrical or computer engineering, or a related field, and two
`years working or studying in the field of design or development of memory sys-
`tems, or a bachelor’s degree in such engineering disciplines and at least three years
`working in the field. . . . Such a hypothetical person would have been familiar with
`the JEDEC industry standards, and knowledgeable about the design and operation
`of standardized DRAM and SDRAM memory devices and memory modules and
`how they interacted with a memory controller and other parts of a computer system,
`including standard communication busses and protocols, such as PCI and SMBus
`busses and protocols. Such a hypothetical person would also have been familiar
`with the structure and operation of circuitry used to access and control computer
`memories, including sophisticated circuits such as ASICs, FPGAs, and CPLDs, and
`more low-level circuits such as tri-state buffers. Such a hypothetical person would
`further have been familiar with voltage supply requirements of such structures (e.g.,
`memory modules, memory devices, memory controller, and associated access and
`control circuitry), including voltage conversion and voltage regulation circuitry.
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`Pet. for Inter Partes Review of U.S. Patent No. 11,232,054, Dkt. No. 82-1 at 7–8. See also Pet.
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`for Inter Partes Review of U.S. Patent No. 11,016,918, Dkt. No. 87-2 at 8–9; Pet. for Inter Partes
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`Review of U.S. Patent No. 9,318,160, Dkt. No. 87-3 at 5 (similar); Pet. for Inter Partes Review
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`of U.S. Patent No. 10,949,339, Dkt. No. 87-3 at 5 (similar).
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`III. U.S. PATENT 10,949,339
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`A.
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`Background
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`According to the ’339 Patent, designing memory subsystems requires balancing memory
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`density, power dissipation, speed, and cost. ’339 Patent at 2:5–7. Adjusting one of these may
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 5 of 35 PageID #: 9421
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`negatively affect the others. Id. at 2:7–12. For example, the ’339 Patent notes two ways of increas-
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`ing memory space: (1) an address decoding scheme, and (2) combining chip-select and address
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`signals “to increase the number of physically addressable memory spaces . . . .” Id. at 5: 15–25.
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`But because both ways add memory chips, the system outputs have a heavier load. That, in turn,
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`slows the system and increases the necessary power. Id. at 4:27–33. Moreover, it results in uneven
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`propagation delay, which can negatively affect internal timing of accessing memory. Id. at 4:38–
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`44. As examples, FIGS. 1–2 show prior-art systems in which differences in trace lengths or com-
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`plexity of the memory controllers affect system speed.
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`As shown in FIG. 3A (below), the ’339 Patent teaches arranging the memory devices 412
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`in multiple ranks A, B, C, D, and a module controller 430 configured to receive and register input
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`control signals from a memory controller 420. The address and control signals select one of the
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`multiple ranks to perform a read or write operation. In response, the module controller 430 outputs
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`a set of control signals that drive data signals between the memory controller 420 and the selected
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`rank. See generally id. fig.3A.
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 6 of 35 PageID #: 9422
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`Based on signals received from the control circuit 430, the data transmission circuits 416
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`selectively enable or disable access to the memory devices 412. For example, whereas a set of
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`control signals from the memory controller 420 may address two memory devices (e.g., 412A1 and
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`412B1), only one of those devices might be enabled depending on the state of the associated data
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`transmission circuit 4161. In FIG. 3A, the data transmission circuit 4161 enables or disables
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`memory devices 412A1 and 412C1 together and memory devices 412B1 and 412D1 together.
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`For claim construction, the relevant limitations are the module controller 430 and the data
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`transmission circuits 416, which the claims refer to as “byte-wise buffers”. Regarding those limi-
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`tations, Claim 1 recites a memory module comprising:
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`a module controller . . . configurable to receive from the memory
`controller via the address and control signal lines input address
`and control signals for a memory write operation to write N-bit-
`wide write data from the memory controller into a first N-bit-
`wide rank of the multiple N-bit-wide ranks, and to output regis-
`tered address and control signals in response to receiving the in-
`put address and control signals, wherein the registered address
`and control signals cause the first N-bit-wide rank to perform the
`memory write operation by receiving the N-bit-wide write data,
`wherein the module controller is further configurable to output
`module control signals in response to at least some of the input
`address and control signals; and
`a plurality of byte-wise buffers . . . configured to receive the module
`control signals, wherein each respective byte-wise buffer . . . has
`a first side configured to be operatively coupled to a respective
`set of data signal lines, a second side that is operatively coupled
`to at least one respective DDR DRAM device in each of the mul-
`tiple N-bit-wide ranks via respective module data lines, and a
`byte-wise data path between the first side and the second side in
`accordance with a latency parameter . . . ; [and]
`wherein the each respective byte-wise buffer further includes logic
`configurable to control the byte-wise data path in response to the
`module control signals, wherein the byte-wise data path is
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`enabled for a first time period in accordance with a latency pa-
`rameter to actively drive a respective byte-wise section of the N-
`bit wide write data associated with the memory operation from
`the first side to the second side during the first time period.
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`Id. at 19:40–61.
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`B.
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`The Disputed Terms From the ’339 Patent
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`1.
`
`the “drive” claim terms (ʼ339 Patent, Claims 1, 11, 19, 27)
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`Plaintiff’s Construction
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`Defendants’ Construction
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`plain and ordinary meaning
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`“each respective byte-wise buffer further includes logic config-
`urable to, in response to the module control signals, activate the
`byte-wise data path connected to a first DDR DRAM device (in
`a first N-bit-wide rank), and disable the byte-wise data path con-
`nected to a second DDR DRAM device (in a second N-bit-wide
`rank), to cause a respective byte-wise section of the N-bit wide
`write data associated with the memory operation to be sent from
`the first side to the first DDR DRAM device along the activated
`byte-wise data path and not sent to the second DDR DRAM de-
`vice along the disabled byte-wise data path during the first time
`period in accordance with a latency parameter”
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`Claim 1 recites a module controller and a plurality of byte-wise buffers, each of which has
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`a first side connected to data lines and a second side connected to physical memory. ’339 Patent at
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`19:40–52; see also id. at 21:66–22:5 (Claim 11); id. at 24:18–29 (Claim 19); id. at 26:17–26
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`(Claim 27). The claims also require logic configurable to enable a data path to “actively drive”
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`write data from one side of the buffer to the other side. See, e.g., id. at 19:53–67 (reciting logic
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`configurable to drive write data from the first side to the second side).
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 8 of 35 PageID #: 9424
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`This claim language is best understood with respect to FIG. 5 (above). As the patent ex-
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`
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`plains:
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`For a write operation . . . the control circuit 430, in one embodiment, provides en-
`able control signals to the control logic circuitry 502 of each data transmission cir-
`cuit 416, whereby the control logic circuitry 502 selects either path A or path B to
`direct the data. Accordingly, when the control logic circuitry 502 receives, for ex-
`ample, an “enable A” signal, a first tristate buffer 504 in path A is enabled and ac-
`tively drives the data value on its output, while a second tristate buffer 506 in path
`B is disabled with its output in a high impedance condition. In this state, the data
`transmission circuit 416 allows the data to be directed along path A to a first termi-
`nal Y1, which is connected to and communicates only with the first group of the
`memory devices 412, e.g., those in ranks A and C. Similarly, if an “enable B” signal
`is received, the first tristate 504 opens path A and the second tristate 506 closes path
`B, thus directing the data to a second terminal Y2, which is connected to and com-
`municates only with the second group of the memory devices 412, e.g., those in
`ranks B and D.
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 9 of 35 PageID #: 9425
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`Id. at 16:7–25. To simplify, depending on to where the data will be written, the control logic cir-
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`cuitry 502 selects either Path A or Path B and disables the other path by commanding the associ-
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`ated tristate buffer into a high-impedance state.
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`The parties’ dispute centers on what it means to “drive” data from one side of the buffer to
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`the other. More specifically, it concerns whether, when one path is enabled, the other paths must
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`be disabled. Samsung contends the claims require only one path be enabled at a time, for two
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`reasons. First, this is how FIG. 5 works. Dkt. No. 82 at 21–22. Second, during prosecution, the
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`applicants argued the “fork”—i.e., one path or the other, but not both—distinguished their inven-
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`tion from the prior art. Id. at 22–23. Netlist argues the inventors never disclaimed the plain meaning
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`of the claim language to limit the scope of the claims as suggested by Samsung.
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`The Court agrees with Samsung based on both the prosecution history and the specifica-
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`tion. During prosecution, the applicants wrote:
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`This claimed limitation . . . is about controlling the data paths between the memory
`devices and the bus interface so that the data paths are open for a time period to
`allow data to be driven between the memory devices and the memory controller.
`This allows the data paths to be kept closed to isolate the memory devices from the
`bus interface when the memory module is not communicating data with the memory
`controller.
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`Resp. to Office Action (Mar. 25, 2020), Dkt. No. 82-6 at 16 (emphasis added). In other words, the
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`claimed invention, unlike the cited prior art, is about selectively opening otherwise closed data
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`paths. See also, e.g., Resp. to Final Office Action (June 23, 2020), Dkt. No. 82-7 at 15–16 (arguing
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`the prior art teaches “write data is sent to both ports A and B of the switch 206/208”; thus, the prior
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`art’s statement “that the control unit 204 ‘causes Port B to be activated and Port A to be disabled’
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`cannot possibly mean activating a data path through Port B and disabling a data path through Port
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`A” (emphasis in original)); Amendment & Req. for Continued Examination, Dkt. No. 82-8 at 21
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`(explaining “[t]he data paths can thus be kept disabled to isolate the memory devices from the bus
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`interface, or vice versa, when the memory module is not communicating data with the memory
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`controller”); id. at 18 (arguing the prior art “reject[s] the idea of using switches to select a data
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`line” and “teaches away from switching data paths”). Although the applications remarks are
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`phrased in terms of “capability” and what the invention “allows,” a skilled artisan would nonethe-
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`less understand those statements as characterizing the applicants’ invention.
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`This is consistent with the specification. When describing the technological problem to be
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`solved, the patent emphasizes reducing the load at the outputs of the memory devices. ’339 Patent
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`at 4:27–31. In addition, the sole embodiment describing path selection during a write operation
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`disables one path within the buffers when the other path is enabled. Id. at 16:1–18 (“the control
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`logic circuitry 502 selects either path A or path B to direct the data”); id. at 17:30–44 (the data
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`transmission circuits “enabl[e] the proper data paths between the system memory controller 420
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`and the targeted or selected memory devices,” so “the memory controller 420 . . . sees four load-
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`reducing switching circuit loads, instead of sixteen memory device loads”); id. at 14:59–15:4 (“the
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`data transmission circuits . . . electrically couple only the enabled memory devices to the memory
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`controller and . . . electrically isolate the other memory devices 412 from the memory controller”).
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`Based on this intrinsic record, the Court adopts the so-called fork-in-the-road approach. A
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`skilled artisan would understand “driving” data from one side of the buffer to the other means,
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`when there are multiple paths in a buffer through which that data can be driven, enabling only one
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`of the data paths while the other possible paths are disabled. Thus, “to drive” as used in these
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`claims means “enabling only one of the data paths while the other possible paths are disabled.”
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 11 of 35 PageID #: 9427
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`2.
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`“module controller” claim terms (ʼ339 Patent, Claims 1, 11, 19, 27)
`
`Plaintiff’s Construction
`
`Defendants’ Construction
`
`No construction is necessary (i.e.,
`plain and ordinary meaning).
`
`“a control circuit configurable to receive from the memory
`controller via the address and control signal lines input ad-
`dress and control signals for a memory write opera-
`tion . . . and corresponding to a number of ranks of memory
`devices lower than the physical number of ranks of memory
`devices on the module, and in response to receiving the in-
`put address and control signals, to output registered address
`and control signals corresponding to the number of physical
`ranks of memory devices on the module . . .”
`
`The second limitation of Claim 1 recites:
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`a module controller . . . configurable to receive from the memory controller via the
`address and control signal lines input address and control signals for a memory
`write operation to write N-bit-wide write data from the memory controller into a
`first N-bit-wide rank of the multiple N-bit-wide ranks, and to output registered ad-
`dress and control signals in response to receiving the input address and control sig-
`nals, wherein the registered address and control signals cause the first N-bit-wide
`rank to perform the memory write operation by receiving the N-bit-wide write data,
`wherein the module controller is further configurable to output module control sig-
`nals in response to at least some of the input address and control signals[.]
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`’339 Patent at 19:24–39. The dispute concerns the “multiple N-bit-wide ranks,” which Samsung
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`contends must be lower than the number of physical memory devices (i.e., chips) on the memory
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`module. Dkt. No. 82 at 27–28. Netlist refers to this concept as “rank multiplication” as described
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`by U.S. Patents 7,289,386 and 7,532,537, which the ’339 Patent incorporates by reference. Id. at
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`10:50–52.
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`Samsung’s reasoning stems from the ’339 Patent’s incorporation by reference of the ’386
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`and ’537 Patents. As the argument goes, the ’339 Patent discloses specific module-controller cir-
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`cuits only by referencing those patents. Those patents, in turn, only disclose mobile control circuits
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`in which the number of memory devices (e.g., virtual memory devices) is smaller than the physical
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`number of ranks of memory devices. Accordingly, says Samsung, the independent claims of the
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`’339 Patent must be so limited. Dkt. No. 82 at 27–28. Further supporting that conclusion, says
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`Samsung, Netlist’s position would exclude the sole embodiment disclosed by the ’339 Patent. Id.
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`at 28–29.
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`Samsung cites Techtronic Indus. Co. v. ITC, 944 F.3d 901 (Fed. Cir. 2019), and Cortland
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`Line Co. v. Orvis Co., 203 F.3d 1351 (Fed. Cir. 2000), but neither case is helpful to its position.
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`Cortland concerns a means-plus-function term, which invokes different claim-construction prin-
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`ciples. See Cortland, 203 F.3d at 1355–59. And Techtronic is distinguishable, concluding “the pa-
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`tentee disavowed claim scope in each of the patent’s sections” and consistently represented the
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`invention a certain way. Techtronic, 944 F.3d at 908. Samsung makes no such showing here.
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`Regarding Samsung’s suggestion its construction must be adopted to avoid excluding the
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`sole embodiment of the patent, that is incorrect. Netlist’s position is broader than Samsung’s and
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`therefore would include embodiments in which the number of N-bit-wide ranks is lower than the
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`number of physical memory devices on the memory module.
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`The Court rejects Samsung’s position, but otherwise gives the term its plain and ordinary
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`meaning.
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`3.
`
`“time period in accordance with a latency parameter” (ʼ339 Patent,
`Claims 1, 11, 34, 35)
`
`Plaintiff’s Construction
`
`Defendants’ Construction
`
`“a time period wherein both the start of the
`time period and duration of the time period de-
`pends on at least a latency parameter”
`
`Plain and ordinary meaning.
`
`The relevant claim limitation reads:
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`each respective byte-wise buffer further includes logic configurable to control the
`byte-wise data path in response to the module control signals, wherein the byte-
`wise data path is enabled for a first time period in accordance with a latency pa-
`rameter to actively drive a respective byte-wise section of the N-bit wide write data
`associated with the memory operation from the first side to the second side during
`the first time period[.]
`
`’339 Patent at 19:53–62 (emphasis added); see also id. at 21:66–2:5 (“each respective data trans-
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`mission circuit is configurable to enable the data paths for a first time period in accordance with a
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`latency parameter to actively drive [write data] from the first side to the second side during the
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`first time period”); id. at 28:22–27 (reciting, in Claims 34–35, that the first and second tristate
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`buffers, respectively, “are enabled for a first time period in accordance with a latency parameter”).
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`The parties dispute whether the recited “latency parameter” relates to just a start time (Samsung’s
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`position), or both a start time and a duration (Netlist’s position). See Dkt. No. 76 at 12; Dkt. No.
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`82 at 29 (“There is no support for Netlist’s argument that the ‘latency’ determines the duration of
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`the data transfer . . . .”).
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`“Latency parameter” appears only once in the specification. See id. at 3:26–28 (noting, in
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`the Summary, that “[i]n certain embodiments, the control circuit controls the byte-wise buffers in
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`accordance with a CAS latency parameter”). But the specification provides more detail on latency:
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`Column Address Strobe (CAS) latency is a delay time which elapses between the
`moment the memory controller 420 informs the memory modules 402 to access a
`particular column in a selected rank or row and the moment the data for or from
`the particular column is on the output pins of the selected rank or row. . . . During
`the latency, address and control signals pass from the memory controller 420 to the
`control circuit 430 which produces controls sent to the control logic circuitry 502
`(e.g., via lines 432) which then controls operation of the components of the data
`transmission circuits 416.
`
`For a write operation, during the CAS latency, the control circuit 430, in one em-
`bodiment, provides enable control signals to the control logic circuitry 502 of each
`
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 14 of 35 PageID #: 9430
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`data transmission circuit 416, whereby the control logic circuitry 502 selects either
`path A or path B to direct the data.
`
`Id. at 15:61–16:11 (emphasis added).
`
`From this, a skilled artisan would understand the “first time period” recited in the claims
`
`is not the latency. Rather, the “first time period” is the period during which the data path is enabled.
`
`Latency, on the other hand, is the time between (1) the moment the memory controller informs the
`
`memory modules to access the memory and (2) the moment the data is on the output pins. While
`
`there is a relationship between latency and the “first time period,” the claims do not limit when the
`
`“first time period” ends. Accordingly, the Court construes “time period in accordance with a la-
`
`tency parameter” as “a time period wherein the start of the time period depends on at least a latency
`
`parameter.”
`
`IV. U.S. PATENT 10,860,506
`
`A.
`
`Background
`
`The patent teaches a memory module having memory devices, a module control circuit,
`
`and buffer circuits between respective sets of data signal lines in a data bus and respective sets of
`
`the memory devices. Each buffer circuit is positioned between a set of data lines and a set of
`
`memory devices. The buffer circuit buffers data signals in response to module control and clock
`
`signals. Each respective buffer circuit includes a delay circuit configured to delay the respective
`
`set of data signals by an amount determined based on at least one of the module control signals.
`
`’506 Patent at [57].
`
`Only Claim 14 is at issue, which recites a method comprising the steps of:
`
`receiving, at the module control device, input C/A signals corre-
`sponding to a memory read operation via the C/A signal lines;
`
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 15 of 35 PageID #: 9431
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`outputting, at the module control device, registered C/A signals in
`response to the input C/A signals, wherein the registered C/A
`signals cause a selected rank of the multiple ranks to perform the
`memory read operation by outputting read data and read strobes
`associated with the memory read operation, and wherein a first
`memory device in the selected rank is coupled to the first data
`buffer and is configurable to output at least a first section of the
`read data and at least a first read strobe;
`outputting, at the module control device, module control signals;
`receiving, at each of the data buffers, the module control signals
`from the module control device;
`the method further comprising, at the first data buffer, in response to
`one of more of the module control signals:
`delaying the first read strobe by a first predetermined amount to
`generate a first delayed read strobe;
`sampling the first section of the read data using the first delayed
`read strobe; and
`transmitting the first section of the read data to a first section of
`the data bus; and
`the method further comprising, before receiving the input C/A sig-
`nals corresponding to the memory read operation at the module
`control device, determining the first predetermined amount
`based at least on signals received by the first data buffer.
`’506 Patent at 21:54–22:15. The parties’ dispute concerns the last claim limitation.
`
`B.
`
`“before receiving the input C/A signals corresponding to the memory read
`operation” (ʼ506 Patent, Claim 14)
`
`Plaintiff’s Construction
`
`Defendants’ Construction
`
`The step of “determining the first predeter-
`mined amount based on at least signals re-
`ceived by the first data buffer” occurs before
`the earlier recited step of “receiving, at the
`module device, input C/A signals correspond-
`ing to a memory read operation via the C/A
`signal lines.”
`
`“during one or more previous memory opera-
`tions”
`
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`Case 2:21-cv-00463-JRG Document 114 Filed 12/14/22 Page 16 of 35 PageID #: 9432
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`Relying mainly on prosecution history, Samsung’s construction comes from the allegedly
`
`interchangeable use of part of the disputed term with Samsung’s construction during prosecution.
`
`Dkt. No. 82 at 19. More specifically, Samsung’s argument hinges on Netlist’s post-allowance
`
`amendment of nine claims to replace “before the memory read operation” with “during one or
`
`more previous memory operations.” Id. When making those amendments, Netlist represented to
`
`the Office that “[n]o new matter was added.” Dkt. No. 82 at 19. Thus, says Samsung, the disputed
`
`term has the same scope of “before the memory read operation,” and the alleged interchangeability
`
`of the two phrases with respect to the amended claims also extends to the disputed phrase in
`
`Claim 14. Id. at 19–20.
`
`The Court disagrees for two reasons. First, “interchangeability” of terms is not a basis for
`
`construing claims. Second, even if it was, Samsung’s reasoning is backwards. If anything, Netlist’s
`
`position during prosecution was that the new phrase meant the same thing as the old phrase—
`
`because “no new matter was added”—not the other way around.
`
`Samsung also relies on the specification, arguing certain excerpts show the disputed phrase
`
`occurs “during one or more previous memory operations.” Id. (citing ’506 Patent at 4:9–19, 18:29–
`
`40, 18:49–64). But even if true, that is not inconsistent with the plain and ordinary meaning of the
`
`claim language.
`
`The disputed phrase is clear. The step of “determining the first predetermined amount based
`
`on at least signals received by the first data buffer” occurs before the earlier recited step of “re-
`
`ceiving, at the module device, input C/A signals corresponding to a memory read operation via the
`
`C/A signal lines.”
`
`
`
`Netlist Ex 2032-p. 16
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`IPR2022-00996
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`Case 2:21-cv-00463-JRG