`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` Samsung Electronics Co. Ltd.
`
`Case No. IPR2022-00996
`
`Petitioner,
`
`Patent No. 11,016,918
`
` vs.
`
` Netlist, Inc.,
`
`Case No. IPR2022-00999
`
`Patent Owner.
`
`Patent No. 11,232,054
`
` -------------------------------/
`
`VIDEOCONFERENCE DEPOSITION OF ANDREW WOLFE, Ph.D.
`
`Thursday, March 16, 2023
`
`Volume I (Pages 1 - 199)
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` Reported Remotely and Stenographically by:
`
` JANIS JENNINGS, CSR No. 3942, CLR, CCRR
`
` Job No. 5807753
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` DEPOSITION OF ANDREW WOLFE, Ph.D.,
`
` appearing remotely, located in Santa Clara,
`
` California, taken on behalf of the Petitioner,
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` beginning at 9:06 a.m., on Thursday, March 16, 2023,
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` sworn remotely by Janis Jennings, Certified Shorthand
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` Reporter No. 3942, CCRR, located in the City of
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` Walnut Creek, County of Contra Costa, State of
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` California.
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` REMOTE APPEARANCES:
`
` For the Patent Owner Netlist, Inc.:
`
` IRELL & MANELLA LLP
`
` BY: H. ANNITA ZHONG, ESQ.
`
` 1800 Avenue of the Stars
`
` Suite 900
`
` Los Angeles, California 90067
`
` 310.277.1010
`
` hzhong@irell.com
`
` For the Petitioner Samsung Electronics Co., Ltd.:
`
` BAKER BOTTS LLP
`
` BY: THEODORE W. CHANDLER, ESQ.
`
` FERENC PAZMANDI, Patent Agent
`
` 101 California Street
`
` Suite 3200
`
` San Francisco, California 94111
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` 415.291.6200
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` ted.chandler@bakerbotts.com
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` I N D E X
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` WITNESS PAGE
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` ANDREW WOLFE, Ph.D.
`
` VOLUME I (Pages 1 - 199)
`
` EXAMINATION BY MS. ZHONG 5
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` E X H I B I T S
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` EXHIBIT PAGE
`
` Exhibit 2101 Intel Developer Forum "Fully 41
`
` Buffered DIMM (FB-DIMM) Design
`
` Considerations" dated 2/18/04
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` THURSDAY, MARCH 16, 2023; 9:06 A.M.
`
` ANDREW WOLFE, Ph.D.,
`
` the witness herein, was sworn and
`
` testified as follows:
`
` EXAMINATION 08:54
`
`BY MS. ZHONG: 08:54
`
` Q. Good morning, Dr. Wolfe. 08:54
`
` A. How are you? 09:07
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` Q. Can you please -- good. 09:07
`
` Can you please state your full name for the 09:07
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`record? 09:07
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` A. Andrew Wolfe. 09:07
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` Q. Okay. Dr. Wolfe, you're familiar with fully 09:07
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`buffered dual in-line memory modules; correct? 09:07
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` (Clarification requested by Reporter.) 09:07
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`BY MS. ZHONG: 09:07
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` Q. Dr. Wolfe, you are familiar with fully 09:07
`
`buffered dual in-line memory modules; correct? 09:07
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` A. I'm familiar with that term as it is used in 09:07
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`certain JEDEC standards. 09:07
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` Q. And fully buffered dual in-line memory 09:07
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`modules are abbreviated as FB-DIMM; correct? 09:08
`
` A. Sometimes they are. 09:08
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` Q. Okay. So if I use the abbreviation FB-DIMM, 09:08
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`can we agree that I am referring to the fully 09:08
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`buffered dual in-line memory modules? 09:08
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` A. As specified in the JEDEC specifications? 09:08
`
` Q. Sure. 09:08
`
` A. Okay. 09:08
`
` Q. And FB-DIMM includes a buffer on a memory 09:08
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`module; correct? 09:08
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` A. Yes, as that's defined in the JEDEC 09:08
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`specification, yes. 09:08
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` Q. Okay. And that buffer is referred to as an 09:08
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`advanced memory buffer or AMB; correct? 09:08
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` A. In some cases it is. 09:08
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` Q. The AMB receives information from a memory 09:08
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`controller of a host system; is that correct? 09:08
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` A. Under certain circumstances that can be 09:09
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`true. 09:09
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` Q. Under what circumstances it is not true? 09:09
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` A. Well, if you buy an FB-DIMM and it's still 09:09
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`in the box, it doesn't receive anything from any 09:09
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`memory controller. You have to install it in a 09:09
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`computer system and you have to configure the 09:09
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`computer system properly and you have to operate the 09:09
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`computer system. 09:09
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` Q. Okay. So when the FB-DIMM is inserted into 09:09
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`a memory slot of a properly configured computer 09:09
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`system, the AMB will receive information from the 09:09
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`memory controller of the host system; is that 09:09
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`correct? 09:09
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` A. It needs a little bit more than that. It 09:09
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`actually needs to be -- the computer system needs to 09:09
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`be operating, and it needs to be programmed to 09:09
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`interact with that particular memory module. 09:10
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` Q. Okay. So assume that if the FB-DIMM is 09:10
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`inserted into a memory slot, a properly configured 09:10
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`computer system that is operating and that is 09:10
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`programmed to interact with the particular memory 09:10
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`module, the MB receives information from the memory 09:10
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`controller of that host system; is that correct? 09:10
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` A. That would normally be true. 09:10
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` Q. Okay. And what information is received by 09:10
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`the AMB from the memory controller in that 09:10
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`situation? 09:10
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` A. Let me look at the specification. 09:10
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` Q. When you say "specification," which exhibit 09:10
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`are you referring to? 09:10
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` A. 1027. 09:10
`
` Q. 1027? 09:10
`
` A. Yes. 09:10
`
` Q. Okay. And that's JSD82-20; is that correct? 09:10
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` A. Yes. 09:11
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` Q. Okay. 09:11
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` A. The AMB receives clocks, it receives address 09:11
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`command bits, and it receives data and data strobe 09:11
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`signals. 09:11
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` Q. Where are you looking at? 09:11
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` A. I'm looking at Figure 1.1. 09:11
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` Q. And which page? 09:11
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` A. 3. 09:11
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` Q. Page 3. 09:11
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` And you are referring to the output on the 09:11
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`DDR I/O side; is that correct? 09:11
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` A. Correct. That's where it outputs the 09:11
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`information that is received over what are called 09:12
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`northbound/southbound links. 09:12
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` Q. What information -- I'm asking what 09:12
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`information it is received. 09:12
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` A. Well, that's the information that's 09:12
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`received. It's received over the northbound and 09:12
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`southbound links in an encoded form. 09:12
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` Q. Why don't you take a look at Exhibit 1028. 09:12
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` A. Okay. 09:12
`
` Q. Can you take a look at pages 11 and 12 of 09:12
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`Exhibit 1028. 09:12
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` A. Yes. 09:13
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` Q. Where are the address pins? 09:13
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` A. I didn't say there were address pins. The 09:13
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`pins are the northbound and southbound lanes. The 09:13
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`information that gets conveyed does include 09:13
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`addresses. 09:13
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` Q. So there are no address pins or control 09:13
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`pins? 09:13
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` MR. CHANDLER: Object to form. Object to 09:13
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`form. 09:13
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` THE WITNESS: There are no pins -- well -- 09:13
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` DEPOSITION REPORTER: Excuse me, Mr. Wolfe. 09:14
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`I'm sorry to interrupt. I'm getting an audio 09:14
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`feedback from somebody. Can we go off the record 09:14
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`real quick and let's see where it is coming from, 09:14
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`please. 09:14
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` MS. ZHONG: Sure. 09:14
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` (Off the record.) 09:14
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`BY MS. ZHONG: 09:15
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` Q. So there are no address pins or control 09:15
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`pins; is that correct, Dr. Wolfe? 09:15
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` MR. CHANDLER: Object to form. 09:15
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` THE WITNESS: No. I think that that would 09:15
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`be misleading. There are no pins that have those 09:15
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`specific names and there are no -- when you talk 09:15
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`about -- pins on the DIMM? Is that the question? 09:15
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`BY MS. ZHONG: 09:15
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` Q. Correct. 09:15
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` A. Yeah. There are no DIMM pins that have 09:15
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`those specific names, but there are pins, the 09:15
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`northbound and southbound lanes, that carry that 09:15
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`information so they perform that function. 09:15
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` Q. And the address and the control information 09:15
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`are sent as serialized packets; is that correct? 09:15
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` A. Serialized packets? They -- yes. They 09:16
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`are -- the information is sent to the advanced 09:16
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`memory buffer in the form of serialized packets. 09:16
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` Q. Okay. So unlike the most common DIMMs with 09:16
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`the dedicated second address and the control pins, 09:16
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`the FB-DIMM does not have dedicated address and 09:16
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`control pins; is that correct? 09:16
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` MR. CHANDLER: Object to form. 09:16
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` THE WITNESS: I want to be clear. When we 09:16
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`talk about the most common DIMMs, I assume we are 09:16
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`talking about unbuffered DIMMs of some type and, of 09:16
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`course, there are a number of different types that 09:16
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`were known at the time of the filing of these 09:16
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`patents. There are more types known today. 09:16
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` Those generally have pins that are used for 09:17
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`address and control, but there are often pins that 09:17
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`are shared between address functions and control 09:17
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`functions. So to that extent, they are not 09:17
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`dedicated to one or the other. 09:17
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` But as I explained before, the northbound 09:17
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`and southbound lanes on the fully buffered DIMM are 09:17
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`used for address and control communications, but 09:17
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`they are also used for data communications. 09:17
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`BY MS. ZHONG: 09:17
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` Q. Okay. So in the most common DIMMs, such as 09:17
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`RDIMMs, or registered DIMMs, SODIMMs, small outlined 09:17
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`DIMMS and the output DIMM connection -- 09:18
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` (Clarification requested by Reporter.) 09:18
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`BY MS. ZHONG: 09:18
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` Q. -- SODIMMs, or small outlined DIMMs, and 09:18
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`unbuffered DIMMs. Small outlined DIMMs, yeah, 09:18
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`SODIMMs, and unbuffered DIMMs or UDIMMs. 09:18
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` So in those DIMMs, data is not sent on the 09:18
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`same pins as for address signals; is that correct? 09:18
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` MR. CHANDLER: Objection to form. 09:18
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` THE WITNESS: Of course, there are many 09:18
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`different generations of those DIMM types at 09:18
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`different times and each one has its own 09:18
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`specification, so I would need to review them all to 09:18
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`give you an absolute answer. 09:18
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` But my recollection is that, generally, 09:19
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`there are separate pins that are used for data 09:19
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`communication as opposed to the pins that are used 09:19
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`for address and commands. 09:19
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`BY MS. ZHONG: 09:19
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` Q. Okay. But in FB-DIMMs, they are sent on the 09:19
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`same pins as for command and address; is that 09:19
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`correct? 09:19
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` MR. CHANDLER: Objection. Form. 09:19
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` THE WITNESS: Between the host computer and 09:19
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`the FB-DIMM, that is the case. 09:19
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`BY MS. ZHONG: 09:19
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` Q. Okay. What's an FB-DIMM? That's only for 09:19
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`the DDR2; correct? There are no DDR3 FB-DIMMs as 09:19
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`far as you know? 09:19
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` A. I don't recall one way or the other. There 09:19
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`certainly is a DDR2 FB-DIMM. 09:19
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` Q. Does your declaration rely on DDR3 FB-DIMMs? 09:19
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` A. Not that I can recall. 09:20
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` Q. And there are no DDR4 FB-DIMMs; correct? 09:20
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` A. I don't recall referring to any in my 09:20
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`declaration. 09:20
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` Q. Okay. So your declaration only referred to 09:20
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`a DDR2 FB-DIMM? 09:20
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` A. As far as I can recall right now. 09:20
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` Q. Okay. What is a termination voltage? 09:20
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` A. In general? 09:20
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` Q. For use with -- let me withdraw and ask. 09:20
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` Is a termination voltage used in connection 09:20
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`with a DDR2 FB-DIMM? 09:20
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` A. I believe it is, yes. 09:20
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` Q. Okay. What is it used for? 09:20
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` MR. CHANDLER: Objection. Form. 09:21
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` THE WITNESS: It's used to provide power to 09:21
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`signal termination networks. 09:21
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`BY MS. ZHONG: 09:21
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` Q. What does "signal termination" mean? 09:21
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` A. What does -- as I used it in that previous 09:21
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`phrase? 09:21
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` Q. Correct. 09:21
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` A. When a high-speed signal passes over a wire 09:21
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`that has what we call transmission line properties, 09:21
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`there is potential for that signal to reflect back 09:21
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`from the end of the wire. 09:21
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` Q. Uh-huh.
`
` A. We can reduce those reflections using what's 09:21
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`called a termination network, and in many cases, 09:22
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`that termination network is powered. 09:22
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` Q. So termination -- signal termination is not 09:22
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`required if you have a low-speed signal; is that 09:22
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`correct? 09:22
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` MR. CHANDLER: Objection. Form. 09:22
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` THE WITNESS: It depends on the 09:22
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`characteristics of the -- of the wiring and the 09:22
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`voltages that are used and the wiring properties and 09:22
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`what your definition of low speed is. 09:22
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` The speed of the signal with respect to 09:22
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`termination requirements has to do with the spectral 09:22
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`distribution of the energy, and that is primarily 09:22
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`reflected by the signal transition speed, not the 09:22
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`total amount of data that's being communicated. 09:23
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`BY MS. ZHONG: 09:23
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` Q. So in DDR2 FB-DIMM, what signals are the 09:23
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`termination voltage used to terminate? 09:23
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` A. The VTT voltage is used to terminate the 09:23
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`signals going to the DRAM chips. I would have to go 09:23
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`through the spec very carefully to figure out if 09:23
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`there were other places where it's used. 09:23
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` Q. Why don't you take a look at Exhibit 1028, 09:23
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`page 11, and the pin name for VTT as well as the 09:23
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`corresponding description. 09:24
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` A. I see that. 09:24
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` Q. So which signals are used to terminate with 09:24
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`VTT? 09:24
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` A. Well, as I said, I -- the ones that I recall 09:24
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`are address command and clock signals to the DRAMs, 09:24
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`but I would have to look very carefully at the 09:24
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`specification to see if there were any others. 09:24
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`That's the one that's documented on, for example, 09:24
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`page 15 or page 14. 09:24
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` Q. So if -- in FB-DIMM, if address command 09:24
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`signal information is transmitted on the same -- 09:24
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`through the same pin as for data, how can VTT be 09:24
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`selectively terminating the address command and 09:25
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`clock signals but not the data? 09:25
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` MR. CHANDLER: Objection. Form. 09:25
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` THE WITNESS: Are you referring to something 09:25
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`in my declaration? 09:25
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`BY MS. ZHONG: 09:25
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` Q. I'm just asking you. 09:25
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` A. So you're asking me about an unmodified 09:25
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`FB-DIMM? 09:25
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` Q. Correct. 09:25
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` A. I'm sorry. Can I hear the question one more 09:27
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`time? 09:27
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` Q. In FB-DIMM, you said that the address and 09:27
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`command information is transmitted on the same pins 09:27
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`as for data; correct? 09:27
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` MR. CHANDLER: Object to form. 09:27
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` THE WITNESS: From the host, that is true. 09:27
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`Not to the DRAMs. 09:27
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`/ / / 09:27
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`BY MS. ZHONG: 09:27
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` Q. Okay. So how can the FTT be used 09:27
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`to selectively terminate the address and command 09:27
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`information signals but not the data signals? 09:27
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` MR. CHANDLER: Objection. Form. And I 09:27
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`think you said "FTT." 09:27
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` (Clarification requested by Reporter.) 09:28
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` MS. ZHONG: FTT -- VTT. 09:28
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` MR. CHANDLER: Even with that correction, 09:28
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`objection to form. 09:28
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` THE WITNESS: So VTT can be used to 09:28
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`selectively enable termination between the AMB and 09:28
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`the DRAMs on the address and command signals without 09:28
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`impacting the termination of the data signals. 09:28
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`BY MS. ZHONG: 09:28
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` Q. So where on the termination resistors placed 09:28
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`between the FTT pins and the address command clock 09:28
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`signals to the DRAM, or they are terminated on the 09:29
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`motherboard? 09:29
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` MR. CHANDLER: Objection. Form. 09:29
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` THE WITNESS: Usually there is a termination 09:29
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`on each end, but there would be termination near the 09:29
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`DRAMs for the address control signals. There are 09:29
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`numerous other places where there's termination, but 09:29
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`I believe on FB-DIMM, the other terminations would 09:29
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`primarily be on-chip terminations. 09:29
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`BY MS. ZHONG: 09:29
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` Q. The on-chip terminations is not part of the 09:29
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`F -- VTT; correct? 09:29
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` MR. CHANDLER: Objection. Form. 09:29
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` THE WITNESS: On an unmodified FB-DIMM, I 09:29
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`believe that's correct. 09:30
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`BY MS. ZHONG: 09:30
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` Q. And in the modified Harris FB-DIMM, how 09:30
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`would that differ? 09:30
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` Let me withdraw and ask it this way. In 09:30
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`your declaration, you didn't say that the FTT -- let 09:30
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`me withdraw and ask. 09:30
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` In your declaration, you do not say that the 09:30
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`VTT would operate any differently in the Harris 09:30
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`FB-DIMM and the JEDEC-compliant FB-DIMM; correct? 09:30
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` A. Well, no. I think that there are certain 09:31
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`teachings from the FB-DIMM that are taken into 09:31
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`account into Harris, but I explained what the 09:31
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`combination would be and how Harris would be 09:31
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`modified in the declaration for the [simultaneous 09:31
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`speakers] --
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` Q. Did you contend -- did you contend that VTT 09:31
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`would be used for online -- on-die termination? 09:31
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` A. I don't recall everything that's in the 09:31
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`declaration. It's quite large, but the focus 09:31
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`appears to be for DRAM termination for VTT in the 09:32
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`embodiment that I'm looking at right now for grounds 09:32
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`2D and 3D. 09:32
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` Q. When you say for "DRAM termination," is it 09:32
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`for the on-die termination? 09:32
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` A. I don't believe so. There is a resistor 09:32
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`shown in the drawings. 09:32
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` Q. Okay. So for the modified Harris, the VTT 09:32
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`is used in the same manner as in the -- for the 09:32
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`JEDEC-compliant FB-DIMM -- 09:32
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` A. No, actually I --
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` Q. -- [Simultaneous speakers] command a clock's
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`signal to the DRAM -- 09:32
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` (Clarification requested by Reporter.) 09:32
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`BY MS. ZHONG: 09:32
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` Q. So in your declaration, the VTT is used in 09:33
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`the same set manner for the modified Harris FB-DIMM 09:33
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`as for the JEDEC-compliant FB-DIMM, which is for the 09:33
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`termination of the address command and clock signals 09:33
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`to the DDR2 devices; is that correct? 09:33
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` A. No, I think that's an overgeneralization. 09:33
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`Again, there are many different grounds that are 09:33
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`presented in the declaration. We'd have to go 09:33
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`through them all carefully. 09:33
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` But, for example, I do see that certainly 09:33
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`some of the grounds refer to DDR3 and some of the 09:33
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`grounds refer to a VTT voltage of 0.9 volts, which I 09:33
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`recall is the on-ground -- or the on-die termination 09:34
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`voltage. 09:34
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` Q. For Harris, you used a DDR3 combination? 09:34
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` A. Let me look. 09:34
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` Q. Are you confusing that with Spiers? 09:34
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` A. Let me look at the various combinations 09:34
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`here. Oh, I'm sorry. I may have these backwards. 09:34
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` For Harris, I have DDR2 combinations that do 09:34
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`show a variety of different VTTs, so those would be 09:35
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`used for a variety of different purposes. 09:35
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` Q. When you say "a variety of VTTs," which 09:35
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`paragraph are you referring to? 09:35
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` A. So in paragraph 247, I talk about a VTT of 09:36
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`1.2 volts and also of .9 volts. I'm sorry, 1.25 09:36
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`volts and .9 volts. 09:36
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` Q. Paragraph 247? 09:36
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` A. Yes. 09:36
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` Q. VTT is half of VDDQ; correct? 09:36
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` A. In some instances, it is. 09:36
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` Q. In which instance is -- it is not? 09:36
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` A. I believe in the instance of DDR2 SDRAM, it 09:36
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`can just be .9 volts independently of VDDQ. 09:37
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` Q. What is VDDQ in DDR2? 09:37
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` A. I'm sorry. I didn't get -- 09:37
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` Q. Let me withdraw and ask. 09:37
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` What is VDDQ for DDR2? 09:37
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` A. It's one of the power supply voltages. 09:37
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` Q. What's the value? 09:37
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` MR. CHANDLER: Objection to form. 09:37
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` THE WITNESS: It's 1.8 volts plus or minus 09:38
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`0.1 volts. 09:38
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`BY MS. ZHONG: 09:38
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` Q. And half of that is 0.9; correct? 09:38
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` A. It is. 09:38
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` Q. Okay. So the 0.9 volt VTT is half of the 09:38
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`DDR2 SDRAM, as you stated in paragraph 247; correct?
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` A. That nominal -- 09:38
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` (Clarification requested by Reporter.) 09:38
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`BY MS. ZHONG:
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` Q. Is half of the VDDQ for DDR2. 09:38
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` MR. CHANDLER: Objection. Form. 09:38
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` THE WITNESS: At the nominal value, that's 09:38
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`true. 09:38
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` MS. ZHONG: VDDQ is one word, VDDQ, as 09:38
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`letter Q. 09:38
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` MR. CHANDLER: And sometimes it's shown as 09:38
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`subscript. It doesn't have to be, but -- so the V 09:39
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`is always capitalized and then the letters after it, 09:39
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`like "TT" and "DD" or "DDQ" are sometimes shown as 09:39
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`subscript. 09:39
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` MS. ZHONG: Yeah, it's probably easier for 09:39
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`you just to type them all as like capitalized 09:39
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`letters. 09:39
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` DEPOSITION REPORTER: Thank you. I 09:39
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`appreciate that. 09:39
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`BY MS. ZHONG: 09:39
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` Q. And which SDRAMs have a VDD or VDDQ of 09:39
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`2.5 volts? 09:39
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` A. I don't recall them all off the top of my 09:39
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`head. 09:39
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` Q. That's DDR; correct? Why don't you take a 09:39
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`look at your paragraph 246. 09:40
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` A. For certain DDR devices. 09:40
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` Q. So do you remember -- do you see like your 09:40
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`quote for different generations, there's 3.3 volt, 09:40
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`2.5 volt, 1.8 volt and a 1.5 volts? 09:40
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` A. I do. 09:40
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` Q. So the -- so the 3.3 is for SDR SDRAM, 2.5 09:40
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`is for DDR1, 1.8V is for DDR2, and 1.5V is for DDR3; 09:40
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`correct? 09:40
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` A. For at least some examples of these, that's 09:40
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`true. 09:40
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` Q. Okay. You're not aware of any DDR1 FB-DIMM, 09:40
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`are you? 09:41
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` A. Not off the top of my head, no. 09:41
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` Q. Okay. And you certainly didn't cite any 09:41
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`JEDEC standards for DDR1 FB-DIMM; correct? 09:41
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` A. I did not. 09:41
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` Q. And you're not aware of any DDR1 FB-DIMM; 09:41
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`correct? 09:41
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` A. I don't recall one right now. 09:41
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` Q. And as far as you know, is FB-DIMM first 09:41
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`developed for DDR2? 09:41
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` MR. CHANDLER: Objection. Form. 09:41
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` THE WITNESS: That particular specification, 09:41
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`JESD82-20, was first developed for DDR2, as far as I 09:41
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`know. 09:41
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`BY MS. ZHONG: 09:42
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` Q. Now, for the memory controller to send data,