NAN CRC Handbook Publishedin
`
`HANDBOOK
`
`Editor-in-Chief
`
`Cooperation with ty iy oa canees
`
`PETITIONER ECOBEE
`EX. 1021
`
`001
`
`PETITIONER ECOBEE
`EX. 1021
`
`

`

`THE
`
`HANDBOOK
`
`Editor-in-Chief
`J. DAVID IRWIN
`
`0cRCPRESS
`
`♦• IEEE PRESS
`
`A CRC Handbook Published in Cooperation with IEEE Press
`
`002
`
`PETITIONER ECOBEE
`EX. 1021
`
`

`

`Library of Congress Cataloging-in-Publication Data
`
`The industrial electronics handbook/edited by J. Da,,id in.;n.
`p. cm.- -(The electrical engineering handbook series )
`Includes bibliographical references and index.
`ISBN 0-8493-8343 -9 (alk. paper)
`l. Industrial electronics-Handbooks, manuals, etc. I. Irv.in, J. ~ ;d, I 939-
`:-_'788 l.!52 1996
`.3-dc20
`'
`
`. 11. Series.
`
`11ti5 book contains information obtained from aulhenti and highly regarded sources. Reprinted material is quoted with permission, and sources are
`~ A wide variety of references are listed. Reasonable efforts ba\-e been made to publish reliable data and info rmation, but the editor, authors, and
`• r do not assume responsibility or liability for the validir,· of arry· materials or for the consequences of their use.
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`C 1997 b-· CRC Press LLC
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`International Swide..'li Boo Number 0-8493-8343-9
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`Printed in the United Stares oi. Amaica I 2 3 4 5 6 7 8 9 O
`aa a:id--free paper
`Prin
`
`003
`
`PETITIONER ECOBEE
`EX. 1021
`
`

`

`Boolean Operations on Bit Variable b
`
`OR
`b + 0 = b
`b +I= I
`
`XOR
`
`bEBO=b
`bEBl=b
`
`Logical shift
`
`59
`
`I
`
`-m
`d-
`~ r+- 1 -m
`
`Arithmetic shift Circular rotate
`
`Circular rotate
`through carry
`
`b3
`b2
`V O O
`b3
`b2
`
`b1
`I
`I
`
`bo
`0
`bo
`
`$
`
`b3
`0
`b3
`
`b2
`0
`b2
`
`b1
`1
`b1
`
`bo
`0
`bo
`
`0
`
`bo
`
`(b) Set b1
`
`( c) Toggle b1
`
`3.19 Logical operations used to alter a selected bit.
`
`ooice register. Table 3.4 summarizes the three Boolean
`applied to a one-bit Boolean variable.
`- ND operator can be used to force selected bits of a word
`illustrated in Figure 3.19a. The second operand is a bit
`called a mask that contains a O in each bit position that
`forced to 0, and a 1 in each bit position that is to be
`.-..:;:;.ii:Ilanged. Similar masks can be created for the OR operator
`selected bits to 1, and for the XOR operator to force
`hits to be complemented. These are illustrated in Figures
`and 3.19c, respectively.
`- input/output devices contain a status register whose bits
`:the readiness of the device to perform an operation. The
`operator can be used to isolate a selected bit of a byte read
`a. status register to determine if that bit is 0 or I. This is
`in Figure 3.20. Here the mask is used to force all bits
`en:ept for bit b1• If the zero flag of the CPU's processor
`register is set, indicating a result of 0000, then it follows
`= O; if the zero flag is not set, the result is nonzero which
`.,,..,.,,.....,bl= l.
`example, assume that a printer interface contains a status
`in which the rightmost bit indicates whether the printer
`· to accept another character to print. The following
`program loop will be continuously executed as long as the
`ready" bit is 0. The CPU will exit the loop and continue
`n as the ready bit becomes l.
`
`IN
`AND
`JZ
`
`AL, PrintStatus
`AL,0000 0001
`Check
`
`;read printer status register
`;isolated "printer ready" bit
`;go back to Check if printer not ready
`
`and rotate instructions slide bits right or left within a
`r or memory location as illustrated in Figure 3.21. These
`be used for extracting or combining bit fields within an
`
`I\
`
`b3
`0
`0
`
`b2
`0
`0
`
`b1
`1
`b1
`
`bo
`0
`0
`
`Figure 3.20 Using AND to isolate one bit.
`
`Figure 3.2 I Shift and rotate operations.
`
`operand, to convert data between parallel and serial form, and
`to perform multiplication and division by powers of 2.
`In a logical shift operation, the bits are shifted right or left by
`one bit position, with the vacated bit replaced by a 0. For unsigned
`numbers, this is equivalent to dividing or multiplying the number
`by 2. An arithmetic right shift implements a divide by 2 operation
`on a two's complement number by preserving the sign bit as the
`operand is shifted. Some CPUs allow an operand to be shifted
`by more than one bit position with a single instruction. The
`following 68000 example packs two BCD digits into a single byte
`by shifting one digit fo ur bits to the left and then combining
`the two digits.
`
`Check:
`
`SHL.B
`OR.B
`
`F4,D0
`DI,D0
`
`;shift BCD digit to upper nibble of DO
`;combine two BCD digits in DI and DO
`
`Circular rotate instructions perform a shift operation while
`replacing the vacated bit with the bit shifted out of the other
`end of the operand. A second rotate operation is often provided
`that rotates the number through the carry flag of the processor
`status register. In most CPUs, the bit shifted out of an operand
`is copied to the carry flag of the processor status register where
`it can be tested or used to support multi-precision shift opera(cid:173)
`tions. A multi-precision number can be shifted by using the carry
`flag as a link between parts of the number, allowing a bit shifted
`out of one part to be shifted into the other using a rotate(cid:173)
`through-carry operation. The following 8086 example multiplies
`a 32-bit number by 2 by shifting one byte at a time one bit to
`the left.
`
`SHL
`RLC
`RLC
`RLC
`
`NUMBER
`NUMBER+l
`NUMBER+2
`NUMBER+3
`
`;shift memory byte 1 bit left
`;shift carry and 2nd byte 1 bit left
`;shift carry and 3rd byte 1 bit left
`;shift carry and 4th byte 1 bit left
`
`Control Transfer
`
`The normal flow of a program is to execute instructions in order
`from sequential memory addresses. To control this flow, the
`program counter increments automatically after each instruction.
`Jump, branch, and subroutine call instructions interrupt the
`normal flow by transferring control of the program to some
`instruction other than the next one in sequence. This allow
`looping and decision-making programs to be written, as well
`as supporting procedure and function calls. The following are
`examples of instructions that unconditionally transfer control of
`a program to location X within the current program:
`
`004
`
`PETITIONER ECOBEE
`EX. 1021
`
`

`

`60
`
`8051 /8086:
`6805/68000:
`SPARC:
`
`JMPX
`JMP X or BR X
`BRAX
`
`Decision making and looping require conditional branch
`instructions that jump only if a given condition is true and
`continue with the next sequential instruction if the condition
`is false .
`Conditional branch instructions typically test selected bits of
`the processor status register, which reflect the result of a previous
`arithmetic or logical operation. The following 8086 program
`loop adds a list of four numbers in memory, decrementing the
`SI register at the end of each iteration and repeating the loop as
`long as SI is greater than or equal to 0.
`
`Start:
`
`MOV
`MOV
`ADD
`DEC
`JGE
`
`SI,3
`AL,O
`AL,TABLES [SI]
`SI
`Start
`
`;set counter to 3
`;clear accumulator
`;add next element of TABLE
`;subtract 1 from SI
`;repeat if SI 2: 0
`
`The relationship between two operands can be tested by sub(cid:173)
`tracting them and then testing the resulting condition codes
`according to Table 3.5. Many CPUs provide a compare instruction
`(CMP) that performs the subtraction and sets the condition
`code flags without altering either operand. The following 6805
`program branches to location RICK if the unsigned number in
`accumulator A is less than or equal to 10, using the "branch ifless
`or same" instruction to test the result of a compare instruction.
`
`Check: CMP
`BLS
`
`# 10
`RICK
`
`;subtract 10 fro m A
`;go to RICK if A lower than or same as 10
`
`Modular programming requires the ability to partition soft(cid:173)
`ware into separate subroutines, such as procedures and functions,
`that can be invoked as needed. This is supported by special
`subroutine call instructions instructions that jump from a main
`program to the start of a subroutine after saving a pointer to
`the next instruction in the main program, allowing a return to
`the main program after completing the subroutine.
`A subroutine call (CALL) or jump to subroutine (JSR) instruc(cid:173)
`tion typically pushes the current program counter onto the sys(cid:173)
`tem stack to save the address of the next instruction in the main
`
`Table 3.5 Condition Codes for Relational Operators
`
`Condition
`
`Symbol
`z
`Zero
`Not zero
`NZ
`Greater than
`G
`Greater than or GE
`equal
`Less than
`Less than or
`equal
`Above
`A
`Above or equal AE
`Below
`B
`Below or equal
`BE
`
`L
`LE
`
`Relation
`
`Nu mber
`type
`
`Both
`Both
`Signed
`Signed
`
`Signed
`Signed
`
`A =B
`A,t.B
`A> B
`A 2: B
`
`A< B
`A s B
`
`A> B
`A 2: B
`A< B
`A :S B
`
`Boolean
`condition
`
`z
`z
`(Ntfl V) + Z
`Nffi V
`
`Nffi V
`(Ntfl V) + Z
`
`Unsigned
`Unsigned
`Unsigned
`Unsigned
`
`C+Z
`C
`C
`C+Z
`
`Supporting Technolo ·
`
`program. A return (RET) or return from subroutine (RTS) -
`executed as the last instruction of the subroutine to pop
`program counter from the stack and thus return to the m ·
`program. The SPARC does not support a system stack; subro
`tines are called with a jump and link (JMPL) instruction, whi
`saves the program counter in register r31 of the current regis
`window, and then slides the window down 16 registers as,\
`illustrated in Figure 3.10. the subroutine returns to the m ·
`program by retrieving the return address from register r7 of ·
`register window, which corresponds to r3 l of the calling progr
`
`Input and Output
`Some CPUs utilize separate address spaces for memo
`and for input/output devices. In these cases, special instructio
`are provided to read information into the CPU from an inp
`device and to write information from the CPU to an outp
`device. The Intel CPUs support an isolated I/0 address spa
`that can be accessed only by the two special instructions IN
`OUT as follows:
`
`IN
`OUT
`
`AL,25
`25,AL
`
`;data from IO address 25 to AL register
`;data from AL register to IO address 25
`
`Processor Control
`
`These instructions manipulate various hardware elements wi
`the CPU and are therefore CPU-specific. The reader is refer
`to The SPARC Architecture Manual, Ver. 7 ( 1983, 1987) , Motor
`Inc. (1990 ), Brey (1 994), and Stewart (1993) for descriptions
`processor control instructions for specific CPUs.
`
`3.8 Interrupts and Exceptions
`
`Events often occur that require interruption of normal instr
`tion processing to perform some special action. Such exceptio
`events, or simply exceptions, can be triggered by condition
`naled by devices external to the CPU, or by conditions dete
`within the CPU.
`For example, desktop PCs often use a timer to interrupt
`CPU once per second to make it update an image of a cl
`displayed on the screen. PCs used in process control are typi
`interrupted by sensors that detect various conditions in the pl
`that require immediate attention. An example of an intern
`detected condition is an attempt to divide a number by 0, whi
`cannot produce a valid result. This type of exceptional conditi
`should suspend normal processing to abort the operation
`send a warning message to the user.
`A primary advantage of external interrupt is that a CPU
`work in parallel with one or more external processes, such
`printing a document, and be interrupted only when the pro
`requires attention. The alternative is to continuously mo ·
`the process by checking a status register in the device to de
`when the device requires attention. Such monitoring would p
`vent the CPU from doing other work while waiting for the de ·
`
`005
`
`PETITIONER ECOBEE
`EX. 1021
`
`