IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Patent of: Mamiko Yamaguchi et al.
`U.S. Patent No.:
`6,603,343
`Issue Date:
`August 5, 2003
`Appl. Serial No.: 10,171,983
`Filing Date:
`June 17, 2002
`Title:
`PHASE CORRECTION CIRCUIT FOR TRANSISTOR USING
`HIGH-FREQUENCY SIGNAL
`
`Attorney Docket No.: 00035-0029IP1
`
`DECLARATION OF DR. SAYFE KIAEI
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`1
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`EXHIBIT 1003
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`
`
`In re Patent of: Mamiko Yamaguchi et al.
`U.S. Patent No.:
`6,603,343
`Issue Date:
`August 5, 2003
`Appl. Serial No.: 10,171,983
`Filing Date:
`June 17, 2002
`Title:
`PHASE CORRECTION CIRCUIT FOR TRANSISTOR USING
`HIGH-FREQUENCY SIGNAL
`
`Attorney Docket No.: 00035-0029IP1
`
`DECLARATION OF DR. SAYFE KIAEI
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`1
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`EXHIBIT 1003
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`Arigna ’343 Patent
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`Table of Contents
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`ASSIGNMENT ............................................................................................. 4
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`QUALIFICATIONS .................................................................................... 4
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`SUMMARY OF CONCLUSIONS FORMED ......................................... 11
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`BACKGROUND KNOWLEDGE ONE OF SKILL IN THE ART
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`WOULD HAVE HAD PRIOR TO THE PRIORITY DATE OF THE
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`’343 PATENT ............................................................................................. 13
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`LEGAL PRINCIPLES ............................................................................... 14
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`A. CLAIM INTERPRETATION ............................................................................. 14
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`B. ANTICIPATION ............................................................................................ 15
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`C. OBVIOUSNESS ............................................................................................. 15
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`MATERIALS CONSIDERED .................................................................. 17
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`TECHNOLOGY OVERVIEW ................................................................. 18
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`A. DIODE CAPACITANCE ................................................................................. 18
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`B.
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`REACTANCE ................................................................................................ 18
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`OVERVIEW OF THE ’343 PATENT ...................................................... 22
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`OVERVIEW OF THE PROSECUTION HISTORY ............................. 30
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`SUMMARY OF THE PRIOR ART ......................................................... 31
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`A. OVERVIEW OF JEON ’412 ............................................................................ 31
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`B. THE CIRCUITS OF THE '343 PATENT AND JEON '412 HAVE SUBSTANTIALLY
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`SIMILAR TOPOLOGY AND FUNCTIONALITY ............................................................ 36
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`C. OVERVIEW OF JEON IEEE ........................................................................... 37
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`D. OVERVIEW OF YOSHIMASU ......................................................................... 41
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` ANALYSIS OF JEON ’412 AND JEON IEEE ....................................... 48
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`A. THE COMBINATION OF JEON ’412 AND JEON IEEE ..................................... 48
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`B. APPLICATION OF JEON ’412 AND JEON IEEE TO CLAIM 1 ........................... 53
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`C. APPLICATION OF JEON ’412 AND JEON IEEE TO CLAIM 2 ........................... 72
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` ANALYSIS OF YOSHIMASU AND JEON IEEE ................................. 73
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`A. THE COMBINATION OF YOSHIMASU AND JEON IEEE .................................. 74
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`B. APPLICATION OF YOSHIMASU AND JEON IEEE TO CLAIM 1 ........................ 80
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`C. APPLICATION OF YOSHIMASU AND JEON IEEE TO CLAIM 2 ........................ 92
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` TEMPERATURE COMPENSATION ..................................................... 95
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` CONCLUSION ........................................................................................... 97
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`I, Dr. Sayfe Kiaei, of Scottsdale, AZ, declare that:
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`1.
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`ASSIGNMENT
`I have been retained on behalf of Apple Inc., LG Electronics, Inc., and
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`Samsung Electronics Co., Ltd. ( collectively "Petitioners") and asked to review and
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`provide my opinion on the patentability of claims 1 and 2 of U.S. Patent No.
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`6,603,343 ("the '343 Patent"). I understand that Petitioners are requesting that the
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`Patent Trial and Appeal Board (“PTAB” or “Board”) institute an inter partes
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`review (“IPR”) proceeding of the ’343 Patent.
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`2.
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`I have been asked to provide my independent analysis of the ’343
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`Patent based on the prior art publications cited in this declaration.
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`3.
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`I am a professor at Arizona State University. I am being compensated
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`for my work as an expert on an hourly basis. My compensation is not dependent
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`on the outcome of these proceedings or the content of my opinions.
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` QUALIFICATIONS
`I am over the age of 18 and am competent to write this declaration. I
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`4.
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`have personal knowledge, or have developed knowledge of these technologies
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`based upon education, training, or experience, of the matters set forth herein.
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`5.
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`A detailed description of my professional qualifications, including a
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`listing of my specialties/expertise and professional activities, is contained in my
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`curriculum vitae, a copy of which is provided as EX-1004. In what follows, I
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`provide a short summary of my professional qualifications.
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`6.
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`In terms of my background and experiences that qualify me as an
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`expert in this case, I earned a Ph.D. in 1987 from Washington State University in
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`Electrical, Computer, and Energy Engineering.
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`7.
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`Since 2001 I have held the position of Motorola Endowed Chair
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`Professor in Analog and Radio Frequency Integrated Circuitry at the School of
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`Electrical, Computer, and Energy Engineering at Arizona State University in
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`Tempe, Arizona. I am also the Director of the National Science Foundation
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`Center, Connection One. Connection One is an industry/university cooperative
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`research center with over thirty industrial members and five university members
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`focused on developing communication system and networking technologies.
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`8.
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`I have graduated over 100 MS and PhD students working under my
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`supervision on their thesis, and many of them are professors in academia, or have
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`senior positions in the industry. Currently, I have 8 MS, PhD, and postdoc
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`students working with in my lab on research related to communication and
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`networking systems, wireless and wireline systems, RF, and integrated circuits. My
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`research is funded by various sources, including industry, federal agencies
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`including NSF, DARPA, ONR, DOE, and other, with an average total research
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`funding of $1M per year.
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`9.
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`I have been involved with wireline systems, cellular systems, RF
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`Integrated circuits, Analog/Digital Integrated Circuits, communications, digital
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`signal processing, and related areas for the last 30 years starting with the first
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`generation of mobile phones (an analog system called AMPS (for Advanced
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`Mobile Phone Service)). I have also worked on second generation (2G) and third
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`generation (3G) mobile phone technologies including GSM, EDGE, IS-95, 1X
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`CDMA, UMTS, and Wide band CDMA. These terms all refer to leading mobile
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`phone standards and technologies, which enjoyed widespread use in mobile
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`telephone networks throughout the world. I have also worked on other wireless
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`data communication technologies including Bluetooth, the global positioning
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`system (GPS), Wireless local area networks (LAN) (often known as Wi-Fi), and
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`related areas.
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`10. From 1985 through 1987, I worked with Boeing on the development
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`of signal processing and control systems.
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`11. From 1987 through 1993, I was a tenured Professor at Oregon State
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`University in the Electrical and Computer Engineering Department. In my over
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`thirty years of teaching experience, I have taught university courses in networking,
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`communication systems, RF, and electronics at both the undergraduate and
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`graduate level.
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`12. From 1993 to 2002, I was a Senior Member of Technical Staff with
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`the Wireless Technology Center and Broadband Operations at Motorola Inc.,
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`where I was responsible for the development of wireless system, cellular system,
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`RF integrated circuits, GPS, and Digital Subscriber Lines (DSL) transceivers.
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`13. From 1995-1998 I was at Motorola and worked on DSL (digital
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`subscriber line, a technology used for high speed Internet service over copper
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`telephone lines), DMT (discrete multitone transmission, a technology underlying
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`DSL and other wireline communication systems), OFDM (orthogonal frequency
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`division multiplexing, a technology for transmitting data on multiple frequencies at
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`the same time for wideband digital communication), wireline and wireless systems,
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`wireless networking, 1G-3G, UMTS, GPS and Bluetooth systems.
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`14.
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`I was involved with the design of two way radios at Motorola from
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`1993–1995. I designed RF LNA, Mixer, receive signal strength indicator (RSSI),
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`AGC (automatic gain controller), and the baseband analog and digital filtering
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`sections. I was also one of the main system architects for the Motorola Talkabout
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`Radio, a handheld radio system with over 100 million units sold. The transceiver I
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`developed for the Motorola Talkabout was a radio frequency transceiver for
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`transmitting and receiving radio signals at distances up to 35 miles.
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`15. From 1998–2002 I was in the Motorola cellular group called WITC
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`(Wireless integrated Technology Center) within the Motorola communication
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`enterprise. This group was responsible for the design and development of
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`integrated circuits for 1G (AMPS, Digital AMPS), 2G (GSM, EDGE), and 3G
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`(CDMA, WCDMA / UMTS, CDMA2000) transceiver. The products were
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`Motorola flip phone, Razor, iDEN, etc. During this time period, I was involved
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`with the design of RF front-end including LNA, variable gain LNA, active and
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`passive mixers, analog front-end, AGC, analog and digital filters, and related areas
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`in the wireless transceiver components. In these products, we used RSSI to vary
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`the gain of RF front end circuits, including LNA and mixer, and the analog circuits
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`including VGA. The circuits used RSSI to find the received signal strength and
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`vary the circuit gain to increase linearity, reduce power consumption, and enhance
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`the sensitivity of the transceivers. We used the RSSI and other signal processing
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`methods to minimize and filter out jammers, interferes, and adjacent channel
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`interferes. The RF IC’s developed were used in over 10’s of millions of Motorola
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`phones from 1998–2002.
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`16.
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`I have also been a consultant on various projects with Intel (designing
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`2G and 3G mobile telephone transceivers), Texas Instrument (developing 3G
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`cellular and Bluetooth technologies), Sony Wireless (developing GPS
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`technologies), Tektronics (designing wireless systems), and various other
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`consultancies. During my work in industry, I have designed and contributed to the
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`design of many radio transceivers for commercial products, including designs for
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`radio transceiver integrated circuits. Many of my designs are still in use today in
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`products manufactured by the companies I have worked for, including Motorola,
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`Intel, Sony, and more.
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`17. From 2002–2010 I was a consultant with Intel on the development of
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`2G and 3G RFIC circuits. From 2002–2005 I was consulting with SONY on the
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`development of GPS RF receivers. I also did some work with Texas instruments
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`on Bluetooth and GPS RF circuits.
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`18. From 1997 to 2001, I was the standards technical analyst for
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`Motorola. I studied the standards and attended the meetings of various standard
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`setting committees, including ITU, IEEE, and ETSI related to DSL, OFDM,
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`CDMA, 2G, and 3G systems. I am thus very familiar with the standards for
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`several wireless communications technologies, including the standards for mobile
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`telephones.
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`19.
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`I joined ASU in 2002 as a tenured full professor and Motorola
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`endowed chair in RFIC and analog circuits. At ASU, I developed a new course at
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`ASU on the design of wireless and RF transceivers. I thought that course for over
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`10 years. This course is EEE524, RFIC for Wireless Transmitters, which is a
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`graduate course at ASU. In this course, we cover design of LNA, Mixer, frequency
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`synthesizer, Variable gain LAN, and other related topics. I have also taught
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`courses on Electronics, VLSI, Analog IC design, RFIC, communications, and
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`related areas.
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`20.
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`I have published over a hundred journal and conference papers
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`covering topics such as communication systems, signal processing, radio
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`frequency, integrated circuits (IC), filter design, and related areas. A list of my
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`publications can be found in my CV, included as EX-1004.
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`21.
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`I am an IEEE Fellow, a distinction and the highest level of IEEE
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`membership awarded by the IEEE directors to recognize a high level of
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`demonstrated extraordinary accomplishments. The IEEE is the Institute of
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`Electrical and Electronics Engineers, the world’s largest association of technical
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`professionals whose objectives include the educational and technical advancement
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`of electrical and electronic engineering, telecommunications, computer
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`engineering, and related disciplines. I am a member of the IEEE Circuits and
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`Systems Society, IEEE Solid State Circuits Society, and IEEE Communication
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`Society, IEEE RF and Microwave committees, IEEE International Symposium on
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`Low Power Electronics and Design (ISLPED), IEEE Signal Processing Society,
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`IEEE Fellow Selection Committee, and many other International Electrical
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`Engineering societies. I was one of the key organizers to establish the IEEE Radio
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`Frequency Integrated Circuits (RFIC) symposium in 1995, and have been on the
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`executive committee, and technical committee of RFIC for the last 16 years. The
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`RFIC Symposium has grown and is now the premier international symposium in
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`the world where the latest RF circuits and components are presented. I have been
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`involved in several international conferences in the areas of RF, Communication,
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`Signal Processing, and IC design.
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`22.
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`I have received several awards including the Carter Best Teacher
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`Award, the IEEE Darlington Award (which is given for the best technical paper on
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`circuits and systems in the IEEE Circuits and Systems Society), and the Motorola
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`10X Rapid Design Cycle Reduction Award.
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`23.
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`I have been one of the key organizers of the IEEE International
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`Symposium on Low Power Electronics and Design (ISLPED) since 1995. I have
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`published papers and organized sessions on techniques for low-power cellular
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`phones at ISLPED. I have published a number of papers on the design and
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`development of low-power RF and wireless transceivers.
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`24. My experience and qualifications are further detailed in my
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`curriculum vitae, which is included as EX-1004.
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` SUMMARY OF CONCLUSIONS FORMED
`25. As part of my analysis, I have reviewed the ’343 Patent, relevant
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`excerpts of the prosecution history of the ’343 Patent, and Plaintiff Arigna
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`Technology Limited’s Preliminary Infringement Contentions As to Apple Inc.,
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`Arigna Technology Limited v. Samsung Electronics Co., Ltd, Samsung Electronics
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`America, Inc., and Apple Inc., Case No. 6:21-cv-943-ADA (W.D. Tex. Jan. 06,
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`2022) (EX-1007). I have also reviewed at least the following prior art references
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`and other materials:
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`Prior Art References and Other Materials
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`U.S. Patent No. 6,603,323 to Yamaguchi et al. (“the ’343 Patent”) (EX-1001)
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`Excerpts of Prosecution History of the ’343 Patent (Serial No. 10,171,983) (EX-
`1002)
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`U.S. Patent No. 6,222,412 to Jeon et al. (“Jeon ’412”) (EX-1005)
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`Jeon et al., “Input Harmonics control using non-linear capacitor in GaAs FET
`Power Amplifier,” 1997 IEEE MTT-S International Microwave Symposium
`Digest, 1997, pp. 817-820 (“Jeon IEEE”) (EX-1006)
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`Plaintiff Arigna Technology Limited’s Preliminary Infringement Contentions As
`to Apple Inc., Exhibit A, Arigna Technology Limited v. Samsung Electronics
`Co., Ltd, Samsung Electronics America, Inc., and Apple Inc., Case No. 6:21-cv-
`943-ADA (W.D. Tex. Jan. 06, 2022) (EX-1007)
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`Translation of Japanese Unexamined Patent Application Publication No. H4-
`40702 to Yoshimasu (“Yoshimasu”) (EX-1008)
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`Baker et al., CMOS Circuit Design, Layout, and Simulation, New York, Institute
`of Electrical and Electronics Engineers, Inc., 1998 (EX-1010)
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`U.S. Patent No. 4,249,122 to Widlar (EX-1011)
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`McClaning and Vito, Radio Receiver Design, Atlanta, Noble Publishing
`Corporation, 2000 (EX-1018)
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`Johnson et al., Basic Electric Circuit Analysis, Englewood Cliffs, Prentice-Hall,
`Inc., 1978 (EX-1019)
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`26. This Declaration explains the conclusions that I have formed based on
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`my analysis. To summarize those conclusions:
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`•
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`Ground 1: Based upon my knowledge and experience and my review of the
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`prior art publications in this declaration, I believe that claims 1 and 2 of the
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`’343 Patent are made obvious by the combination of Jeon ’412 and Jeon
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`IEEE.
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`•
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`Ground 2: Based upon my knowledge and experience and my review of the
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`prior art publications in this declaration, I believe that claims 1 and 2 of the
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`’343 Patent are made obvious by the combination of Yoshimasu and Jeon
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`IEEE.
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` BACKGROUND KNOWLEDGE ONE OF SKILL IN THE ART
`WOULD HAVE HAD PRIOR TO THE PRIORITY DATE OF THE ’343
`PATENT
`27.
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`I have been informed that a person of ordinary skill in the art is a
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`hypothetical person who is presumed to have the skill and experience of an
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`ordinary worker in the field at the time of the alleged invention. Based on my
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`knowledge and experience in the field and my review of the ’343 Patent and file
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`history, I believe one of ordinary skill in the art relating to, and at the time of, the
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`invention of the ’343 Patent would have been someone with at least a Master of
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`Science degree in an academic area emphasizing circuit design, such as electrical
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`engineering or an equivalent field (or a similar technical Master’s Degree, or a
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`higher degree) with a concentration in circuit design. Alternatively, one of ordinary
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`skill in the art would have been someone with a Bachelor’s Degree (or higher
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`degree) in an academic area such as electrical engineering. Additional education in
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`a relevant field could substitute for professional experience, or relevant experience
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`in the field could substitute for formal education.
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`28. My analysis and conclusions set forth in this declaration are based on
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`the perspective of a person of ordinary skill in the art having this level of
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`knowledge and skill as of the date of the alleged invention of the ’343 Patent
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`(“POSITA”). Based on instruction from Counsel, I have applied December 18,
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`2001 (the “Critical Date”), as the date of the alleged invention of the ’343 Patent.
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`29. Based on my experiences, I have a good understanding of the
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`capabilities of a POSITA. Indeed, I have taught, mentored, advised, and
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`collaborated closely with many such individuals over the course of my career.
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` LEGAL PRINCIPLES
`30.
`I am not a lawyer and I will not provide any legal opinions in this IPR.
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`Although I am not a lawyer, I have been advised that certain legal standards are to
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`be applied by technical experts in forming opinions regarding the meaning and
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`validity of patent claims.
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`A. Claim Interpretation
`I understand that claim terms are generally given their plain and
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`31.
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`ordinary meaning based on the patent’s specification and file history as understood
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`by a person of ordinary skill in the art at the time of the purported invention. In that
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`regard, I understand that the best indicator of claim meaning is its usage in the
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`context of the patent specification as understood by a POSITA. I further
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`understand that the words of the claims should be given their plain meaning unless
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`that meaning is inconsistent with the patent specification or the patent’s history of
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`examination before the Patent Office. I also understand that the words of the
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`claims should be interpreted as they would have been interpreted by a POSITA at
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`the time of the invention was made (not today).
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`B. Anticipation
`I understand that a patent claim is invalid as anticipated if each and
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`32.
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`every element as set forth in the claim is found, either expressly or inherently
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`described, in a single prior art reference. I also understand that, to anticipate, the
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`reference must teach all of the limitations arranged or combined in the same way
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`as recited in the claim. I do not rely on anticipation in this declaration.
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`33. With respect to inherency, I understand that the fact that a certain
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`result or characteristic may occur or be present in the prior art is not sufficient to
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`establish the inherency of that result or characteristic. Instead, the inherent
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`characteristic must necessarily flow from the teaching of the prior art.
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`C. Obviousness
`I understand that a patent claim is invalid if the claimed invention
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`34.
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`would have been obvious to a person of ordinary skill in the field at the time of the
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`purported invention, which is often considered the time the application was filed.
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`Even if all of the claim limitations are not found in a single prior art reference that
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`anticipates the claim, the claim can still be invalid.
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`35. To obtain a patent, a claimed invention must have, as of the priority
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`date, been nonobvious in view of the prior art in the field. I understand that an
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`invention is obvious when the differences between the subject matter sought to be
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`patented and the prior art are such that the subject matter as a whole would have
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`been obvious at the time the invention was made to a person having ordinary skill
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`in the art.
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`36.
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`I understand that, to prove that prior art or a combination of prior art
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`makes a patent obvious it is necessary to: (1) identify the particular references that,
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`singly or in combination, make the patent obvious; (2) specifically identify which
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`elements of the patent claim appear in each of the asserted references; and (3)
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`explain a motivation, teaching, need, market pressure or other legitimate reason
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`that would have inspired a person of ordinary skill in the art to combine prior art
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`references to solve a problem.
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`37.
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`I also understand that certain objective indicia can be important
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`evidence regarding whether a patent is obvious or nonobvious. Such indicia
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`include:
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`•
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`•
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`•
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`Commercial success of products covered by the patent claims;
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`A long-felt need for the invention;
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`Failed attempts by others to make the invention;
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`•
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`•
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`•
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`•
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`•
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`•
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`Copying of the invention by others in the field;
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`Unexpected results achieved by the invention as compared to the closest
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`prior art;
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`Praise of the invention by the infringer or others in the field;
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`The taking of licenses under the patent by others;
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`Expressions of surprise by experts and those skilled in the art at the making
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`of the invention; and
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`The patentee proceeded contrary to the accepted wisdom of the prior art.
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`38. To the extent these factors have been brought to my attention, if at all,
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`I have taken them into consideration in rendering my opinions and conclusions.
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` MATERIALS CONSIDERED
`39. My analysis and conclusions set forth in this declaration are based on
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`my educational background and experiences in the field (see Section IV). Based on
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`my above-described experience, I believe that I am considered to be an expert in
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`the field. Also, based on my experiences, I understand and know of the capabilities
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`of persons of ordinary skill in the field during the 1980s-1990s, and I taught,
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`participated in organizations, and worked closely with many such persons in the
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`field during that time frame.
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`40. As part of my independent analysis for this declaration, I have
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`considered the following: the background knowledge/technologies that were
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`commonly known to persons of ordinary skill in this art during the time before the
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`earliest claimed priority date for the ’343 Patent; my own knowledge and
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`experiences gained from my work experience in the field of the ’343 Patent and
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`related disciplines; and my experience in working with others involved in this field
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`and related disciplines.
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`41.
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`In addition, I have analyzed the publications and materials listed
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`above.
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` TECHNOLOGY OVERVIEW
`A. Diode Capacitance
`42. By the time of the Critical Date, the capacitance-voltage
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`characteristics of diodes had been well-understood for decades. A diode is
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`“reverse-biased” when the voltage at the diode’s anode is less than the voltage at
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`the diode’s cathode. When a diode is in a reverse-biased state, an increasing
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`reverse bias on the diode (for example, due to the anode voltage decreasing, the
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`cathode voltage increasing, or a combination thereof) causes the capacitance of the
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`diode to decrease. EX-1010, 33-35. Correspondingly, a decreasing reverse bias
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`causes an increase in the capacitance. This is caused by changes in the width of the
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`depletion region that is present in diodes such as Schottky diodes, pn-junction
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`diodes, and pin diodes. Id.
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`B. Reactance
`43. The reactance of a circuit element is the opposition to the flow of
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`varying current from the circuit element due to its inductance or capacitance. EX-
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`1019, 264-265. Reactance is associated with the impedance of an inductor or
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`capacitor and can be defined more specifically in different ways. However,
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`because the reactance of a circuit element (which may include multiple circuit
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`elements in combination) depends on the circuit element’s capacitance, a change in
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`the circuit element’s capacitance can be associated with a corresponding change in
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`the circuit element’s reactance. The definition of reactance with which I am most
`
`familiar, and which I believe a POSITA would have understood as of the Critical
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`Date, would suggest that capacitance and reactance are inversely proportional and
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`change in opposite directions. See, e.g., EX-1019, 264-265. This definition would
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`suggest that, as the reverse bias on a diode increases (e.g., as the cathode voltage of
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`the diode increases, for constant anode voltage), the reactance of the diode
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`increases.
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`44. However, for certain definitions of reactance or a reactance
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`component, a change in capacitance can be associated with, equivalent to, or an
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`example of a change in reactance or reactance component in the same direction as
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`the change in capacitance, such that an increasing capacitance is associated with,
`
`equivalent to, or an example of an increasing reactance or reactance component,
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`and a decreasing capacitance is associated with, equivalent to, or an example of a
`
`decreasing reactance or reactance component. A POSITA would have interpreted
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`19
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`Arigna ’343 Patent
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`this relationship as applying to the reactances referenced in the ’343 Patent. For
`
`example, the ’343 Patent describes that “the depletion capacitance Cd of the diode
`
`21 decreases inversely with the increase in potential of the gate of the transistor
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`100,” describes “to decrease the reactance component in response to an increase in
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`potential of the gate,” and describes “in order to decrease the reactance component
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`according to the increase in potential of the gate of the transistor.” EX-1001, 3:6-7,
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`5:3-5, 6:18-21. The increase in potential of the gate is described as causing changes
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`in the capacitance and a reactance component in the same direction (a decrease).
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`The ’343 Patent also describes “the reactance component Cd,”1 where Cd is also
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`described as “the depletion capacitance . . . of the diode.” EX-1001, 3:41-42,
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`4:47-48.
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`45.
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`In addition, the ’343 Patent, in describing the circuit of FIG. 1,
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`describes that a “depletion capacitance Cd of the diode 21 decreases inversely with
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`the increase in potential of the gate of the transistor 100 in order that the total
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`capacitance of CGS and Cd reaches a substantially constant value.” EX-1001, 5:36.
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`Other than use of the word capacitance in place of the word reactance, this
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`language closely mirrors the language of claim 1 of the ’343 Patent (of which FIG.
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`1 provides an example of a phase correction circuit), in which “the reactance of the
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`1 All emphasis is added unless indication otherwise.
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`20
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`Arigna ’343 Patent
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`circuit element decreases in response to an increase in potential of the gate,
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`wherein a sum of the reactance of the circuit element and a gate-source reactance
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`of the transistor remains substantially constant.”
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`46. Based on these disclosures, a POSITA would have understood and/or
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`would have found obvious that, for the purposes of interpreting the ’343 Patent,
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`changing capacitances are equivalent to or an obvious example of changing
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`reactances or reactance components, in the same direction as the changing
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`capacitances. It follows that a POSITA would have understood and/or would have
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`found obvious that, for the purposes of interpreting the ’343 Patent, a constant
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`capacitance is equivalent to or an obvious example of a constant reactance or a
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`constant reactance component.
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`47. This interpretation is consistent with statements made by the ’343
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`Patent’s applicant during prosecution and with the preliminary infringement
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`contentions filed by the Patent Owner. In a response to a non-final Office Action,
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`the applicant noted that “it is well known that a reverse biased diode functions as a
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`capacitor, i.e., a reactance.” EX-1002, 4. Patent Owner identifies a claim mapping
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`in which “the circuit element has a reactance component (i.e. capacitance) that
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`changes with potential difference.” EX-1007, 7. Patent Owner also contends that
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`“the ’343 Patent specification at 4:46-51 and 5:3-8 identifies the ‘reactance
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`component’ as equivalent to ‘capacitance’ (‘Cd’).” EX-1007, 10. These statements
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`21
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`Arigna ’343 Patent
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`equating “capacitance” to “reactance” and “reactance component” are consistent
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`with an interpretation of a change in capacitance as associated with, equivalent to,
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`or an example of a change in reactance or a reactance component in the same
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`direction as the change in capacitance.
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` OVERVIEW OF THE ’343 PATENT
`48. The ’343 Patent “relates to a phase correction circuit for a transistor
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`using a high-frequency signal.” EX-1001, 1:7-9. The Challenged Claims are
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`directed to techniques for compensating for changes in transistor reactance using a
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`circuit element connected to a gate of the transistor. As was well-established in this
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`field at the time of invention, when an AC voltage is applied to a capacitor, there
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`exists a time delay between the voltage across the capacitor and the current through
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`the capacitor. This delay is measured by the phase difference between the voltage
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`across the capacitor and the current flowing through the capacitor. For example,
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`for an AC signal, the phase difference is a quarter-cycle (90°) phase difference. For
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`more complex circuits, the phase difference is tan-1(X/R), where X is the reactive
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`component of the circuit and R is the real component. By altering reactance
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`components (e.g., by altering capacitances as performed in the ’343 Patent), phases
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`in the circuit are modified. See, e.g., EX-1019, 264-265.
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`49. FIG. 1 of the ’343 Patent, reproduced below in annotated form, shows
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`an example of a phase correction circuit. The phase correction circuit operates in
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`22
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`Arigna ’343 Patent
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`conjunction with a temperature compensation circuit. EX-1001, 4:1-63. The phase
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`correction circuit and temperature compensation circuit are each connected to a
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`gate of a transistor. The phase correction circuit includes a revere-biased diode, the
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`cathode of which is connected to the gate of the transistor. EX-1001, 4:59-5:2.
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`Annotated FIG. 1 of the ’343 Patent
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`APPLE-1001, Fig. 7 (annotated)
`
`50.
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`I first describe the operation of the temperature compensation circuit.
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`As temperature changes, the threshold voltage of the transistor also changes. EX-
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`1001, 4:33-38, FIG. 2. To provide for temperature-invariant operation, the
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`temperature compensation circuit applies a temperature-dependent voltage to the
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`gate of the transistor. EX-1001, 4:28-33, FIG. 4. For example, as shown in FIG. 4
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`23
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`Arigna ’343 Patent
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`of the ’343 Patent (reproduced below in annotated form) when the temperature
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`increases from T1 to T2, the voltage applied at the gate of the transistor (at
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`terminal P1) increases by 0.5 V. EX-1001, 4:28-33, FIG. 4. This voltage incr
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