Vt Compensated voltage-data a-Si TFT AMOLED pixel circuits
`
`James L. Sanford
`Frank R. Libsch
`
`Abstract— Active-matrix organic light-emitting-diode (AMOLED) displays are now entering the mar-
`ketplace. The use of a thin-film-transistor (TFT) active matrix allows OLED displays to be larger in size,
`higher in resolutions and lower in power dissipation than is possible using a conventional passive
`matrix. A number of TFT active-matrix pixel circuits have been developed for luminance control, while
`correcting for initial and electrically stressed TFT parameter variations. Previous circuits and driving
`methods are reviewed. A new driving method is presented in which the threshold-voltage (Vt) com-
`pensation performance, along with various circuit improvements for amorphous-silicon (a-Si) TFT
`pixel circuits using voltage data, are discussed. This new driving method along with various circuit
`improvements is demonstrated in a state-of-the-art 20-in. a-Si TFT AMOLED HDTV.
`
`Keywords—Activematrix,amorphous silicon(a-Si),organiclight-emittingdiode(OLED),light-emit-
`tingdiode(LED),thin-filmtransistor(TFT),thresholdvoltage,threshold-voltagecompensation.
`
`Introduction
`1
`Due to their high brightness and efficiency, the develop-
`ment of organic light-emitting diodes (OLEDs) has lead to
`considerable interest for use in displays.1 OLED display
`products were first commercialized incorporating passive-
`matrix addressing in 1999 for use in automotive stereo dis-
`plays.2,3 Passive-matrix OLED displays are now being used
`in mobile telephones and even electric shavers. While con-
`ventional passive-matrix addressing simplifies the display
`fabrication, the number of rows is limited to a few hun-
`dred.4,5 Since the OLED is on only when being addressed,
`high peak currents are required to obtain average brightness
`levels. Row line resistance, column line resistance, and vari-
`ous OLED electrical characteristics restrict display lumi-
`nance, size, format, and efficiency. Some improvements are
`possible by tiling multiple passive-matrix displays or by fab-
`ricating a monolithic array of passive-matrix sub-arrays with
`associated drive electronics on the substrate backside.6 For
`very-high-information-content displays, the cost of these
`approaches is likely to be prohibitive.
`Thin-film-transistor (TFT) active-matrix backplanes
`can virtually eliminate the limitations of display content,
`size, format, luminance, and efficiency. Kodak has incorpo-
`rated a small AMOLED display in their commercially
`available EasyShare LS633 digital camera.7 Large-area
`high-resolution AMOLED TFT displays are being demon-
`strated with active-matrix TFT backplanes.8–10 The largest
`AMOLED display demonstrated to date, for example, uses
`a-Si TFT backplanes to achieve 20-in. diagonal HDTV for-
`mats with peak brightness (>500 cd/m2), with an efficiency
`>20 cd/A NTSC white.10 TFT active-matrix backplanes
`were initially developed for making large-sized and high-
`resolution liquid-crystal displays (LCDs). The pixel circuit
`simply consists of a TFT connected to a storage capacitor
`
`and the pixel LC electrode. The impedance of the liquid-
`crystal materials used is that of a capacitor whose value var-
`ies as a function of applied voltage as the refractive index
`changes. TFT performance is sufficient to stabilize the stor-
`age-capacitor voltage and LC voltage within a row time. The
`percentage of time that the pixel TFT is on and conducts is
`very low (~0.1–1%). Applied data and LC voltages alternate
`polarity from frame to frame to avoid image sticking due to
`ion plating in the LC. The alternating data voltages and low
`duty factor on times tend to stabilize transistor charac-
`teristics such as threshold voltage for long operating life-
`times in AMLCDs.
`Driving OLEDs uniformly with TFTs is more chal-
`lenging than driving liquid crystal. The main reasons are (1)
`OLED current-dependent luminance, (2) high OLED
`capacitance, (3) large TFT dimensions with high gate-to-
`drain capacitance (Cgd) and gate-to-source capacitance
`(Cgs), and (4) threshold voltage and mobility variations. The
`drive TFT should provide a continuous current over a large
`portion of the frame time to efficiently drive the OLED to
`desired luminance levels. The pixel area limits the number
`of TFTs and their widths, which is directly proportional to
`TFT transconductance. As a result, the OLED driving TFT
`transconductance can be limited. The mobility (µ) of low-
`temperature polysilicon (LTPS) can be one to two orders of
`magnitude higher than that of amorphous-silicon (a-Si). As
`a consequence, LTPS TFT widths can be smaller, with pos-
`sibilities of allowing for more TFTs in the pixel area for
`additional error correction. In addition, the LTPS TFT ter-
`minal voltages may be lower, yielding better power-efficient
`operation. As a result of high gate capacitances, TFT on/off
`switching can create large voltage offsets. Thus, offset cor-
`rection is required. The OLED capacitance is so large that
`the OLED current and voltage cannot be driven into equi-
`
`Revised version of a paper presented at the 2003 SID International Symposium, Seminar, and Exhibition, held May 20–22, 2003, in Baltimore,
`Maryland, U.S.A., and at the 2003 International Display Research Conference, held September 16–18, 2003, in Phoenix, Arizona, U.S.A.
`The authors are with the IBM T. J. Watson Research Center, M/S 25-137, 1101 Kitchawan Road, Route 134, P.O. Box 218, Yorktown Height, NY
`10598; telephone 914/945-1568, fax -2141, e-mail: sanfordj@us.ibm.com
`© Copyright 2004 Society for Information Display 1071-0922/04/1201-0065$1.00
`
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`librium within a typical row time (10–30 µsec). This can
`result in luminance that depends upon the previous state.
`Pixel-to-pixel variations in Vt and µ add to unwanted lumi-
`nance variations. With LTPS, initial Vt and mobility vari-
`ations exist due to grain size and boundary variations.11
`Time-related electrical stress variations in both Vt and mo-
`bility usually occur.12,13 In contrast, in most a-Si processes,
`the initial Vt and µ are uniform within a backplane.10,14
`While time-related electrical stress may produce large Vt
`variations, there is typically little change in mobility.15 Op-
`timized AC terminal voltages help to minimize time-related
`electrical stress variations.16
`Various techniques have been employed to minimize
`the impact of TFT variations with the use of simple pixel
`circuits. For example, restricting the use of an AMOLED
`display to video can assure that all pixels experience the
`same electrical stress. Another method is to operate the
`OLED driving TFT in a highly nonlinear manner such as an
`on-off switch.17,18 In one method, to obtain gray-level images,
`the bits are sequentially written with binary-weighted tim-
`ing to the array. This requires a custom-designed frame
`buffer. In another method, the binary data bits are decoded
`to drive separate subpixel OLEDs.
`A lower cost solution is to send analog data to the pixel
`circuit and to have the driving method compensate for the
`Vt and µ variations in the OLED driving TFT. The need for
`Vt compensation and previous Vt compensation methods
`are discussed. A distinction is made regarding current or
`voltage data and the logical use of such data for a-Si and
`LTPS backplanes. Due to its inherent lower manufacturing
`cost, a-Si backplanes for driving OLEDs is of interest.
`Emphasis on lower cost also creates a need for simpler volt-
`age-data circuits along with simpler driving methods. New
`pixel circuits and driving methods with performance results
`are presented.19,20 Further improvements and display sys-
`tem integration methods are discussed.
`
`Prior art
`2
`Simple pixel circuits: The need for Vt
`2.1
`compensation
`The purpose of an ideal AMOLED pixel circuit is to convert
`the data signal into a predetermined non-varying current for
`the OLED. Almost all pixel circuits using only conventional
`active-matrix-addressing schemes are Vt dependent. To
`illustrate this point, two relatively simple pixel circuits, a
`voltage follower and a current source, are shown in Fig. 1.
`In Fig. 1(a), data in the form of voltage is written onto the
`data storage capacitor, C, by T1 when the gate line signal is
`switched high. Transistor T3 operates as a voltage source
`follower to provide OLED current. Operating in the saturation
`regime, T3 drain-to-source current, I, is proportional to (Vdata
`– VOLED – Vt)2 for Vdata < Vdd + Vt, where Vt is the T3
`threshold voltage. It is desirable for the OLED driving tran-
`sistor to operate in saturation so as to minimize current
`dependence on drain-to-source voltage. In addition to cur-
`
`FIGURE 1 — Simple AMOLED pixel circuits; (a) voltage follower, (b)
`current source.
`
`rent dependence on Vt, the current also depends on the
`OLED voltage. The OLED voltage may vary from pixel to
`pixel and increase slowly with usage, ~0.1–1 mV/hour, pro-
`viding additional sources of non-uniformity.
`The current dependence on OLED voltage is elimi-
`nated by using the circuit shown in Fig. 1(b). T3 is a PFET
`device connected in a common source arrangement, allow-
`ing T3 to operate as a current source. The current is propor-
`tional to (Vdd – Vdata – Vt)2 for Vdd + Vt > Vdata > VOLED –
`Vt. As such, the drive current is independent of the OLED
`voltage.
`There are some other operating issues with the cir-
`cuits in Fig. 1. First, turning T1 off will increase the voltage
`across C because of T1’s gate-to-source capacitance. This is
`a systematic effect that can be compensated for by modify-
`ing the applied data voltages. Second, as the OLED lumi-
`nance is changed from one frame to the next, the OLED
`voltage will change, which modifies the voltage across C due
`to T3’s Cgs coupling in Fig. 1(a) and T3’s Cgd coupling in
`Fig. 1(b). Several addressing frames using the same data
`level may be needed for stabilizing the luminance. Thus, a
`need exists for incorporating Vt compensation.
`
`Voltage-data Vt compensation
`2.2
`The first Vt-compensation AMOLED pixel circuit used volt-
`age data (Vdata) and four TFTs with two additional row line-
`control signals.21 The circuit is shown in Fig. 2. Seven
`sequential operations are performed to address each row.
`First, with a low SW input signal and a high AZ input signal,
`the gate line voltage is switched with Vdd on the data line.
`Second, the AZ signal is set low, turning T2 on. A voltage across
`both capacitors is developed that forces T3 to conduct.
`Third, the SW input signal is pulsed high, turning T4 off and
`isolating the circuit from the OLED. With T2 on, a voltage
`that is proportional to the threshold voltage of T3, due to T3
`conduction, is developed across both capacitors. Fourth, the
`AZ input voltage is switched high, turning T2 off. Fifth, the
`data voltage for luminance is then presented on the data
`line. A part of the data voltage is coupled onto the capacitor
`C by capacitor Cc. Sixth, the gate line signal is set high. Sev-
`
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`FIGURE 2 — Data voltage pixel with threshold compensation.
`
`enth, the SW input signal is pulsed low turning T4 on and
`allowing current to flow into the OLED. The OLED cur-
`rent is, to a first order, proportional to the square of the data
`voltage coupled onto capacitor C.
`The circuit in Fig. 2 is fairly complex. It uses four tran-
`sistors and two storage capacitors. In addition, two other
`signals and drivers, SW and AZ inputs, are needed for each
`row. Simulations have shown that there is not sufficient time
`to accurately set the threshold voltage and write data within
`a typical row time. To account for high OLED capacitance,
`a two-row timing scheme was developed for a prototype
`QVGA display.22 With this driving method, it is unlikely the
`circuit in Fig. 2 can be made to work for a higher-resolution
`display having shorter row times. Accurately setting the
`threshold voltage on the storage capacitor is a time-consum-
`ing operation.
`
`Current data Vt compensation
`2.3
`Another threshold-voltage compensation approach uses
`data in the form of current or current data (Idata).17 Data
`line current is used to directly set the current flowing
`through the OLED driving transistor. Both the circuit and
`driving method are simpler than the circuit shown in Fig. 2.
`Figure 3 shows two circuit implementations. The circuits
`consist of four transistors, one capacitor and only one addi-
`tional input. The driving method consists of four sequential
`steps. First, the SW signal is switched high turning off T4 to
`isolate the pixel circuit from VDD in Fig. 3(a) or from the
`OLED in Fig. 3(b). Second, in Fig. 3(a), a data current is
`put onto the data line while the gate line is pulled low, turn-
`ing on T1 and T2, allowing the data current to flow into the
`pixel circuit. In Fig. 3(b), a data current is pulled out of the
`data line while the gate line voltage is set high turning T1
`and T2 on. In both cases, the data current flows through
`both T2 and T3 until the current through T3 matches the
`data current. Third, the gate line voltage is switched high
`
`FIGURE 3 — poly-Si current data pixel circuits.
`
`in Fig. 3(a) and is switched low in Fig. 3(b). Fourth, the SW
`input signal is pulled, connecting the pixel circuit to Vdd in
`Fig. 3(a) and to the OLED in Fig. 3(b).
`Ignoring the capacitor-voltage errors arising from
`switching of the row and SW inputs, the Idata method does
`account for any changes in Vt and µ in the OLED driving
`transistor T3. However, for dark-gray data levels, the low
`data current is not able to charge or discharge the data line
`for pixel circuit to reach equilibrium within a row time.
`There are some solutions to this issue. One solution is to
`incorporate high data currents with a current mirror that
`provides a reduction in the ratio data current to the OLED
`current.9 However, this arrangement does not directly set
`the current of the OLED driving transistor. The current
`through the OLED driving TFT can be different than the
`current mirror ratio of the data current because of variations
`in fabrication and differences in electrical stress. Another
`solution is to modulate the SW input signal in Fig. 3 at a low
`duty factor to compensate for the use of high data currents.
`A third solution is to drive the SW input in Fig. 3 with time
`binary-weighted digital data.24 A reference current is used
`in the place of current data.
`Recently, threshold-voltage compensation circuits
`using Idata for an a-Si TFT active matrix are being consid-
`ered.25 Figure 4 shows an a-Si pixel circuit using only
`NFETs. The circuit operation is essentially the same as the
`circuits shown in Fig. 3. Since the drain and source currents
`are identical, it is only a matter of perspective to use NFETs
`to form current sources. The SW input signal can be elimi-
`nated by connecting the input to Vdd. This allows T4 to func-
`tion like a diode and still provide some power-supply
`isolation when writing.
`While a-Si is able to produce steady-state currents
`suitable for reasonable brightness levels, the terminal volt-
`ages are fairly large. Due to the high terminal voltages
`resulting from low µ the two transistors in series between the
`power supply and the OLED significantly add to the power
`dissipation. As a result, the circuit in Fig. 4 may not be suit-
`able for large-sized displays having high luminance. Fur-
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`FIGURE 4 — An a-Si current data pixel circuit.
`
`thermore, unlike poly-Si where the current data drivers may
`be designed into the display panel, a-Si backplanes must
`incorporate crystalline-silicon data drivers. Commercial
`Idata drivers are not available. An Idata driver for various dis-
`play sizes, formats, pixel designs, and brightness levels are
`more complex and costly than Vdata drivers to design and
`build.
`
`A new voltage-data Vt compensation
`3
`method for a-Si
`It is generally accepted that the backplane fabrication using
`a-Si is lower in cost than that for poly-Si. Since, a-Si mobility
`does not vary within a backplane or with electrical stress
`over time, it seems appropriate to use the Vdata compensa-
`tion method with a-Si. In contrast, it seems appropriate to
`use Idata with poly-Si since mobility varies across the back-
`plane. Vdata allows the use of low-cost commercial LCD
`data drivers and eliminates the cost associated with crystal-
`line-silicon Idata drivers.
`In the design of an AMOLED pixel circuit, there are
`many design tradeoffs such as cost, display lifetime, the
`number and size of the pixel circuit components, data volt-
`age range, and power dissipation. As seen with the Vdata
`pixel circuit shown in Fig. 2, additional row control signals
`
`FIGURE 5 — (a) Initial pixel circuit; (b) a simpler circuit.
`
`FIGURE 6 — Signal timing for Fig. 5(a).
`
`are needed. For a-Si backplanes, this requires a custom-
`designed crystalline-silicon row driver, which would be
`more expensive than commercial LCD row drivers. The on
`time or duty factor of the OLED current driving TFT needs
`to be a large part of the frame in order to produce sufficient
`luminance. Too much variation in Vt will produce objection-
`able luminance variation. The large duty cycle severely
`stresses the OLED driving TFT. By increasing the width of
`the OLED driving TFT, the terminal voltages can be reduced.
`On the other hand, the TFT width cannot be too large or
`else the TFT will not fit within the pixel area or leave room
`for the other pixel circuit components. It may also be neces-
`sary for the TFT terminal voltage polarities to be alternated
`to further reduce the electrical stress in order to meet the
`display lifetime requirements. The size of the data storage
`capacitor also impacts the time required to establish the
`threshold voltage, the time to write data, the amount of pixel
`area, the voltage offsets, and Vt errors due to switching sig-
`nals. In addition, the range of data voltages (just off to maxi-
`mum luminance) should be large relative to Vt to minimize
`the impact of Vt compensation errors. For operation in the
`saturation regime, the OLED driving TFT drain-to-source
`voltage needs to be equal to or greater than the data voltage
`range. A larger data voltage range results in higher power
`dissipation. The different design tradeoffs depend largely
`upon the application.
`Simpler Vdata Vt compensation pixel circuits are possi-
`ble by using multilevel cathode voltages, use of the OLED
`capacitance, elimination of write data conduction, and
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`FIGURE 7 — Figure 5 equivalent circuits for the different circuit
`operation.
`
`device merging. An initial pixel circuit and signal timing
`incorporating a multilevel cathode voltage is shown in Figs.
`5(a) and 6, respectively. The equivalent circuit for each step
`is shown in Fig. 7. The frame time is segmented into a write
`Vt period, a write data period, and an expose period. This
`allows the write Vt step to be longer than a row time. At the
`beginning of the write Vt period (step 1), the Z input signal
`is momentarily pulled high to assure that a voltage greater
`than T3’s Vt (~10 V) is established on the storage capacitor
`Cs. The cathode voltage (Vca) is then switched from –18 V
`to +10 V with a low Z input (step 2). This reverse biases the
`
`FIGURE 9 — Circuits that inhibits write period conduction in T3.
`
`OLED via the reverse (source-to-drain) conduction of T3.
`In addition, the gate-to-drain voltage and drain-to-source
`voltage is reversed for removing residual charge induced
`from normal operation. The duration and voltages in this
`step can be adjusted to minimize the electrical stress due to
`T3 driving the OLED. The Vca is then set to 0 V with a high
`Z input signal (step 3). The T3’s drain-to-source conduction
`then establishes a voltage that is approximately equal to T3’s
`Vt across Cs and the OLED cathode-to-anode terminals.
`Since the settling time is non-linear, the duration and accu-
`racy are best determined with circuit simulations. During
`the write data period, the Z input is low while data is written
`onto node A. Since the OLED capacitance is much greater
`than Cs and T3’s Cgs, node B is maintained at –Vt during the
`write data period. The resulting voltage on Cs is Vdata + Vt.
`During the expose period, the Vca is set to –18 V assuring
`that T3 operates in saturation. The current through T3 and
`the OLED is proportional to (Vdata + Vt – Vt)2 or just Vdata.2
`SW and Vca are connected to all of the pixels in the display.
`The circuit in Fig. 5(b) functions in a similar manner,
`but without T2. The gate-line signal timing has been modi-
`fied and is shown in Fig. 8. The gate-signal timing during
`the write Vt period along with the 0-V data line voltage per-
`forms the same function that T2 and SW input did for the
`circuit in Fig. 5(a). The required operating signal voltage
`amplitudes are shown as a function of circuit properties.
`This notation allows for signal and power dissipation optimi-
`
`FIGURE 8 — Signal timing for Figs. 5(b), 9, and 13.
`
`FIGURE 10 — Luminance for standard voltage follower circuit
`(diamonds); Fig. 5(b) (squares), Fig. 9(a) (triangles), and Fig. 9(b) (×).
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`FIGURE 11 — Percent luminance loss due to 2-V Vtincrease for standard
`voltage follower (diamond); Fig. 5(b) (squares), Fig. 9(a) (triangles), and
`Fig. 9(b) (×).
`
`zation. The SW signal timing shown in Fig. 8 is for use with
`the circuits in Figs. 9 and 13.
`The circuits in Fig. 5, to a first order, do correct for Vt
`variations from one pixel circuit to another. However, as
`data is written onto the storage capacitor Cs, T3 conducts,
`charging up node B and reducing the voltage across Cs. The
`previously written Vt is also effectively reduced, thereby
`lowering the amount of Vt compensation. The circuits
`shown in Fig. 9 with the signal timing in Fig. 8 inhibit cur-
`rent flow through T3 during the write data period. The SW
`signal input is switched low during the write data period. In
`Fig. 9(a), T4 is off, which isolates the data from T3’s gate. At
`the expose period, the SW signal is set high turning T4 on and
`connecting Cs to the gate of T3. Since, for luminance, the
`voltage on the positive Cs terminal, node A, is greater then
`the voltage at the gate of T4, node C, some portion of the
`charge on Cs will be redistributed onto node C. This capaci-
`tance divider action also effectively reduces the previously
`
`FIGURE 12 — Percent luminance loss for a 1 V (diamonds), 2 V
`(squares), and 5 V (triangles) Vt increase for the Fig. 9(b) circuit.
`
`FIGURE 13 — Circuit with a top- and bottom-gate TFT.
`
`written Vt, reducing the amount of Vt compensation. In Fig.
`9(b), T4 is off, not allowing current to flow through T3 dur-
`ing the write data period. Since T4 is connected in series
`with T3 to provide current to the OLED, T4’s drain-to-
`source voltage must be added to the magnitude of Vca. The
`additional voltage increases the power dissipation.
`
`Results
`4
`With nearly identical conditions, the circuits in Figs. 5(b),
`9(a), and 9(b) have somewhat different transfer functions or
`input-to-output functions, where the input is the Vdata volt-
`age and the output is the OLED luminance. The ideal trans-
`2 and be Vt
`fer function would be proportional to Vdata
`independent. Results of transient simulation depicting the
`transfer functions of these circuits are shown in Fig. 10. The
`transfer function of a standard voltage follower circuit simi-
`lar to that shown in Fig. 5(b), which does not incorporate the
`signal timing in Fig. 8 and where Vca is fixed at –4.5 V and
`T3’s drain is connected to +13.5 V, is shown for comparison.
`The capacitance of Cs is 0.5 pF. A model for a small-mole-
`cule low-off-current OLED having a ~4-cd/A efficiency is
`used. The OLED forward voltage at 500 cd/m2 is ~7 V, the
`OLED capacitance is ~6 pf, and the TFT mobility is 0.7
`cm2/V-sec. The channel length for all TFTs is 8 µm. The
`channel width of T1 and T3 for all circuits is 48 and 64 µm,
`respectively. The channel width for T4 in Fig. 9(b) is 48 µm.
`A low off luminance level with Vdata = 0 is obtained by using
`the gate line, SW, and Vca voltage levels as shown in Fig. 6,
`and transistor widths mentioned above, to balance the
`charge pulled out of the Cs as the gate line is switched low
`when data is written with charge put into Cs as T4 is turned
`on and Vca is set to low at the beginning of the expose
`period. In order to obtain a low luminance level of <0.3
`cd/m2 with Vdata = 0, the width of T4 in Fig. 9(a) was set to
`4 µm. The write Vt period is 0.5 msec with the write data
`period splitting the remaining frame time with the expose
`period.
`The relatively low luminance output with data voltage
`for the standard voltage follower (diamond data points)
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`resulted from lower data voltage on Cs since the OLED
`voltage is current dependent. The standard voltage follower
`results shown here are equilibrated; that is, with the same
`Vdata for five repeated frame times. The output luminance
`of the circuit shown in Fig. 9(a) (triangle data points) is less
`than that of the circuits shown in Figs. 5(b) and 9(b), as a
`result of the circuit charge redistribution discussed earlier.
`The luminance of the circuit in Fig. 9(b) (X data points) is
`slightly higher than that of the circuit in Fig. 5(b) (square
`data points) due to the elimination of T3 conduction during
`the write data period.
`Rather than repeat Fig. 10, which shows luminance
`versus Vt, it is more useful to present the percent loss in
`luminance with an increase in Vt. The plot in Fig. 11 shows
`the percent luminance loss resulting from a +2 V increase in
`Vt over a 0–10-V data voltage range for the standard voltage
`follower circuit (diamond data points), the circuit in
`Fig. 5(b) (square data points), the circuit in Fig. 9(a) (trian-
`gle data points), and the circuit in Fig. 9(b) (X data points).
`As expected, the luminance loss for the standard voltage fol-
`lower circuit is the largest, having ~100% at Vdata = 2 V and
`40% at Vdata = 10 V. The circuit in Fig. 5(b) reduced the
`luminance loss to ~25% at Vdata = 2 V and to ~20% for Vdata
`= 10 V. For the circuit shown in Fig. 9(a), the luminance loss
`is ~5% at Vdata = 10 V. The circuit in Fig. 9(b) gave the
`lowest luminance loss; ~10% for Vdata = 2 V and ~2.3% for
`Vdata = 10 V, respectively.
`Shown in Fig. 12 is the percent luminance loss over a
`0–10-V data voltage range for a 1, 2, and 5 V Vt increase for
`the circuit shown in Fig. 9(b). Even with a 5-V Vt increase,
`the luminance loss is <30% for Vdata = 2 V and <6% for Vdata
`= 10 V.
`There are several sources of error that explain the
`luminance loss for these Vt-compensated circuits. First,
`during the write Vt period, the differences in Vt are stored
`to within 10 mV for 2-V Vt difference. Second, signal switch-
`ing at the end of the write Vt period and during the write
`data period reduces the stored Vt difference by about
`15 mV. For the circuit shown in Fig. 5(b), there is an error
`of 800 mV in the stored Vt difference due to conduction
`when data is written. Third, for the circuit shown in Fig. 9,
`most of the loss occurs when Vca is set to –18 V at the begin-
`ning of the expose period. Since T3’s Vt is established on the
`OLED capacitance, there is an increased voltage swing
`across the OLED as the OLED turns on with Vt. The volt-
`age swing pulls charge out of the positive terminal of Cs
`through the Cgs and Cgd capacitance of T1 and T3, respec-
`tively. Differences in Vt established on the OLED at the end
`of the write Vt period will induce a voltage difference on Cs.
`The stored Vt difference is reduced by another 75 mV for
`2-V difference in Vt. This error can only be reduced by
`increasing Cs, reducing the Cgs and Cgd capacitance and
`OLED current. Reducing the OLED current allows for the
`reduction of TFT widths, voltages, time-related voltage
`stress, and the amount of Vt variation.
`
`FIGURE 14 — Structure of top- and bottom-gate TFT.
`
`Additional improvements
`5
`5.1 Device merging
`The circuit shown in Fig. 13 is a lower-power alternative to
`the circuit shown in Fig. 9(b). TFT T3 is shown as having a
`top and bottom gate26. T3 is a functional merging of T3 and
`T4 in Fig. 9(b). The structure of the top-and bottom-gate
`TFT is shown in Fig. 14. With the exception of the top gate,
`the structure or device is that of a standard bottom-gate
`TFT. The bottom gate operates as an accumulation gate.
`The top gate is formed or etched at the same time as drain
`and source is formed without additional fabrication steps.
`Since the top gate does not overlap the drain and source
`contacts, it can only deplete or pinch off the channel. The
`top gate stops conduction through the TFT during the write
`Vt and write data periods. The width of the top gate and
`spaces to the drain and source metal can be minimum proc-
`ess feature dimensions, thus enabling the same bottom-gate
`channel length dimension as that in single-gate TFT imple-
`mentation. The SW input switching has less effect on the Cs
`voltage than the circuit shown in Fig. 9(b). Due to extra gate
`dielectric and narrow length, the top-gate to bottom-gate
`capacitance is approximately 10× less than the conventional
`bottom-gate Cgd or the bottom gate Cgs. The top-gate Cgs
`and the top-gate Cgd capacitance are also ~10× smaller in
`comparison to that of the bottom gate. While characteristics
`are highly process dependent, the Vt-compensation per-
`formance is expected to be similar to that of the circuit
`shown in Fig. 9(b).
`
`Simpler and faster operation
`5.2
`The a-Si circuits shown in Figs. 5, 9, and 13 use multilevel
`cathode voltage switching, and these circuits take 0.5 msec
`to write the Vt on the data-storage capacitor. The multilevel
`cathode voltage switching can be eliminated, a faster write
`Vt time and lower cost are obtained with a somewhat more
`complex pixel circuit. The circuit is shown in Fig. 15 and the
`associated timing diagram is shown in Fig. 16. An additional
`TFT T5, an additional voltage input Va, and input signal RS
`are incorporated to quickly reverse the voltage across the
`OLED without changing the OLED cathode voltage, Vca.
`At the beginning of the writeV t period, the RS and gate line
`input signals are switched high with 0 V on the data line.
`This reverse biases the OLED to –8 V. In one step, the cir-
`cuit is set up for setting Vt on the storage capacitor. Since
`the Vca terminal voltage is not set low during the beginning
`
`Journal of the SID 12/1, 2004
`
`71
`
`SAMSUNG, EXH. 1026, P. 7
`
`

`

`FIGURE 15 — Faster and simpler operation.
`
`of the expose period, a voltage larger than Vt is needed on
`the storage capacitor prior to writing data to offset the
`charge pulled out of the storage capacitor when the gate line
`voltage is switched low when writing data. In setting the
`capacitor voltage prior to writing data, the capacitor voltage
`needs to be Vt plus the gate line turnoff offset; typically 1 V.
`This voltage can be set much faster than with the other a-Si
`circuits; ~150 µsec as compared to 0.5 msec. The OLED
`cathode is a high-capacitance connection. There is some
`power supply and driver cost associated with multi-level
`cathode voltage switching. In Fig. 15, Vca and Va are fixed
`voltages. The capacitance of the RS signal is much lower
`than that of the OLED cathode and is easier to drive.
`One potential drawback of this circuit and driving
`method is that the gate-to-drain and drain-to-source termi-
`nal voltage of T3 do not alternate polarity. The circuit, how-
`ever, does allow for the possibility of alternating the
`gate-to-drain voltages with the use of high data voltages with
`a time allocated period.
`
`System integration
`6
`In Fig. 5(b), it is assumed that all the row driver outputs can
`be set high simultaneously during the write Vt period. Clock
`rates for high-voltage gate drivers can be less than 1 MHz.
`For such drivers, it could take more than 1 msec to switch
`all the rows to high. However, a number of gate drivers have
`output gates to simultaneously switch the outputs to high for
`testing purposes. In other cases, the shift registers used for
`row selection can be made transparent so that a high row
`selection state can very quickly propagate though to all row
`latches without clocking. Otherwise, a TFT, T2 in Fig. 5(a),
`can be used. The drawback is that T2 adds additional stray
`capacitance to node A which impacts the Vt-compensation
`performance.
`Another possible system integration issue is that the
`data is written to display in about half the frame time. This
`requires that the data bandwidth from the frame buffer and
`data driver speed be twice as fast as in typical dis