1111111111111111 IIIIII IIIII 11111 1111111111 111111111111111 111111111111111 IIIIII IIII 11111111
`US 20060170629Al
`
`c19) United States
`c12) Patent Application Publication
`Baek
`
`c10) Pub. No.: US 2006/0170629 Al
`Aug. 3, 2006
`(43) Pub. Date:
`
`(54) DISPLAY DRIVER CIRCUIT, CURRENT
`SAMPLEillOLD CIRCUIT AND DISPLAY
`DRIVING METHOD USING THE DISPLAY
`DRIVER CIRCUIT
`
`(75)
`
`Inventor: Jong-Hak Baek, Yongin-si (KR)
`
`Correspondence Address:
`HARNESS, DICKEY & PIERCE, P.L.C.
`P.O. BOX 8910
`RESTON, VA 20195 (US)
`
`(73) Assignee: Samsung Electronics Co., LTD
`
`(21) Appl. No.:
`
`11/340,705
`
`(22) Filed:
`
`Jan.27, 2006
`
`(30)
`
`Foreign Application Priority Data
`
`Jan. 31, 2005
`
`(KR) ......................................... 2005-8629
`
`Publication Classification
`
`(51)
`
`Int. Cl.
`G09G 3/30
`(2006.01)
`(52) U.S. Cl. ................................................................ 345/76
`
`(57)
`
`ABSTRACT
`
`A display driver circuit may include, a shift register config(cid:173)
`ured to shift a first clock signal to generate at least one
`second clock signal, a digital-to-analog conversion unit
`configured to convert digital gray-scale data to an analog
`gray-scale signal, a first sample/hold output circuit config(cid:173)
`ured to sample/hold the analog gray-scale signal in response
`to the at least one second clock signal, and configured to
`provide the sampled/hold analog gray-scale signal to a
`plurality of first channels in response to a first latch enable
`signal, and a second sample/hold output circuit configured to
`sample/hold the analog gray-scale signal in response to the
`second clock signal, and configured to provide the sample/
`hold analog gray-scale signal to a plurality of second chan(cid:173)
`nels in response to a second latch enable signal.
`
`SHL
`
`SHR
`
`Q-CHANNEL Bl-DIRECTIONAL S/R
`
`10
`
`CLK
`
`DATA
`
`DATA
`INTERFACE
`
`BIAS
`CIRCUIT
`
`R CURRENT
`DAG
`
`G CURRENT
`DAG
`
`334
`
`B CURRENT
`DAC
`
`350
`
`PRE CHARGE
`Cl RCUIT
`
`LE2
`LE1
`
`336
`t - - - - - - - - - - - - -+ - -1 :-----7
`t
`I
`_! M+ 1 ! 360
`! N !
`! OUT !" • ! OUT !
`- - - - - - - - - - - - - - - - - - - - - -< I
`I
`I
`I
`L ___ J
`L ___ J
`
`C_PRE
`
`CURRENT S/H
`OUTPUT I
`
`r-----,
`I
`I
`I
`I
`I
`I
`
`I
`I
`I
`
`I
`I
`I
`
`: OUT l ... : OUT i
`! M \
`\ 1 !
`I
`I
`I
`I
`L ___ J
`L ___ J
`
`CURRENT S/H
`OUTPUT II
`
`370
`
`I
`I
`
`I
`I
`
`370-(M+1)
`370-N
`OUTPUT[ N : M+ 1 ]
`
`360-1
`360-M
`OUTPUT [ M : 1]
`
`SAMSUNG, EXH. 1005, P. 1
`
`

`

`FIG. 1
`(PRIOR ART)
`100
`SHL
`
`SHR
`
`Q-CHANNEL Bl-DIRECTIONAL
`SHIFT REGISTER
`
`I I . . . I 1 I
`
`DATA LATCH CIRCUIT
`
`1 - - - - - - - - , - - i I
`
`I
`
`I
`
`I
`
`L _______ .J L _______ .J
`
`•
`
`•
`
`r-------7 r-------,
`, . 1
`, , 2
`,
`I CHNNEL I I CHNNEL !
`l DAC
`l l DAC
`l
`i~~J~;~l i~~i~;~l
`
`I
`
`·
`
`I
`
`I
`
`I
`
`l OUTPUT I I OUTPUT l
`I OUTPUT I l OUTPUT l
`OUTPUT
`CIRCUIT
`
`I
`
`I
`
`I
`
`r-------, r-------,
`, N-1
`, , N
`,
`! CHNNEL ! I CHNNEL !
`I
`l DAC
`l l DAC
`~
`• L-------.J L _______ .J
`!~~~J;~l !~~~~;~1
`
`I
`
`I
`
`I
`
`I
`
`L ______ .J L ______ .J
`
`L ______ .J L ______ .J
`
`OUT1
`
`OUT2
`
`OUTN-1
`
`OUTN
`
`CLK
`
`DATA
`
`LE
`
`DATA
`I NTE~ACE
`
`120
`
`REFERENCE
`B I As
`CI RCU IT
`
`)
`
`140
`
`""O
`~ .....
`('D = .....
`
`(')
`
`~ .....
`
`t "e -....
`.... 0 =
`""O = O" -....
`.... 0 =
`~
`~
`~
`N
`0
`0
`O'I
`
`(')
`
`~ .....
`
`~
`
`('D
`('D
`
`rJJ =(cid:173)
`.....
`....
`0 ....
`
`Ul
`
`c
`rJJ
`N
`0
`0
`~
`0 ....
`
`-....J
`0
`O'I
`N
`1,0
`
`> ....
`
`-110
`
`-130
`
`-150
`-152
`
`-154
`
`SAMSUNG, EXH. 1005, P. 2
`
`

`

`Patent Application Publication Aug. 3, 2006 Sheet 2 of 5
`
`US 2006/0170629 Al
`
`'1
`
`I
`
`FIG. 2
`(PRIOR ART)
`
`CLK
`
`I
`I
`I
`
`I n__
`
`I
`
`n
`I [L
`~
`
`N
`
`I
`I
`I
`I
`
`SHR J7
`
`or
`SHL
`
`SHL
`or
`SHR
`
`LE
`
`DATA
`
`2
`
`3
`
`OUT1
`
`OUT2
`
`OUT N-1
`
`OUT N
`
`SAMSUNG, EXH. 1005, P. 3
`
`

`

`FIG. 3
`
`SHL
`
`SHR
`
`CLK
`
`Q-CHANNEL Bl-DIRECTIONAL S/R
`
`r----.--;.
`
`10
`
`r------------------✓330
`
`IT\
`....__,.,:;__ _ _ - - - - , - - - - - ,
`
`
`
`.-----t-_,1"1._........,_ ( _ _ _ _ --,
`
`l
`
`. . . . - - - - - - tT \~ -C PF
`j
`E
`I
`-
`l
`
`DATA - - -R CURRENT t------7: _ _
`DATA
`DAC ~
`,.../ INTERFACE
`3
`20
`.
`1 332
`I
`!
`l ___ D_Ac_~334
`
`I
`
`I
`
`3
`40'-"""" C IBRltusl T ,-- : G CURRENT
`
`I
`I
`I
`
`: B CURRENT t - - t - -~
`i
`DAC
`: ______ , i'--336
`I"-!
`L-----, ____________ J
`
`so~
`
`PRECHARGE
`c I RCU I T
`
`LE2
`LE1
`
`:
`:
`:
`:
`: M+1 :
`: N :
`: OUT :· • ·: OUT I
`- - - - - - - - - - - - - - - - - - - - i : :
`:
`:
`I
`I
`I
`I
`~-)--~
`
`CURRENT S/H
`OUTPUT II
`
`--., 370
`
`CURRENT S/H
`OUTPUT I
`
`r - - - '~~ - - - - ,
`,
`
`,------,
`
`,------,
`
`I
`
`I
`
`I
`
`I
`
`360___...-
`
`~-,--~
`1
`'
`(
`t 370-( M+1)
`370-N
`OUTPUT[N:M+1]
`
`,------,
`
`,------,
`
`I
`
`I
`
`I
`
`I
`
`: : -
`:
`:
`: OUT : ••• : OUT :
`: M I
`I 1 :
`:
`:
`:
`:
`I
`I
`I
`I
`~-)--~
`
`~-,--~
`
`_II
`
`(
`)
`360-1
`360-M
`OUTPUT[M:1]
`
`""O
`~ .....
`('D = .....
`
`(')
`
`~ .....
`
`(')
`
`~ .....
`
`t "e -....
`.... 0 =
`""O = O" -....
`.... 0 =
`~
`~
`~
`N
`0
`0
`O'I
`
`~
`
`('D
`('D
`
`~
`
`rJ'1 =(cid:173)
`.....
`0 ....
`
`Ul
`
`c
`rJ'1
`N
`0
`0
`
`O'I ---0 ....
`
`--.J
`0
`O'I
`N
`1,0
`
`> ....
`
`SAMSUNG, EXH. 1005, P. 4
`
`

`

`Patent Application Publication Aug. 3, 2006 Sheet 4 of 5
`
`US 2006/0170629 Al
`
`·· ·
`
`FIG. 4
`
`CLK
`
`SHR
`or
`SHL
`
`SHL
`or
`SHR
`
`I
`I
`I
`I
`
`._____~------+-----'IL .
`______ n~-
`C_PRE 1'-------+----------i---'n...___ _
`LE1 _ _ ___.m.____ _ _
`
`LE2
`
`DATA
`
`2
`
`3
`
`OUT1
`
`OUTM
`
`OUTM+1
`
`OUTN
`
`I
`I
`I
`I
`
`I
`I
`
`I I •
`
`T2
`
`.
`
`SAMSUNG, EXH. 1005, P. 5
`
`

`

`Patent Application Publication Aug. 3, 2006 Sheet 5 of 5
`
`US 2006/0170629 Al
`
`::z
`0 w
`c::
`
`1~
`
`UJ er:
`c...
`>
`
`C'\J._.,.:..
`w 0 w
`
`_J
`
`_J
`
`,.......,
`~
`I-
`::,
`0
`
`('I')
`if)
`
`C'\J
`::iE
`
`LO
`
`C'\J
`~~~ if)
`.------------1 I I
`c : :o~ v------.--.
`LL
`---'--+-....._
`
`0
`I.{)
`C'0
`
`SAMSUNG, EXH. 1005, P. 6
`
`

`

`US 2006/0170629 Al
`
`Aug. 3, 2006
`
`1
`
`DISPLAY DRIVER CIRCUIT, CURRENT
`SAMPLEillOLD CIRCUIT AND DISPLAY DRIVING
`METHOD USING THE DISPLAY DRIVER CIRCUIT
`
`clock signal CLK to a right direction in response to a right
`input start pulse; the shift register 110 may store the shifted
`clock signal and output the shifted clock signal.
`
`CLAIM FOR PRIORITY
`
`[0001] A claim of priority is made to Korean Patent
`Application No. 2005-8629, filed on Jan. 31, 2005 in the
`Korean Intellectual Property Office, the entire contents of
`which are hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`[0002] 1. Field of the Invention
`
`[0003] Example embodiments of the present invention
`relate to a display driver circuit for a flat display panel and
`a display driving method using the same. More particularly,
`example embodiments of the present invention relate to a
`display driver circuit, a current sample/hold circuit, and a
`display driving method using the display driver circuit.
`
`[0004] 2. Description of the Related Art
`
`[0005] A liquid crystal display (LCD) and a plasma dis(cid:173)
`play panel (PDP) are the two most common type of flat panel
`displays. Recently, an organic light emitting diode (OLED)
`display, which features higher contrast and/or quicker
`response time, is a type of display that has gain increased
`attention.
`
`[0006]
`In order to implement a display driver circuit
`capable of supporting higher definition, a number of bits for
`a gray level should be increased. Accordingly, each of
`channels in the display driver circuit should process more
`data; however, the number of channels may increase as a
`size of a display panel increases.
`
`[0007] A conventional display driver circuit, which may
`include a digital-to-analog converter (DAC) corresponding
`to each one of the channels, may be limited in its function
`as the number of the gray-scale bits and the number of the
`channels increases. Therefore, a display driver circuit
`capable of supporting an increased number of gray-scale bits
`and increased number of channels may be required.
`
`[0008] FIG. 1 is a block diagram illustrating a conven(cid:173)
`tional display driver circuit 100.
`
`[0009] Referring to FIG. 1, the conventional display
`driver circuit 100 may include a shift register 110, a data
`interface circuit 120, a data latch circuit 130, a reference bias
`circuit 140, and/or an output circuit 150.
`[0010] The shift register 110 may receive a clock signal
`CLK and output a shifted clock signal. The data interface
`circuit 120 may receive and process display data. The data
`latch circuit 130 may receive output signals from the data
`interface circuit 120 in response to the shifted clock signal
`output from the shift register 110, and output the display data
`to each of a plurality of channels in response to a latch
`enable signal LE. The reference bias circuit 140 may provide
`a reference value. The output circuit 150 may receive the
`output signals from the data latch circuit 130, convert the
`received output signals to analog output signals, and output
`the analog output signals to each of the plurality of channels.
`
`In further detail, the shift register 110 may receive
`[0011]
`the clock signal CLK to shift the clock signal CLK to a left
`direction in response to a left input start pulse or shift the
`
`[0012] The data interface circuit 120 may receive and
`process the received display data corresponding to each of
`the plurality of channels, and output the processed display
`data to the data latch circuit 130.
`
`[0013] The data latch circuit 130 may sample/hold output
`signals received from the data interface circuit 120 based on
`the shifted clock signal of the shift register 110. When the
`data latch circuit 130 receives all of the output signals of the
`data interface circuit 120, the data latch circuit 130 may
`output the sampled/held output signals to each of the plu(cid:173)
`rality of channels based on the latch enable signal LE.
`
`[0014] The output circuit 150 may receive the output
`signals of the data latch circuit 130. Each of a plurality of
`digital-to-analog converters (DAC) 152 included in the
`output circuit 150 may convert the corresponding output
`signals of the data latch circuit 130 to analog output signals,
`and output the analog output signals to the plurality of a
`plurality of channels via each of channel output circuits 154
`also included in the output circuit 150.
`
`[0015] FIG. 2 is a timing diagram to explain operations of
`the display driver circuit 100 shown in FIG. 1.
`
`[0016] Referring to FIG. 2, when shift clocks CLK 1
`through CLK Q corresponding to the number of channels N
`are turned on, a latch enable signal LE is activated on and
`output signals are output to all of a plurality of channels
`OUT 1 through OUT N.
`
`[0017]
`If a size of a display panel becomes larger, the
`number of channels increases, and the number of DACs
`included in each of the channels also increases, and a chip
`size of the display driver circuit 100 also increases.
`
`[0018]
`In addition, in order to implement high definition,
`a gray level may increase; thus, the number of processing
`bits of the DAC may also increase. As a result, a chip size
`of the DAC included in each of the channels may also
`increase, and the chip size of the display driver circuit 100
`increases. If a display panel supporting a large scale panel
`and high definition is implemented using the conventional
`display driver circuit 100 shown in FIG. 1, a size of the
`display driver circuit 100 may be relatively large.
`
`SUMMARY OF EXAMPLE EMBODIMENTS OF
`THE INVENTION
`
`[0019] Example embodiments of the present invention
`may provide a display driver circuit with a smaller chip size
`capable of supporting a larger scaled and higher definition
`panel. Example embodiments of the present invention also
`may provide a display driving method capable of supporting
`a larger scaled high definition panel. Example embodiments
`of the present invention may also provide a current sample/
`hold circuit capable of performing faster sampling on an
`analog gray-scale signal, and capable of reducing a mis(cid:173)
`match between a sampling value and a holding value of the
`analog gray-scale signal.
`
`[0020]
`In an example embodiment of the present inven(cid:173)
`tion, a display driver circuit, may include a shift register
`configured to shift a first clock signal to generate at least one
`second clock signal, a digital-to-analog conversion unit
`
`SAMSUNG, EXH. 1005, P. 7
`
`

`

`US 2006/0170629 Al
`
`Aug. 3, 2006
`
`2
`
`configured to convert digital gray-scale data to an analog
`gray-scale signal, a first sample/hold output circuit config(cid:173)
`ured to sample/hold the analog gray-scale signal in response
`to the at least one second clock signal, and configured to
`provide the sampled/hold analog gray-scale signal to a
`plurality of first channels in response to a first latch enable
`signal, and a second sample/hold output circuit configured to
`sample/hold the analog gray-scale signal in response to the
`second clock signal, and configured to provide the sample/
`hold analog gray-scale signal to a plurality of second chan(cid:173)
`nels in response to a second latch enable signal.
`
`[0021]
`In an example embodiment of the present inven(cid:173)
`tion, a current sample/hold circuit, may include a sample/
`hold unit configured to receive an analog gray-scale signal
`in response to a clock signal, and adapted to output the
`analog gray-scale signal in response to at least one of a first
`latch enable signals and a second latch enable signal. The
`sample/hold unit may include a first transistor configured to
`receive the analog gray-scale signal, a first switch configured
`to control an electrical connection between a gate and a drain
`of the first transistor in response to the second clock signal,
`a second switch configured to apply the analog gray-scale
`signal to the first transistor in response to the second clock
`signal, a storage capacitor coupled to the gate of the first
`transistor and configured to charge the analog gray-scale
`signal, a second transistor configured to have a gate com(cid:173)
`monly coupled to the gate of the first transistor and a drain
`coupled to an output terminal, and a third switch configured
`to control an electrical connection between the drain of the
`second transistor and the output terminal in response to at
`least one of the first latch enable signal and the second latch
`enable signal.
`
`[0022]
`In another example embodiment of the present
`invention, a display driving method may include converting
`digital display data to an analog gray-scale signal, shifting a
`first clock signal and outputting at least one second clock
`signal, performing at least one sampling/holding operation
`on the analog gray-scale signal in response to the second
`clock signal, and, outputting the first sampled/held analog
`gray-scale signal in response to at least one of a first latch
`enable signal and a second latch enable signal.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0023] Example embodiments of the present invention
`will become more apparent with the description of the
`detailed example embodiments thereof with reference to the
`attached drawings in which:
`
`[0024] FIG. 1 is a block diagram illustrating a conven(cid:173)
`tional display driver circuit;
`
`[0025] FIG. 2 is a timing diagram to explain operations of
`the display driver circuit shown in FIG. 1;
`
`[0026] FIG. 3 is a block diagram illustrating a display
`driver circuit according to an example embodiment of the
`present invention;
`
`[0027] FIG. 4 is an example timing diagram to explain
`operations of the display driver circuit shown in FIG. 3; and
`
`[0028] FIG. 5 is a circuit diagram illustrating a current
`sample/hold circuit according to an example embodiment of
`the present invention.
`
`DESCRIPTION OF EXAMPLE EMBODIMENTS
`OF THE PRESENTION INVENTION
`
`[0029] Detailed illustrative example embodiments of the
`present invention are disclosed herein. However, specific
`structural and functional details disclosed herein are merely
`representative for purposes of describing example embodi(cid:173)
`ments of the present invention. This invention may, how(cid:173)
`ever, be embodied in many alternate forms and should not be
`construed as limited to the example embodiments set forth
`herein.
`
`[0030] Accordingly, while the invention may be suscep(cid:173)
`tible to various modifications and alternative forms, specific
`embodiments thereof are shown by way of example in the
`drawings and will herein be described in detail. It should be
`understood, however, that there is no intent to limit the
`invention to the particular forms disclosed, but on the
`contrary, the invention is to cover all modifications, equiva(cid:173)
`lents, and alternatives falling within the spirit and scope of
`the invention. Like numbers refer to like elements through(cid:173)
`out the description of the figures.
`
`[0031]
`It will be understood that, although the terms first,
`second, etc. may be used herein to describe various ele(cid:173)
`ments, these elements should not be limited by these terms.
`These terms are only used to distinguish one element from
`another. For example, a first element could be termed a
`second element, and, similarly, a second element could be
`termed a first element, without departing from the scope of
`the present invention. As used herein, the term "and/or"
`includes any and all combinations of one or more of the
`associated listed items.
`
`[0032]
`It will be understood that when an element is
`referred to as being "connected" or "coupled" to another
`element, it can be directly connected or coupled to the other
`element or intervening elements may be present. In contrast,
`when an element is referred to as being "directly connected"
`or "directly coupled" to another element, there are no
`intervening elements present. Other words used to describe
`the relationship between elements should be interpreted in a
`like fashion (i.e., "between" versus "directly between",
`"adjacent" versus "directly adjacent", etc.).
`
`[0033] The terminology used herein is for the purpose of
`describing particular embodiments only and is not intended
`to be limiting of the invention. As used herein, the singular
`forms "a", "an" and "the" are intended to include the plural
`forms as well, unless the context clearly indicates otherwise.
`It will be further understood that the terms "comprises",
`"comprising", "includes" and/or "including", when used
`herein, specify the presence of stated features, integers,
`steps, operations, elements, and/or components, but do not
`preclude the presence or addition of one or more other
`features, integers, steps, operations, elements, components,
`and/or groups thereof.
`
`[0034] Unless otherwise defined, all terms (including tech(cid:173)
`nical and scientific terms) used herein have the same mean(cid:173)
`ing as commonly understood by one of ordinary skill in the
`art to which this invention belongs. It will be further
`understood that terms, such as those defined in commonly
`used dictionaries, should be interpreted as having a meaning
`that is consistent with their meaning in the context of the
`relevant art and will not be interpreted in an idealized or
`overly formal sense unless expressly so defined herein.
`
`SAMSUNG, EXH. 1005, P. 8
`
`

`

`US 2006/0170629 Al
`
`Aug. 3, 2006
`
`3
`
`[0035] FIG. 3 is a block diagram illustrating a display
`driver circuit according to an example embodiment of the
`present invention, and FIG. 4 is a timing diagram to explain
`operations of the display driver circuit shown in FIG. 3.
`
`output circuit 360 may sample/hold the analog gray-scale
`current from the channels 1 through M based on the output
`signal ( or the second clock signal) of the bidirectional shift
`register 310.
`
`[0036] Referring to FIGS. 3 and 4, a display driver circuit
`may include a bidirectional shift register 310, a data inter(cid:173)
`face circuit 320, a current digital-to-analog conversion unit
`330, a bias circuit 340, a pre-charge circuit 350, a first
`current sample/hold output circuit 360, and/or a second
`current sample/hold output circuit 370.
`
`[0037] The current digital-to-analog conversion unit 330
`may include a red current digital-to-analog converter
`(DAC), a green current DAC, and a blue current DAC.
`
`[0038] The first sample/hold output circuit 360 may
`include current sample/hold circuits 360-1 through 360-M,
`each corresponding channels 1 through M.
`
`[0039] The second sample/hold output circuit 370 may
`include current sample/hold circuits 370-(M + 1) through
`370-N, each corresponding to channels M+l through N.
`
`[0040] The bidirectional shift register 310 may shift a first
`clock signal CLK received from an external device to
`sequentially output second clock signals. For example, the
`bidirectional shift register 310 may shift the first clock signal
`CLK from a left direction to a right direction in response to
`a left input start pulse SHL or may shift the first clock signal
`CLK from a right direction to a left direction in response to
`a right input start pulse SHR.
`
`[0041] Output signals of the bidirectional shift register
`310, for example, the second clock signals may be used as
`control signals of corresponding current sample/hold cir(cid:173)
`cuits 360-1 through 370-N.
`
`[0042] The data interface circuit 320 may interface
`between a main chip (not shown) and the current digital-to(cid:173)
`analog conversion unit 330. The current digital-to-analog
`conversion unit 330 may process digital display data DATA
`received from the main chip (not shown). For example, if the
`digital display data DATA is composed of 18 bits, the data
`interface circuit 320 may output digital gray-scale data
`composed of 6 bits to each of the red current DAC, green
`current DAC, and blue current DAC, respectively.
`
`[0043] The current digital-to-analog conversion unit 330
`according to an example embodiment of the present inven(cid:173)
`tion may be indirectly coupled to each of the channel output
`via the first/second current sample/hold output circuits 360
`and 370. In addition, the current digital-to-analog conver(cid:173)
`sion unit 330 may be composed of just three current DA Cs,
`instead of a number of DACs corresponding to the number
`of channels.
`
`[0044] The bias circuit 340 may generate a gamma refer(cid:173)
`ence signal to provide a gamma reference signal to the
`current digital-to-analog conversion unit 330. The current
`digital-to-analog conversion unit 330 may convert gray(cid:173)
`scale data provided from the data interface circuit 320 to an
`analog gray-scale current based on the gamma reference
`signal.
`
`[0046] When a first latch enable signal LEl is activated,
`the sampled/held analog gray-scale current from the chan(cid:173)
`nels 1 through M may be output. For example, M may be
`N/2.
`
`[0047] The second current sample/hold output circuit 370
`may sample/hold the analog gray-scale current from the
`channels M+l through N based on the output signal of the
`bidirectional shift register 310.
`
`[0048] While the first current sample/hold output circuit
`360 outputs the analog gray-scale current during a first time
`period Tl, the second current sample/hold output circuit 370
`may sample/hold the analog gray-scale current correspond(cid:173)
`ing to the channels M+l through N.
`
`[0049] When the second latch enable signal LE2 is acti(cid:173)
`vated, the second current sample/hold output circuit 370
`may output output signals OUT M+l through OUT N to the
`channels M+l through N during a second time period T2.
`
`[0050] While the second current sample/hold output cir(cid:173)
`cuit 370 outputs the analog gray-scale current during the
`second time period T2, the first current sample/hold output
`circuit 360 may sample/hold the analog gray-scale current
`corresponding to the channels 1 through M. For example,
`when M is equal to N/2, the first time period Tl and the
`second time period T2 may be a ½ line time (½H). A 1 line
`time (lH) may denote a time period of a one line scanning
`interval.
`
`[0051] Referring to FIG. 4, when the first latch enable
`signal LEl is activated, the output signals OUTPUT 1
`through OUTPUT M may be activated to be output to the
`channels 1 through M.
`
`[0052] When the second latch enable signal LE2 is acti(cid:173)
`vated, the output signals OUTPUT M+l through OUTPUT
`N may be activated to be output to the channels M + 1
`through N. While the output signals OUTPUT M+l through
`OUTPUT N of the second current sample/hold output circuit
`370 are activated, the output signals OUTPUT 1 through
`OUTPUT M of the first current sample/hold output circuit
`360 may be inactivated. In other words, the output process
`of the first current sample/hold output circuit 360 and the
`second current sample/hold output circuit 370 may be alter(cid:173)
`nately performed.
`
`[0053] FIG. 5 is a circuit diagram illustrating a current
`sample/hold circuit according to an example embodiment of
`the present invention.
`
`[0054] Hereinafter, operations of a current sample/hold
`circuit 370-k, which may correspond to a kth channel, will
`be described below.
`
`[0055] Referring to FIG. 5, the current sample/hold circuit
`370-k may include a first transistor Ml, a second transistor
`M2, a third transistor M3, a first switch Sl through a fourth
`switch S4, and a storage capacitor CST.
`
`[0045] The first current sample/hold output circuit 360
`may sample/hold the analog gray-scale current and may
`output output signals OUTPUT 1 through OUTPUT M to
`the channels 1 through M. The first current sample/hold
`
`[0056] When a second clock signal SR CLK, which may
`be an output signal of a bidirectional shift register 310
`shown in FIG. 3, is activated, the first switch Sl and the
`second switch S2 may be turned on. As a result, an analog
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`gray-scale current output from a current digital-to-analog
`conversion unit 330 may be applied to a drain of the first
`transistor Ml via the second switch S2. At this time, because
`the first switch Sl is also turned on, the analog gray-scale
`current applied to the drain of the first transistor Ml may be
`applied to a gate of the first transistor Ml. The storage
`capacitor CST, which may be coupled to the gate of the first
`transistor Ml, charges the analog gray-scale current.
`[0057] When a second clock signal SR CLK is inactivated,
`the first switch Sl and the second switch S2 may be turned
`off; thus, the analog gray-scale current corresponding to the
`analog gray-scale current may be held in the storage capaci(cid:173)
`tor CST.
`
`[0058] When the first latch enable signal LEl or the
`second latch enable signal LE2 is activated, a third switch S3
`may couple a drain of the second transistor M2 to an output
`terminal OUT[K], and the second transistor M2, which may
`have its gate coupled to the storage capacitor CST, may
`output the analog gray-scale current to the output terminal
`OUT[K] based on the charged analog gray-scale current.
`
`[0059] An analog gray-scale current used for representing
`a gray level, which may correspond to a minimum size DAC
`unit, may be about several tens of nA, therefore, may require
`a relative long charge time to charge the storage capacitor
`CST.
`
`[0060]
`In order to reduce the charge time, a current, N
`times higher than a minimum output current of the current
`DAC, may be supplied to the first transistor Ml.
`
`[0061]
`In order to output desired output signals at the
`output terminal OUT[K], the first transistor Ml and the
`second transistor M2 may have a size ratio of N: 1 using a
`current mirror configuration.
`
`[0062] To further reduce a charge time, a fourth switch S4
`may be turned on to pre-charge a voltage of the storage
`capacitor CST to a voltage level slightly lower than a
`threshold voltage of the first transistor Ml in response to the
`capacitor pre-charge signal C_PRE before the first switch Sl
`and the second switch S2 are turned on.
`
`[0063] The output terminal OUT[K] may be used to drive
`a display panel (not shown) using a smaller current. The
`output terminal OUT[K] may be pre-charged, which may be
`implemented using the third transistor M3, to quickly pro(cid:173)
`vide display data to a display panel (not shown). In other
`words, the third transistor M3 may be turned on to pre(cid:173)
`charge the output terminal OUT[K] with a pre-charge volt(cid:173)
`age VPRE in response to an output pre-charge signal
`PREON before the output signals are applied to the output
`terminal OUT[K].
`
`[0064] The display driver circuit according to example
`embodiments of the present invention may be applicable to
`Organic Light Emitting Diode (OLED) display devices, for
`example, current-driven active matrix type OLED display
`devices.
`
`may be substituted for a digital-to-analog conversion unit
`330 shown in FIG. 3, and an output buffer may be substi(cid:173)
`tuted for first and second sample/hold output circuits 360
`and 370.
`
`[0066] As described above, a display driver circuit and a
`display driving method may divide output terminals into two
`blocks and couple a current digital-to-analog conversion unit
`to an output terminal of an data interface circuit; therefore,
`an increase of chip area, due to an increase of number of
`channels and high definition requirements, may be reduced.
`In addition, the current sample/hold circuit may perform a
`sampling operation faster, and may more accurately output
`output signals to corresponding channels.
`
`[0067] While example embodiments of the present inven(cid:173)
`tion and aspects thereof have been described in detail, it
`should be understood that various changes, substitutions and
`alterations may be made herein without departing from the
`scope of the example embodiments of the present invention.
`
`What is claimed is:
`1. A display driver circuit, comprising:
`
`a shift register configured to shift a first clock signal to
`generate at least one second clock signal;
`
`a digital-to-analog conversion unit configured to convert
`digital gray-scale data to an analog gray-scale signal;
`
`a first sample/hold output circuit configured to sample/
`hold the analog gray-scale signal in response to the at
`least one second clock signal, and configured to pro(cid:173)
`vide the sampled/hold analog gray-scale signal to a
`plurality of first channels in response to a first latch
`enable signal; and
`
`a second sample/hold output circuit configured to sample/
`hold the analog gray-scale signal in response to the at
`least one second clock signal, and configured to pro(cid:173)
`vide the sample/hold analog gray-scale signal to a
`plurality of second channels in response to a second
`latch enable signal.
`2. The display driver circuit of claim 1, further including
`a bias circuit configured to generate a gamma reference
`signal, wherein the digital-to-analog conversion unit con(cid:173)
`verts the digital gray-scale data to the analog gray-scale
`signal based on the gamma reference signal.
`3. The display driver circuit of claim 2, wherein the
`digital-to-analog conversion unit includes:
`
`a first digital-to-analog converter (DAC) configured to
`convert a digital red gray-scale data to a first analog
`gray-scale signal based on the gamma reference signal;
`
`a second digital-to-analog converter (DAC) configured to
`convert a digital green gray-scale data to a second
`analog gray-scale signal based on the gamma reference
`signal; and
`
`[0065] Additionally, a panel driven method, for example,
`output terminals shown in FIG. 3, which may be divided
`into two blocks, may be applicable to active matrix type
`liquid crystal display devices. For example, when output
`terminals shown in FIG. 3 are applicable to voltage-driven
`active matrix type liquid crystal display devices instead of
`current-driven devices, a digital-to-analog converter (DAC)
`
`a third digital-to-analog converter (DAC) configured to
`convert a digital blue gray-scale data to a third analog
`gray-scale signal based on the gamma reference signal.
`4. The display driver circuit of claim 1, wherein the shift
`register includes a bidirectional shift register configured to
`shift the first clock signal to a first direction in response to
`a first input start pulse and shift the first clock signal to a
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`second direction in response to a second input start pulse,
`and sequentially generate the at least one second clock
`signal.
`5. The display driver circuit of claim 4, wherein the
`bidirectional shift register includes a multiple channel bidi(cid:173)
`rectional shift register configured to output the at least one
`second clock signal so as to simultaneously control the
`plurality of first and second channels.
`6. The display driver circuit of claim 1, wherein the
`second sa