Introduction to Digital Electronics
`INTRODUCTION TO
`DIGITAL ELECTRONICS
`
`John Crowe and Barrie Hayes-Gill
`
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`Introduction to Digital
`Electronics
`
`John Crowe and Barrie Hayes-Gill
`Both Lecturers in the
`Department of Electrical and Electronic Engineering
`University of Nottingham
`
`Nownes
`
`OXFORD AMSTERDAM BOSTON LONDON NEW YORK PARIS
`SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO
`
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`Newnes
`An imprint of Elsevier Science
`Linacre House, Jordan Hill, Oxford OX2 8DP
`200 Wheeler Road, Burlington, MA 01803
`
`First published by Arnold 1998
`Reprinted 2001, 2002, 2003
`
`Copyright (cid:14)9 1998, John Crowe and Barrie Hayes-Gill. All rights reserved
`
`The right of John Crowe and Barrie Hayes-Gill to be identified as the authors
`of this work has been asserted in accordance with the Copyright,
`Designs and Patents Act 1988
`
`No part of this publication may be reproduced in any material form (including
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`
`ISBN 0 340 64570 9
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`208 Choosing a means of implementation
`
`larger current to be passed within the same size transistor. In addition the higher
`the mobility, the faster the switching speed. In fact N-channel mobility is 2-3
`times that of P-channel carriers and hence the NMOS logic operates at 2-3 times
`the speed of PMOS.
`One problem of the NMOS gates (and for that matter PMOS) is that the upper
`transistor load is just acting as a resistor. When the lower transistor is on then
`current will flow from Vdd to V~ and hence these types of devices consume a
`moderate amount of power. Consequently in 1978 both PMOS and NMOS
`devices were combined on to the same chip to produce the Complementary Metal
`Oxide Semiconductor family or CMOS as it is more commonly known.
`
`9.3.3 CMOS inverter
`
`A CMOS inverter is shown in Fig. 9.11. It consists of one NMOS and one PMOS
`transistor. The PMOS device is indicated by the negation sign (i.e. a bubble) on its
`gate and has a negative threshold voltage of typically-1V. To turn on a PMOS
`device we require a voltage, VGs, more negative t h a n - 1 V. Notice that the two
`drains of the two MOS transistors are connected together and form the output
`whilst the two gates form the single input. Due to the difference in the mobilities
`of the two devices the PMOS device is made with its WIL ratio 2-3 times larger
`than the NMOS device. This results in the two transistors having the same value
`of K so that both will have the same electrical performance.
`
`i/p
`
`c
`
`Vdd
`
`f
`
`Vss
`
`Fig. 9.11 CMOS inverter
`
`The circuit operation depends upon the individual gate-source voltages. When
`the input voltage is 5 V then the NMOS VGs is 5 V and hence this device is on.
`However, the PMOS VGs is 0 V and so this device is turned off. The output voltage
`is thus pulled down to 0 V. Now with the input at 0 V the NMOS VGs is 0 V and
`hence is turned off. However, the PMOS VGs i s - 5 V and is thus turned on
`(remember a voltage more negative than the threshold voltage is needed to turn
`on a PMOS device). With the PMOS device on, the output voltage is pulled up to
`Voo. The circuit thus operates as an inverter or a NOT gate.
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`The MOSFET 209
`
`CMOS inverter power dissipation
`You should notice that when the input is steady at either a high or a low voltage
`(static condition) then one transistor is always off between V~d and V~s. Hence the
`current flowing is extremely small - equal to the leakage current of the off tran-
`sistor which is typically 100 nA. As a result of this the static power dissipation is
`extremely low and it is this reason that has made CMOS such a popular choice of
`technology.
`For input voltages between V T and Vd~- V T then the individual MOS transis-
`tors will be switched on by an amount dictated by Equations 9.1 and 9.2 and
`thus current will flow from Vd~ to V~. When the input voltage is V~J2 both
`transistors will be turned on by the same amount and hence the current will rise
`to a maximum and power will be dissipated. On many integrated circuits,
`several thousand gates exist and hence this power dissipation can be large. It is
`for this reason that the input voltage to a CMOS circuit must not be held at
`Vd,]2. When the inputs are switching the power dissipated is called dynamic
`power dissipation. However, as long as the input signals have a fast rise and fall
`time then this form of dynamic power dissipation is small. The main cause of
`dynamic power dissipation, however, in a CMOS circuit is due to the charge
`and discharge of capacitance at each gate output. The dynamic power dissipa-
`tion of a CMOS gate is therefore dependent upon the number of times a capac-
`itor is charged and discharged. Hence as the frequency of switching increases so
`the dynamic power dissipation increases. The dynamic power dissipation for a
`CMOS gate is equal to
`
`edynamic- CL X V~d x f
`
`(9.3)
`
`wherefis the switching frequency and C L is the load capacitance.
`The total power dissipated in a CMOS inverter is thus the sum of the static and
`dynamic components.
`
`Example 9.9
`
`Compare the power dissipated by a CMOS inverter driving a 50pF load at (a)
`10 kHz and (b) 10 MHz. What average current flows in each case. Assume a 5 V
`power supply.
`
`Solution
`
`(a) 10 kHz:
`
`Also:
`
`(b) 10 MHz:
`
`Pdynami~- CL • V~o •
`
`50• 10-12 •
`
`• 10• 103= 12.5 ~W
`
`Pdynamic- Vdd X [average ~
`
`]average- 12.5 • 10-6/5 - 2.5 gA
`
`Pdynamic = C L x V~,jxf= 50x 10-12 x 25 x 10• 106-12.5 mW
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`210 Choosing a means of implementation
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`Also"
`
`Example 9.10
`
`edynamir = Vdd X/average ~/average-- 12.5 x 10-3/5-- 2.5 mm
`
`Calculate the output voltage and the current los flowing between V~ and V~ when
`the input to the CMOS inverter in Fig. 9.11 is 2.5V. Assume that K N - K P-
`128 ~A V -2.
`
`Solution
`
`When the input voltage is 2.5 V then VGS N =-VGS P = 2.5 V. Hence both devices will
`be turned on by the same amount. Since K N = Kp then the output voltage will equal
`( Vd~- Vs~)/2 = 2.5 V.
`The current, IDS, is determined by using one of the two Equations 9.1 or 9.2.
`Since VDS > VGS- V s for both the NMOS and PMOS transistors then both devices
`are in saturation and Equation 9.2 is used. Thus:
`
`IDs- KN( VGs- VT)e/2 -- 128 X 10-6(2.5 - 1)2/2 = 0.144 mA
`
`CMOS inverter delay
`The delay for a CMOS inverter depends upon the rate of charge or discharge of all
`capacitors at the output. This load capacitance is due to two components called
`the inherent capacitance and the external load capacitance. The inherent capaci-
`tance is due to the drain regions of each transistor and the wiring connecting these
`two drains together. The external capacitance is due either to the input capaci-
`tance of the next stage or any parasitic off-chip capacitance. The propagation
`delay (Xp) of a CMOS inverter, and for that matter all CMOS gates, is approxi-
`mately equal to
`
`Xp - 2 CLIKVdd
`
`(9.4)
`
`Example 9.11
`
`A CMOS inverter has a total inherent drain capacitance at the output of 1 pF
`before any external load is added. What is the propagation delay for this inverter
`unloaded? Also, plot a graph of inverter propagation delay versus external load
`capacitance. Assume that K N - K e - 64 ~ V -2.
`
`Solution
`
`Before any load is added (i.e. with 1 pF inherent capacitance) the inherent propa-
`gation delay of this inverter can be calculated from Equation 9.4. Now, since K s =
`K e then the high-to-low delay will equal the low-to-high delay and it does not
`matter which of the two we use. Hence
`
`17p(inherent)= 2 X 1X 10-~2/64 X 10-6X 5 =6.25 ns
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