US008020022B2
`
`(12)
`
`United States Patent
`Tokuhiro
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,020,022 B2
`Sep. 13, 2011
`
`(54) DELAYTIME CONTROL OF MEMORY
`CONTROLLER
`
`(75) Inventor: Noriyuki Tokuhiro, Kawasaki (JP)
`
`(73) Assignee: Fujitsu Limited, Kawasaki (JP)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 334 days.
`
`(21) Appl. No.: 12/209,740
`(22) Filed:
`Sep. 12, 2008
`
`(65)
`
`Prior Publication Data
`
`Mar. 19, 2009
`US 2009/OO77411A1
`O
`O
`Foreign Application Priority Data
`(30)
`Sep. 18, 2007 (JP) ................................. 2007-241610
`s
`
`(51) Int. Cl.
`(2006.01)
`G06F 3/42
`(52) U.S. Cl. ........................................ 713401713,601
`(58) Field of Classification Search
`713 400401
`713/500-501, 600-601
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`7,412,616 B2 * 8/2008 Matsui et al. ................. T13/401
`7,796.465 B2* 9/2010 Swain et al. ............. 365,233.13
`2005/00471.92 A1
`3, 2005 Matsui et al.
`2005/0174878 A1
`8, 2005 Osaka et al.
`FOREIGN PATENT DOCUMENTS
`2003-099321
`4/2003
`JP
`2005-078547
`3, 2005
`JP
`2005-209168
`8, 2005
`JP
`* cited by examiner
`Primary Examiner — Raymond Phan
`(74) Attorney, Agent, or Firm — Staas & Halsey LLP
`(57)
`ABSTRACT
`A memory control circuit has a write leveling function and
`controls read/write operations by Supplying a clock signal to
`a plurality of memories through a clock signal line which is
`wired to the plurality of memories through daisy chain con
`nection. For each of the plurality of memories, a first variable
`delay unit delays, in a write operation, a data strobe signal
`output to the memory by a first delay time that is set by
`utilizing the write leveling function and a second variable
`delay unit delays, in a read operation, a data signal input from
`the memory by a second delay time that is set based on the first
`delay time.
`
`16 Claims, 20 Drawing Sheets
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`10
`^-y
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`17-k, 17
`DQ-1K (DQ-1:DQ).
`| N
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`| |
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`d1, d2
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`* 22
`DELAYTIME
`CONTROLUNT
`FIRSTDELAYTIME
`CONTROLUNT
`SECOND DELAYTIME
`CONTROLUNT
`
`1
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`24
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`DQ-n1 (DQ-n:DQ)
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`DQ-nk (DQ-n:DQ)
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`14
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`11
`-12
`CK1Add!CMD
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`MEMORY CONTROLLER
`FIRSICLOCKSIGNAL
`GENERATOR
`CONTROLCIRCUITUN
`DQS-1 (DQS)
`...DQSSIGNALGENERATOR. --
`DW
`FIRSTVARIABLEDELAY CIRCUI -
`DSOAORLIN --Dw
`: FIRSTVARIABLEDELAY CIRCUIT.L. DQ-11 (DQ-1-DQ)
`SECONDVARIABLEDELAY CIRCUI-LDR
`DSIGNALCONTROLUNI-DW
`FIRSTVARIABLEDELAY CIRCUIT;
`DQ-1(k)(DQ-1:DQ)
`lili,
`ESEUUNLVARIABLEDELAY CIRCUI - SDR
`
`- -
`
`- - -
`
`- - - - - - - - -
`
`- - - -
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`- -
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`DQS-n (DQS)
`FIRSTVARABLEDELAY CIRCUIT-L DW
`T. DW
`DQ-n1 (DQ-n:DQ)
`is - DR
`-
`P.
`DQ-nk (DQ-n:DQ)
`
`------itics:
`SECOND WARIABLEDELAY CIRCUIT
`DOSIGNALCONTROLUNT
`FIRSTWARIABLEDELAY CIRCUI
`
`
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`DIMM
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`SDRAM1
`
`:
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`D SDRAM-n
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`Micron et al. - Exhibit 1006
`Micron et al. v. Netlist - IPR2022-00236
`Page 1 of 36
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`U.S. Patent
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`Sep. 13, 2011
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`U.S. Patent
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`Micron et al. - Exhibit 1006
`Micron et al. v. Netlist - IPR2022-00236
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`. Patent
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`Sep
`. 13, 2011
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`Sheet 12 of 20
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`020,022 B2
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`Micron et al. - Exhibit 1006
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`FIG. 18A
`33-1
`32-2
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`FIG. 18B
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`FIG. 18C
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`Micron et al. - Exhibit 1006
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`Patent
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`Micron et al. - Exhibit 1006
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`Sep. 13, 2011
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`Micron et al. - Exhibit 1006
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`US 8,020,022 B2
`
`1.
`DELAYTIME CONTROL OF MEMORY
`CONTROLLER
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is related to and claims priority to Japa
`nese patent application no. 2007-241610 filed on Sep. 18.
`2007, in the Japan Patent Office, and incorporated by refer
`ence herein.
`
`10
`
`BACKGROUND
`
`2
`SDRAMs 92-1 to 92-n at the same time. According to the
`JEDEC standards, for example, a length L1 of outer dimen
`Sion of the DIMM module 91 is determined to be 133 mm.
`Assuming a data transmission speed to be 7 pS/mm, therefore,
`a difference of about 1 ns is generated in arrival time of the
`clock signal CK between the SDRAM 92-1 disposed at one
`end and the SDRAM 92-n disposed at the other end of the
`DIMM module 91 in the lengthwise direction thereof
`(namely, 7 ps/mmx133 mm=931 ps).
`For that reason, according to the JEDEC standards, it is
`specified to employ the write leveling function in the DDR3
`memory interface.
`The term “write leveling function” refers to the function of
`sampling the clock signal CK by using the data strobe signal
`DQS output from the memory controller 90, detecting the
`phase relationship between the data strobe signal DQS and
`the clock signal CK, and adjusting (compensating) a delay
`time of the data strobe signal DQS. The write leveling func
`tion is realized, as shown in FIG. 2, by incorporating variable
`delay circuits 93-1 to 93-n, which can change respective delay
`times of the data strobe signals DQS-1 to DQS-n, in the
`memory controller 90 corresponding to the plurality of
`SDRAMs 92-1 to 92-n, respectively.
`In the following description, regarding characters denoting
`the delay circuits, when one among the plurality of delay
`circuits needs to be specified, any of characters 93-1 to 93-n
`is used, while a character 93 is used when an arbitrary delay
`circuit is to be indicated.
`More specifically, for the data strobe signals DQS-1 to
`DQS-n output respectively to the plurality of SDRAMs 92-1
`to 92-n to which the clock signal line is wired through the
`daisy chain connection, a CPU (Central Processing Unit, not
`shown) sets respective delay times t1-1 to t1-n based on the
`data signals DQ-1 to DQ-n output from the plurality of
`SDRAMs 92-1 to 92-n so that the data strobe signals DQS-1
`to DQS-n are adjusted to be input respectively to the plurality
`of SDRAMs 92-1 to 92-n substantially at the same time as the
`clock signal CK for each SDRAM.
`In other words, for example, at the time of completion of
`the write leveling, the data strobe signals DQS are delayed
`through the respective delay times t1-1 to t1-n in the delay
`circuits 93-1 to 93-n which correspond to the SDRAMs 92-1
`to 92-n on the DIMM module 91, respectively, whereby the
`data strobe signal DQS and the clock signal CK are input in
`phase to each of the SDRAMs 92-1 to 92-n.
`Thus, in the DDR3 memory interface, the difference in the
`delay time caused in the write operations between the
`memory controller 90 and the plurality of SDRAMs 92 is
`adjusted by employing the write leveling function.
`Additionally, in the above-described case, the delay times
`t1-1 to t1-n are not equal to each other because the clock
`signal CK is input to the SDRAMs 92-1 to 92-n via the clock
`signal line through the daisy chain connection.
`Although, the DDR3 memory interface compensates the
`arrival time when the data strobe signals DQS-1 to DQS-n
`arrive at the SDRAMs 92-1 to 92-n in the write operations
`according to the JEDEC standards as described above, com
`pensations of the signal arrival time in read operations are not
`provided with the JEDEC standards.
`FIG. 3 is a block diagram explaining the read operation of
`the conventional DDR3 memory interface.
`The SDRAMs 92-1 though92-n output data signals DQ-1
`though DQ-n and the data strobe signals DQS-1 through
`DQS-n to the memory controller 90 on receiving the clock
`signal CK output from the memory controller 90 via the data
`signal line in the daisy chain connection in the read operation
`as shown in FIG. 3.
`
`15
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`30
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`35
`
`1. Field
`The memory control circuit, delay time control device, and
`delay time control method relate to a technique for control
`ling read/write operations for a plurality of memories to
`which a clock signal line is wired through the daisy chain
`connection, as in, e.g., a DDR3 memory interface, by Supply
`ing a clock signal through the clock signal line.
`2. Description of the Related Art
`Recently, the DDR3 (Double Data Rate 3) memory inter
`face has been standardized as standards of a DRAM (Dy
`namic Random Access Memory) by JEDEC (Joint Electron
`Device Engineering Council) (see, e.g., JDEC STANDARD
`25
`(JESD79-3; DDR3 SDRAM Standard). Unlike the hitherto
`practiced DDR (Double Data Rate) memory interface and
`DDR2 (Double Data Rate 2) memory interface (see, e.g.,
`Japanese Laid-open Patent Publication No. 2003-99321, No.
`2005-78547, and No. 2005-209168), the DDR3 memory
`interface employs fly-by topology for connection between a
`memory controller and a DIMM (Dual Inline Memory Mod
`ule).
`FIG. 1 is a block diagram showing a configuration example
`of the recently proposed DDR3 memory interface, and FIG.2
`is a block diagram for explaining a write leveling operation in
`the DDR3 memory interface.
`As shown in FIG. 1, for example, the fly-by topology is
`configured such that a signal line for each of a clock signal
`CK, an address signal Add and a command signal CMD is
`wired from a memory controller 90 to a plurality (number n)
`of SDRAMs (Synchronous Dynamic Random Access
`Memories) 92-1 to 92-n (n is a natural number of 2 or more)
`on a DIMM module 91 through the daisy chain connection.
`On the other hand, data signal lines for data signals DQ and
`data strobe signals DQS are wired from the memory control
`ler 90 to the plurality of SDRAMs 92-1 to 92-n on the DIMM
`module 91, respectively.
`In the following description, regarding characters denoting
`the SDRAMs, when one among the plurality of SDRAMs
`50
`needs to be specified, any of characters 92-1 to 92-n is used,
`while a character 92 is used when an arbitrary SDRAM is to
`be indicated.
`Also, regarding characters denoting the data signals, when
`one among the plurality of data signals needs to be specified,
`55
`any of characters DQ-1 to DQ-n is used, while a character DQ
`is used when an arbitrary data signal is to be indicated.
`Further, regarding characters denoting the data strobe Sig
`nals, when one among the plurality of data strobe signals
`needs to be specified, any of characters DQS-1 to DQS-n is
`used, while a character DQS is used when an arbitrary data
`strobe signal is to be indicated.
`Thus, in the DDR3 memory interface, because the clock
`signal line for the clock signal CK is wired to the plurality of
`SDRAMs 92-1 to 92-n through the daisy chain connection
`65
`and a propagation delay is generated, the clock signal CK
`output from the memory controller 90 cannot reach all the
`
`40
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`45
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`US 8,020,022 B2
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`3
`Therefore, the data signal DQ-n and the data strove signal
`DQS-n output from the SDRAM 92-n to which the clock
`signal CK is input lastly arrives at the memory controller 90
`approximately 1 ns after the data signal DQ-1 and the data
`strobe signal DQS-1 output from the SDRAM92-1 to which
`the clock signal CK is input firstly where the data transmis
`sion speed is 7 pS/mm as the case described above. 7 pS/mmx
`133 mm=931 ps.
`The delay on the order of 1 ns will become greater than a
`typical data period of the DDR3 memory interface, at mini
`mum 0.625 ns, so that the delay may affect in reading data
`from the SDRAM 92.
`
`SUMMARY
`
`10
`
`15
`
`25
`
`A memory control circuit having a write leveling function
`and controlling read/write operations by Supplying a clock
`signal to a plurality of memories through a clock signal line
`which is wired to the plurality of memories through daisy
`chain connection is comprising, for each of the plurality of
`memories, a first variable delay unit for delaying, in the write
`operation, a data strobe signal output to the memory by a first
`delay time that is set by utilizing the write leveling function
`and a second variable delay unit for delaying, in the read
`operation, a data signal input from the memory by a second
`delay time that is set based on the first delay time.
`Additional objects and advantages of the embodiment will
`be set forth in part in the description which follows, and in
`part will be obvious from the description, or may be learned
`by practice of the embodiment. The object and advantages of
`the embodiment will be realized and attained by the elements
`and combinations particularly pointed out in the appended
`claims.
`It is to be understood that both the foregoing general
`description and the following detailed description are exem
`35
`plary and explanatory only and are not restrictive of the
`embodiment, as claimed.
`These together with other aspects and advantages which
`will be subsequently apparent, reside in the details of con
`struction and operation as more fully hereinafter described
`40
`and claimed, reference being had to the accompanying draw
`ings forming a part hereof, wherein like numerals refer to like
`parts throughout.
`
`30
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`45
`
`4
`FIG. 8 is a block diagram for explaining calculation for
`mulae used to determine a first delay time in the first delay
`time control unit of the information processing apparatus
`according to the first embodiment;
`FIG. 9 is a block diagram for explaining the calculation
`formulae used to determine the first delay time in the first
`delay time control unit of the information processing appa
`ratus according to the first embodiment;
`FIG. 10 is an explanatory diagram for explaining a write
`operation using a first variable delay circuit in the information
`processing apparatus according to the first embodiment;
`FIG. 11 is an explanatory diagram for explaining a read
`operation using a second variable delay circuit in the infor
`mation processing apparatus according to the first embodi
`ment;
`FIG. 12 is a circuit diagram showing a portion of the
`memory controller, which corresponds to the SDRAM-1, in
`the information processing apparatus according to a modifi
`cation of the first embodiment;
`FIG. 13 is a circuit diagram showing a portion of the
`memory controller, which corresponds to the SDRAM-n, in
`the information processing apparatus according to the modi
`fication of the first embodiment;
`FIG. 14 is a circuit diagram showingaportion of a memory
`controller, which corresponds to SDRAM-1, in an informa
`tion processing apparatus according to a second embodiment;
`FIG. 15 is a circuit diagram showing a portion of the
`memory controller, which corresponds to SDRAM-n, in the
`information processing apparatus according to the second
`embodiment;
`FIG. 16 is a diagram for explaining the function of a third
`variable delay circuit of the memory controller in the infor
`mation processing apparatus according to the second embodi
`ment;
`FIG. 17 is a block diagram showing a configuration
`example of the third variable delay circuit in the information
`processing apparatus according to the second embodiment;
`FIGS. 18A to 18C are circuit diagrams each showing a
`configuration example of a unit circuit of the third variable
`delay circuit in the information processing apparatus accord
`ing to the second embodiment;
`FIG. 19 is a circuit diagram showing a portion of the
`memory controller, which corresponds to the SDRAM-1, in
`the information processing apparatus according to a modifi
`cation of the second embodiment;
`FIG. 20 is a circuit diagram showing a portion of the
`memory controller, which corresponds to the SDRAM-n, in
`the information processing apparatus according to the modi
`fication of the second embodiment; and
`FIG. 21 is a block diagram for explaining another example
`of use of the third variable delay circuit in the information
`processing apparatus according to the second embodiment.
`
`FIG. 1 is a block diagram showing a configuration example
`of the known DDR3 memory interface;
`FIG. 2 is a block diagram for explaining a write leveling
`operation in the known DDR3 memory interface;
`FIG.3 is a block diagram for explaining a read operation in
`the known DDR3 memory interface;
`FIG. 4 is a block diagram showing a configuration example
`of an information processing apparatus according to a first
`embodiment;
`FIG.5 is a block diagram showing a configuration example
`of a circuit of a memory controller, which corresponds to
`SDRAM-1, in the information processing apparatus accord
`ing to the first embodiment;
`FIG. 6 is a block diagram showing a configuration example
`of a circuit of the memory controller, which corresponds to
`SDRAM-n, in the information processing apparatus accord
`ing to the first embodiment;
`FIG. 7 is an explanatory diagram for explaining the write
`leveling function of a first delay time control unit in the
`information processing apparatus according to the first
`embodiment;
`
`50
`
`DETAILED DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`55
`
`Embodiments will be described below with reference to the
`drawings.
`
`60
`
`65
`
`1 First Embodiment
`FIG. 4 is a block diagram showing a configuration example
`of an information processing apparatus according to a first
`embodiment, FIG. 5 is a block diagram showing a configu
`ration example of a circuit of a memory controller, which
`corresponds to SDRAM-1, in the information processing
`apparatus, and FIG. 6 is a block diagram showing a configu
`
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`US 8,020,022 B2
`
`5
`ration example of a circuit of the memory controller, which
`corresponds to SDRAM-n, in the information processing
`apparatus.
`As shown in FIG. 4, an information processing apparatus
`(delay time control device) 10 according to the first embodi
`ment is constituted as a computer comprising a DIMM (Dual
`Inline Memory Module) 11, a memory controller (memory
`control circuit) 12, and a CPU (Central Processing Unit) 13.
`The DIMM 11 is a memory module incorporating a plu
`rality of memories therein. In the first embodiment, as shown
`in FIG. 4, the DIMM 11 includes a plurality (number n) of
`SDRAMs (Synchronous DRAMs (Dynamic Random Access
`Memories)), i.e., SDRAM-1 to SDRAM-n (n is a natural
`number of 2 or more). Also, “n” represents the number of
`channel (ch), but for the sake of simplicity, only the
`SDRAM-1 and SDRAM-n are illustrated in FIG. 4. It is to be
`noted that SDRAM itself is the known technique and a
`detailed description thereof is omitted here.
`In the following description, regarding characters denoting
`the SDRAMs, when one among the plurality of SDRAMs
`needs to be specified, any of 1 to n is suffixed to SDRAM
`along with '-', while just SDRAM is used when an arbitrary
`SDRAM is to be indicated.
`Further, in the first embodiment, fly-by topology is
`employed for wiring between the memory controller 12 and
`the plural SDRAMs of SDRAM-1 to SDRAM-n.
`The term “fly-by topology” refers the daisy chain connec
`tion is used as part of the wiring between the memory con
`troller 12 and the plural SDRAMs of SDRAM-1 to SDRAM
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`The plural control circuit units 15-1 to 15-in are constituted
`corresponding to the plural SDRAMs of SDRAM-1 to
`SDRAM-n, respectively. In other words, as shown in FIG.4,
`the memory controller 12 includes, for example, the control
`circuit unit 15-1 corresponding to SDRAM-1 and the control
`circuit unit 15-in corresponding to SDRAM-n.
`In the following description, regarding characters denoting
`the control circuit units, when one among the plurality of
`control circuit units needs to be specified, any of 1 to n is
`suffixed to a character 15 along with “-”, while just the char
`acter 15 is used when an arbitrary control circuit unit is to be
`indicated.
`Also, for the sake of simplicity, only the control circuit unit
`15-1 and the control circuit unit 15-in are illustrated in the
`drawings.
`The first clock signal generator 14 generates and outputs
`the clock signal CK1 having a predetermined cycle based on
`a clock signal CLK input from a CPU13 (described later). As
`shown in FIGS. 5 and 9, for example, the first clock signal
`generator 14 outputs the clock signal CK1 to not only the
`DIMM 11 (SDRAM-1 to SDRAM-n), but also to the plural
`control circuit units 15-1 to 15-in through the clock signal
`lines. The first clock signal generator 14 may output, as the
`clock signal CK1, a clock signal having the same clock cycle
`as that of the clock signal CLK, or a clock signal produced by
`converting the clock signal CLK to have a different clock
`cycle, e.g., /2 or 4 of the original clock cycle.
`The control circuit unit 15 is to control input/output of the
`data strobe signal DQS and the data signals DQ. As shown in
`FIGS. 4 to 6, for example, the control circuit unit 15 com
`prises a DQS signal generator 16, a number k (k is a natural
`number of 2 or more) of DQ signal control units 17-1 to 17-k,
`and a logical sum circuit OR (see FIGS. 5 and 6).
`In the following description, regarding characters denoting
`the DQ signal control units, when one among the DQ signal
`control units needs to be specified, any of 1 to k is suffixed to
`a character 17 along with “-”, while just the character 17 is
`used when an arbitrary DQ signal control unit is to be indi
`cated.
`Also, for the sake of simplicity, only the DQ signal control
`unit 17-1 and the DQ signal control units 17-kare illustrated
`in the drawings.
`The DQS signal generator 16 is to generate the data strobe
`signal DQS and is included in each control circuit unit 15 in
`a one-to-one relation. As shown in FIG. 5, for example, the
`control circuit unit 15-1 generates a data strobe signal DQS-1
`and outputs it to SDRAM-1. Also, as shown in FIG. 6, the
`control circuit unit 15-in generates a data strobe signal DQS-n
`and outputs it to SDRAM-n.
`In the following description, regarding characters denoting
`the data strobe signals, when one among the plurality of data
`strobe signals needs to be specified, any of characters DQS-1
`to DQS-n is used, while just a character DQS is used when an
`arbitrary data strobe signal is to be indicated.
`As shown in FIGS. 5 and 6, for example, the DQS signal
`generator 16 comprises a first variable delay circuit (first
`variable delay unit) DW0, a second clock signal generator 18,
`and a flip-flop FF0.
`The first variable delay circuit DW0 is to delay the clock
`signal CLK, which is input from the CPU13 (described later),
`in accordance with a first control signal d1 from a first delay
`time control unit 23 (described later), and to output the
`delayed clock signal. For example, the first variable delay
`circuit DW0 delays the clock signal CLK, which is input from
`the CPU 13 (described later), by a first delay time set by the
`
`In the first embodiment, therefore, a clock signal line for
`outputting (supplying) a clock signal CK1 generated by a first
`clock signal generator 14 (described later) is wired to the
`SDRAM-1 to the SDRAM-n through the daisy chain connec
`tion. Stated another way, as shown in FIG. 4, the clock signal
`line connected to the first clock signal generator 14 is con
`nected to the SDRAM-1 to the SDRAM-n in series one after
`another. As with the clock signal line, other signal lines for
`outputting an address signal Addanda command signal CMD
`are also each connected to the SDRAM-1 to the SDRAM-n
`40
`through the daisy chain connection.
`Data signal line for interconnecting the memory controller
`12 and the plural SDRAMs of SDRAM-1 to SDRAM-n are
`connected from the memory controller 12 respectively to the
`plural SDRAMs of SDRAM-1 to SDRAM-n in parallel. In
`45
`the exemplary circuit diagram shown in FIG. 5, one DQS
`signal line (data signal line) for transmitting the data strobe
`signal DQS and a number k (k is a natural number of 2 or
`more) of DQ signal lines (data signal lines) for transmitting
`data signals DQ are connected from the memory controller 12
`to each of the plural SDRAMs of SDRAM-1 to SDRAM-n in
`parallel. Further, those data signal lines are wired in lengths
`equal to one another (i.e. in the same length). In other words,
`the plurality of data signal lines connecting the memory con
`troller 12 and the plural SDRAMs of SDRAM-1 to
`SDRAM-n have the same length.
`The memory controller 12 is a DDR3 (Double Data Rate 3)
`memory interface for controlling read/write operations by
`Supplying, through the clock signal line, the clock signal CK1
`to the plural SDRAMs of SDRAM-1 to SDRAM-n to which
`the clock signal line is wired through the daisy chain connec
`tion. As shown in FIG. 4, by way of example, the memory
`controller 12 comprises the first clock signal generator 14 and
`a plurality of control circuit units 15-1 to 15-n.
`In addition, the memory controller 12 has the write leveling
`function. Details of the write leveling function will be
`described later.
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`Micron et al. - Exhibit 1006
`Micron et al. v. Netlist - IPR2022-00236
`Page 24 of 36
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`7
`first delay time control unit 23 (described later), and then
`outputs the delayed clock signal to the second clock signal
`generator 18.
`In this embodiment, respective first delay times are set for
`the plurality of control circuit units 15-1 to 15-in. More spe
`cifically, a first delay time Dt1-1 is set for the first variable
`delay circuit DW0 of the control circuit unit 15-1. Likewise,
`a first delay time Dt1-n is set for the first variable delay circuit
`DWO of the control circuit unit 15-in.
`In the following description, regarding characters denoting
`the first delay times, when one among the plurality of first
`delay times needs to be specified, any of characters Dt1-1 to
`Dt1-n is used, while just a character Dt1 is used when an
`arbitrary first delay time is to be indicated.
`The second clock signal generator 18 is to generate and
`output (Supply) a clock signal CK2 based on the clock signal
`CLK input from the CPU 13 (described later). As shown in
`FIGS. 5 and 6, when the clock signal CLK is input, the second
`clock signal generator 18 outputs the clock signal CK2 having
`a predetermined cycle to the flip-flop FF0 and to flip-flops
`FF2 and FF4 (described later). The second clock signal gen
`erator 18 may output, as the clock signal CK2, a clock signal
`having the same clock cycle as that of the clock signal CLK,
`or a clock signal produced by converting the clock signal
`CLK to have a different clock cycle, e.g., /2 or 4 of the
`original clock cycle.
`The flip-flop FF0 is to generate and output the data strobe
`signal DQS in accordance with the clock signal CK2 input
`from the second clock signal generator 18. As shown in FIGS.
`5 and 6, for example, when the clock signal CK2 is input, the
`flip-flop FF0 generates the data strobe signal DQS and out
`puts it to the SDRAM.
`The DQ signal control unit 17 is to control input/output of
`the data signal DQ. As shown in FIGS. 5 and 6, for example,
`35
`the DQ signal control unit 17 comprises a DQ signal input
`control unit 19 and a DQ signal output control unit 20. More
`specifically, as shown in FIGS. 5 and 6, in each of the plurality
`(number n) of control circuit units 15-1 to 15-in, the DQ signal
`control unit 17-1 comprises a DQ signal input control unit
`40
`19-1 and a DQ signal output control unit 20-1. Likewise, a DQ
`signal control unit 17-k comprises a DQ signal input control
`unit 19-k and a DQ signal output control unit 20-k.
`In the following description, regarding characters denoting
`the DQ signal input control units, when one among the plu
`rality (number k) of DQ signal input control units needs to be
`specified, any of characters 19-1 to 19-k is used, while just a
`character 19 is used when an arbitrary DQ signal input control
`unit is to be indicated. Also, regarding characters denoting the
`DQ signal output control units, when one among the plurality
`of DQ signal output control units needs to be specified, any of
`characters 20-1 to 20-k is used, while just a character 20 is
`used when an arbitrary DQ signal output control unit is to be
`indicated.
`The DQ signal input control unit 19 executes control to
`output the data signal DQ, which is input from the CPU 13
`(described later), to the SDRAM in the write operation. As
`shown in FIG. 5, for example, in the control circuit unit 15-1,
`the plurality (numberk) of DQ signal input control units 19-1
`to 19-k perform control such that, taking 19-1 as an example,
`a first data signal I DQe-11 and a second data signal
`I DQo-11 each input from the CPU 13 (described later) are
`output as a data signal DQ-11 to the SDRAM-1, and that,
`taking 19-kas an example, a first data signal I DQe-1k and
`a second data signal I DQo-1R each input from the CPU 13
`(described later) are output as a data signal DQ-1R to the
`SDRAM-1.
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`US 8,020,022 B2
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`Also, the DQ signal input control unit 19 executes control
`in the control circuit unit 15-in as follows. As shown in FIG. 6,
`for example, the plurality of DQ signal input control units
`19-1 to 19-k perform control such that, taking 19-1 as an
`example, a first data signal I DQe-n1 and a second data
`signal I DQo-n1 each input from the CPU 13 (described
`later) are output as a data signal DQ-n1 to the SDRAM-n,
`and that, taking 19-kas an example, a first data signal I DQe
`nk and a second data signal I DQo-nk each input from the
`CPU 13 (described later) are output as a data signal DQ-nk
`to the SDRAM-n.
`In the following description, regarding characters denoting
`the first data signals, when one among the plurality of first
`data signals needs to be specified, any of characters I DQe
`11 to I DQe-1R and I DQe-n1 to I DQe-nk is used,
`while just a character I DQe is used when an arbitrary first
`data signal is to be indicated. Also, regarding characters
`denoting the second data signals, when one among the plu
`rality of second data signals needs to be specified, any of
`characters I DQo-11 to I DQo-1 k and I DQo-n1 to
`I DQo-nk is used, while just a character I DQo is used
`when an arbitrary second data signal is to be indicated.
`Further, in the following description, when the first data
`signal or t