as) United States
`a2) Patent Application Publication 10) Pub. No.: US 2007/0206776 Al
`
` Patel et al. (43) Pub. Date: Sep. 6, 2007
`
`
`US 20070206776A1
`
`(54) MAINTAINING LINE VOLTAGE DURING
`RESET
`
`Related U.S. Application Data
`
`(76)
`
`Inventors: Dipak R. Patel, Hatboro, PA (US);
`Christopher J. Cotignola, Doylestown,
`PA (US); Thomas C. Gross, Honey
`Brook, PA (US)
`
`(51)
`
`(60) Provisional application No. 60/779,517, filed on Mar.
`6, 2006.
`
`.
`.
`oo.
`Publication Classification
`
`Int. cl
`(2006.01)
`HO4M 1/00
`(2006.01)
`HO04M 9/00
`52) US. CD.
`eccesceecsccneceseessecssesneenseaersneesees 379/399.01
`62)
`(57)
`
`ABSTRACT
`
`Correspondence Address:
`GENERAL INSTRUMENT CORPORATION
`DBA THE CONNECTED
`HOME SOLUTIONS BUSINESS OFAfirst clock signal is generatedby a first circuit and a second
`MOTOROLA,INC.
`clock signal is generated by an auxiliary clock circuit. A
`101 TOURNAMENTDRIVE
`switch controls whetherthe first clock signal or the second
`HORSHAM,PA 19044 (US)
`clock signal is provided to a subscriberline integrated circuit
`(SLIC). The SLIC is operable to generate a line voltage
`within predeterminedtolerances on a loop line at a customer
`premisesif the SLIC is receivingthefirst clock signal or the
`second clock signal.
`
`(21) Appl. No.:
`
`11/411,696
`
`(22)
`
`Filed:
`
`Apr. 26, 2006
`
`CENTRAL
`LOCATION
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`
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`
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`PREMISES
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`

`

`Patent Application Publication
`
`Sep. 6, 2007 Sheet 1 of 8
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`US 2007/0206776 A1
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`Patent Application Publication
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`Sep. 6, 2007 Sheet 3 of 8
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`Patent Application Publication
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`US 2007/0206776 A1
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`Patent Application Publication
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`Sep. 6, 2007 Sheet 6 of 8
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`US 2007/0206776 A1
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`Patent Application Publication
`
`Sep. 6, 2007 Sheet 7 of 8
`
`US 2007/0206776 A1
`
`
`
`DETECT SOFT RESET
`
`
`
`STORE CALIBRATION DATA
`
`501
`
`502
`
`
`
`SLIC
`
`IN ON-HOOK
`
`STATUS ?
`
`503
`
`PERFORM RESET
`
`504
`
`AUXILIARY CLOCK CIRCUIT
`DETECTS RESET
`
`505
`
`8
`
`

`

`Patent Application Publication
`
`Sep. 6, 2007 Sheet 8 of 8
`
`US 2007/0206776 A1
`
`SWITCH TO CLOCK SIGNAL
`GENERATED BY AUXILIARY
`CLOCK CIRCUIT
`
`LONGER IN RESET
`
`DETECT PROCESSOR IS NO
`
`GENERATED BY PROCESSOR
`
`SWITCH TO CLOCK SIGNAL
`
`RESET SLIC
`
`INITIALIZE SLIC AFTER RESET
`
`FIG. 5B
`
`506
`
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`
`9
`
`

`

`US 2007/0206776 Al
`
`Sep. 6, 2007
`
`MAINTAINING LINE VOLTAGE DURING RESET
`
`PRIORITY
`
`[0001] This application claims the benefit of U.S. Provi-
`sional Patent Application No. 60/779,517, filed Mar. 6,
`2006, and entitled, “MTA Design For Line Voltage Across
`Reset”. The aforementionedprovisional patent application is
`incorporated by reference in its entirety.
`
`BACKGROUND
`
`[0002] There are services that a plain old telephone system
`(POTS) can sustain while executing many sorts of system
`maintenance. Oneof these servicesis the ability to maintain
`loop line voltage at a customer premises to keep customer
`premise equipment (CPE) devices operating and unaffected
`by the system maintenance.
`
`[0003] A subscriber line circuit in a plain old telephone
`system (POTS)is a circuit connecting a subscriber line at a
`customer premises to the central office. The subscriber line
`is traditionally a twisted-pair loop for carrying analog voice.
`Today, the subscriberline is also used for digital services as
`well, such as provided via cable, DSL orsatellite.
`
`[0004] Customer premise equipment (CPE) devices, such
`as phones, facsimiles, home security systems, answering
`machines, etc., connected to the subscriber line at
`the
`customer premises may depend on the line voltage of the
`subscriber line for proper operation. For example, an alarm
`system at a customer premises monitors the line voltage. If
`the line voltage falls below a threshold for a predetermined
`period of time, the alarm system assumesthe subscriberline
`has been cut, and sends an alarm message to a remote
`monitoring station. In addition, the alarm system activates a
`loud, local alarm siren, which can wake everyone in the
`middle of the night for a false alarm if the line voltage falls
`below a threshold in the middle of the night.
`
`[0005] The POTS hasthe ability to maintain line voltage
`to keep the CPE devices operating and unaffected when
`system maintenance is performed, such as software down-
`loads and upgrades, system reboots, and system re-configu-
`rations. However, the ability to maintain line voltage during
`system maintenance may not be supported by a multimedia
`terminal adaptor (MTA) for a voice-over-internet-protocol
`(VoIP) network. VoIP is a digital telephone service that may
`be provided using the subscriber home wiring and typically
`replaces conventional POTSservice provided by a telephone
`company. VoIP may be deployed at the customer premises
`via the MTA. The MTAinterfaces with an IP network andis
`operable to adapt VoIP data for use by CPE devices con-
`nected to the subscriber line via the home wiring. The MTA
`may be embedded in a modem,such as a cable modem or
`DSL modem, as an embedded MTA (eMTA) or may be
`provided as a standalone device connected to the modem.
`
`[0006] When maintenance is performed on the modem or
`MTA,which may include software downloads, correcting a
`lock-up situation or other maintenance, the line voltage on
`the subscriber line may drop because the MTA does not
`include the ability to maintain the line voltage when being
`reset. This may result in failure or improper operation of a
`CPE device. For example, if the line voltage falls below a
`threshold for a predetermined period of time,
`the alarm
`system assumesthe subscriber line has been cut, and sends
`
`a false alarm to the remote monitoring station. Furthermore,
`scheduled system maintenance is typically performed during
`non-peak hours, such as late at night. Thus, a false alarm
`caused by the scheduled maintenance may appear real,
`because homerobberies mostly occur during the late night
`hours.
`
`SUMMARY
`
`[0007] According to an embodiment,a first clock signal is
`generated by a first circuit and a second clock signal is
`generated by an auxiliary clock circuit. A switch controls
`whether the first clock signal or the second clock signal is
`provided to a subscriber line integrated circuit (SLIC). The
`SLIC is operable to generate a line voltage within predeter-
`minedtolerances on a loop line at a customer premisesif the
`SLIC is receiving the first clock signal or the second clock
`signal.
`
`[0008] The first circuit may include a processor. If the
`processor goesinto reset, the SLIC conventionally is unable
`to generate a line voltage on the loop line. This may cause
`CPEdevicesto fail or operate incorrectly, such as generating
`a false alarm if the CPE device includes an alarm system.
`According to an embodiment, the auxiliary clock circuit
`may be used to generate the clock signal for the SLIC if the
`processorgoes into reset, thus allowing the SLIC to maintain
`the line voltage on the loop line.
`
`[0009] According to another embodiment, a method of
`controlling a clock signal for a SLIC in a multimedia
`terminal adaptor includes receiving a first clock signal at a
`SLIC. Ifa soft reset is detected, the clock signal for the SLIC
`is switched from the first clock signal to a second clock
`signal generated by an auxiliary clock circuit. The SLIC is
`able to generate a line voltage within predeterminedtoler-
`ances on a loop line at a customer premises if the SLIC is
`receiving the first clock signal or the second clock signal.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0010] Embodiments are illustrated by way of example
`and not limited in the following Figure(s), in which like
`numerals indicate like elements, in which:
`
`[0011]
`ment;
`
`FIG. 1 illustrates a system, according to an embodi-
`
`FIG. 2A illustrates a block diagram of a modem
`[0012]
`with an eMTA,according to an embodiment;
`
`FIG. 2B illustrates a block diagram of a modem
`[0013]
`and a standalone MTA, according to an embodiment;
`
`FIG.3 illustrates a block diagram of an auxiliary
`[0014]
`clock circuit, according to an embodiment;
`
`FIG. 4A illustrates a schematic diagram of the
`[0015]
`auxiliary clock circuit, according to an embodiment;
`
`FIG. 4B illustrates a schematic diagram of a SLIC
`[0016]
`reset circuit, according to an embodiment; and
`
`[0017] FIGS. 5A-B illustrates a flow chart of a method for
`maintaining line voltage during a soft reset, according to an
`embodiment.
`
`DETAILED DESCRIPTION
`
`[0018] For simplicity and illustrative purposes, the prin-
`ciples of the embodimentsare described by referring mainly
`
`10
`
`10
`
`

`

`US 2007/0206776 Al
`
`Sep. 6, 2007
`
`to examples thereof. In the following description, numerous
`specific details are set forth in order to provide a thorough
`understanding of the embodiments.
`It will be apparent
`however, to one of ordinary skill in the art, that the embodi-
`ments may bepracticed without limitation to these specific
`details. In other instances, well known methods and struc-
`tures have not been described in detail so as not to unnec-
`
`essarily obscure the embodiments.
`
`[0019] FIG. 1 illustrates a system 100, according to an
`embodiment. The system 100 includes a central location 101
`transmitting digital content to a plurality of customer pre-
`mises 110a-n via a network 105. The central location 101
`
`mayinclude a cable head-end or a central office connected
`to a cable head-end providing communication services to the
`customerpremises 110a-n. The network 105 mayinclude an
`IP network for providing digital communication services.
`The digital communication services may include a high-
`speed Internet connection, cable television, VoIP, andsatel-
`lite services, etc.
`
`[0020] The customer premises 110a-n may each include a
`modem and an MTAproviding VoIP services. For example,
`the customer premise 110a is shown with a modem 120
`having an MTA 121. Although not shown, one or more of the
`remaining customer premises 1105-7 may include a modem
`and an MTA. The MTA 121 may be embeddedin the modem
`120 or provided as a standalone device connected to the
`modem 120. In one embodiment, the modem 120 is a cable
`modem. However,
`the modem 120 may include a DSL
`modem, satellite modem, or other types of modems. The
`modem 120 is operable to receive digital data from the
`central location 101 for use at the customer premises 110a.
`The digital data may includedigital audio, digital video, data
`downloaded from the Internet, etc. The MTA 120 provides
`VoIP services for the customer premises 110a, as described
`in further detail below.
`
`[0021] One or more CPE devices 11la-e may be con-
`nected to the twisted pair loop, referred to as the loop line
`140 at the customer premises 110a. The loop line 140, for
`example,
`is a twisted pair copper subscriber line at the
`customer premises 110a. Examples of CPE devices include
`phones, home security systems, answering machines, fac-
`similes, and others. According to an embodiment, the MTA
`121 is operable to maintain the line voltage on the loop line
`140 during system maintenance, which allows the CPE
`devices 11la-e that utilize the line voltage to maintain
`normal operation during system maintenance.
`
`[0022] FIG. 2Aillustrates a block diagram of the modem
`120 with eMTA,according to an embodiment. The modem
`120 includes a tuner 129, a digital signal processing (DSP)
`circuit 125, a processor 122, a subscriber line integrated
`circuit (SLIC) 123, an auxiliary clock circuit 124, nonvola-
`tile memory 128, a power supply 126, and a battery-backup
`127. The modem 120 receives the digital data sent via the
`network 105 shown in FIG. 1 and demodulates and formats
`the data for transmission on the loop line 140 and for use by
`the customer premises equipment. For example, if the sys-
`tem 100 represents a cable network architecture, the pro-
`cessor 122 tunes the tuner 129 to receive high frequency
`cable (HFC) signals on predetermined channels carrying
`digital data, and the signals are demodulated as is known in
`the art. The DSP circuit 125 converts the received signals to
`
`frames for each channel. The processor 123 may be a cable
`modem processor or other type of processor depending on
`the type of modem.
`
`[0023] The SLIC 123 emulates the functions of a tele-
`phony central office, as is known in the art, for providing
`VoIP services. The SLIC 123 is provided in an MTA, which
`may be embedded in the modem 120, such as shownin FIG.
`2A. One function performed by the SLIC 123 is generating
`a line voltage on the loop line 140, which is typically
`provided by a telephone central office to a customer pre-
`mises, such that
`the customer premises equipment can
`function properly. For example, on-hook and off-hook volt-
`ages, also referred to as tip and ring voltages, are generated
`by the SLIC 123. The SLIC 123 generates a line voltage,
`which may include a tip voltage or a ring voltage, within
`predetermined tolerances.
`
`[0024] Conventionally, the line voltage of the loop line
`140 may fall outside of a predetermined tolerance during a
`soft reset because the SLIC 123 is unable to generate the
`properline voltage during the soft reset. A soft reset is when
`poweris maintained to a modem with an eMTA,such as the
`modem 120, or to a standalone MTA,but a processorfor the
`MTA,such as the processor 122, is reset. During a reboot or
`another type of reset, the power is maintained to the pro-
`cessor 122. The soft reset is different than a power cycle. A
`power cycle may be performed when poweris not main-
`tained. For example, a power cycle is performed during
`power up, after the modem 120 or MTA is off for an
`extended period. A soft reset may be caused by a software
`download to the modem 120 or other factors. During a soft
`reset, when power is maintained to the modem 120, firm-
`ware and/or hardware executes a reset of the processor 122
`and other components of the modem 120.
`
`[0025] The SLIC 123 needs a clock signal to generate the
`line voltage for the loop line 140. During a soft reset, a clock
`signal may not be provided to the SLIC 123 from the
`processor 122 if the processor 122 is in reset for architec-
`tures where the SLIC 123 receives the clock signal from the
`processor 122. According to an embodiment, the auxiliary
`clock circuit 124 generates a clock signal for the SLIC 123
`when a soft reset occurs. Thus, even if the processor 122 is
`in reset, the SLIC 123 generates the line voltage for the loop
`line 140 because the SLIC 123 is receiving a clock signal
`from the auxiliary clock circuit 124. Thus, the SLIC 123 is
`able to maintain the line voltage of the loop line 140 within
`the predetermined tolerances during the soft reset.
`
`[0026] For architectures where a clock circuit, instead of
`the processor 122, generates the clock signal for the SLIC
`123 when the modem is notreset, the clock circuit may also
`cease generating a clock signal during a soft reset. For these
`architectures,
`the auxiliary clock circuit 124 generates a
`clock signal for the SLIC 123 whena soft reset occurs, such
`as described above with respect to the embodiment where
`the processor 122 generates the clock signal for the SLIC
`123.
`
`[0027] The modem 120 also includes a nonvolatile (NV)
`memory 128. According to an embodiment, the NV memory
`128 stores calibration data that
`is generated when the
`modem 120 with an eMTA or when a standalone MTA is
`
`powered up. A calibration is typically performed by every
`modem and MTAafter a power-up. The calibration proce-
`dure generates calibration data including current measure-
`
`11
`
`11
`
`

`

`US 2007/0206776 Al
`
`Sep. 6, 2007
`
`ments, voltage measurements, and/or other data as is known
`in the art which is neededfor the calibration. The calibration
`data for different modems is different, because the circuit
`components used for each modem may haveslight vari-
`ances.
`
`[0028] Typically, the calibration data is not saved after the
`calibration. According to an embodiment, the calibration
`data is saved in the NV memory 128, so the calibration data
`maybe loaded into the SLIC 123 bythe processor 122 when
`the SLIC 123is initialized after a soft reset without requiring
`the processor 122 to perform another calibration procedure
`to generate the calibration data. Thus, the SLIC 123 can be
`initialized faster after a soft reset, because the calibration
`data is loaded into the SLIC 123 from the NV memory 128
`by the processor 122 rather than having to perform the
`calibration again. Also, the SLIC 123 maynotbe able to
`maintain the line voltage of the loop line 140 shownin FIG.
`1 when initializing. However,
`the line voltage may be
`brought within the predetermined tolerances in a much
`shorter period of time by loading the SLIC 123 with the
`calibration data from the NV memory 128. Also, the NV
`memory 128 may store error checking data, such as a
`checksum, to determine whether the calibration data stored
`in the NV memory 128is valid before loading into the SLIC
`123.
`
`[0029] The modem 120 includes a power supply 126 and
`may include a battery-backup 127 operable to supply power
`to the components of the modem 120. In one embodiment,
`the auxiliary clock circuit 124 generates a clock signal for
`the SLIC 123 only when needed, instead of continuously
`generating a clock signal. Thus, power is conserved. This is
`especially beneficial if the battery-backup 127 is supplying
`power to the modem 120 instead of the main power supply
`126, so as not to consume the limited amount of power
`available via the battery-backup 127. It will be apparent to
`one of ordinary skill in theart that in other embodiments,the
`auxiliary clock circuit 124 may be designed to generate a
`clock signal continuously or even when not needed, how-
`ever, only a clock signal from a single source is provided to
`the SLIC 123 at any given time.
`
`[0030] FIG. 2B illustrates a standalone MTA 121 con-
`nected to a modem 120a, according to an embodiment. The
`standalone MTA 121 and the modem 120a include a tuner
`
`129, a DSP circuit 125, a processor 122, a SLIC 123, an
`auxiliary clock circuit 124, nonvolatile memory 128, a
`power supply 126a for the standalone MTA 121, a power
`supply 1265 for the modem 120, and battery-backup 127 for
`the modem 120. Thecircuits in the standalone MTA 121 and
`
`the modem 120 function as described above with respect to
`FIG. 2A.
`
`It will be apparent to one ofordinary skill in the art
`[0031]
`that the modems and MTAs shown in FIGS. 2A-B may
`include more components and more connections between
`components than shown. Simplified block diagrams are
`showntoillustrate the embodiments.
`
`FIG.3 illustrates a block diagram of the auxiliary
`[0032]
`clock circuit 124, according to an embodiment. The auxil-
`iary clock circuit 124 includes an oscillator circuit 301
`generating a clock signal at a desired frequency, shown as
`hardware (H/W) CLK. The auxiliary clock circuit 124 also
`includes a switch 302 controlling whether the SLIC 123
`receives a clock signal from the processor 122 or the
`
`oscillator circuit 301. For example, the switch 302 enables
`the clock signal from the processor 122, shown as software
`(S/W) CLK,for the SLIC 123 if the processor 122 is not in
`reset, which may be detected by using an I/O line 320 of the
`processor 122. The SLIC 123 is operable to maintainthe line
`voltage for the loop line 140 when receiving a clock signal
`from either the auxiliary clock circuit 124 or the processor
`122.
`
`FIG. 4A illustrates a schematic diagram of the
`[0033]
`auxiliary clock circuit 124, according to an embodiment.
`The oscillator circuit 301 of the auxiliary clock circuit 124
`includes an input 420 receiving the I/O line 320 of the
`processor 122 that indicates whether the processor 122 is in
`reset. If the input 420 indicates that the processor 122 is in
`reset, then the oscillator circuit 301 generates a clock signal
`for the SLIC 123.
`
`[0034] The buffer 430 performsthe functions of the switch
`302 shown in FIG. 3. The buffer 430 shown in FIG.4 is
`
`enabled to output the clock signal from the processor 122 if
`the processor 122 is not in reset. If the processor 122 is in
`reset, then the buffer 430 is not enabled and the clock signal
`generated from the oscillator circuit 301 is output to the
`SLIC 123.
`
`[0035] The oscillator circuit 301 shown in FIG.4A is one
`example of a well knownoscillator circuit that may be used
`to generate a clock signal of desired frequency. Other well
`known oscillator circuits may alternatively be used. The
`oscillator circuit 301 includes a crystal 401, inverters 402,
`403 and 413 and D/Q flip flop 412. The crystal 401, inverters
`402 and 403, and the resistors connectedto the inverters 402,
`403 and 413 generate a clock signal at the frequency of the
`crystal 401. For example, a clock signal is generated at 2.048
`MHz. The desired frequency of the clock signal to be output
`to the SLIC 123 is 1.024 MHz. Thus, the D/Q flip flop 412,
`the inverters 411 and 413 andresistors shown divide the
`
`2.048 MHz by 2. The inverter 411 is provided to enable the
`D/Q flip flop 412 if the processor 122 is in reset and Vccis,
`for example, 3.3V. If a crystal is available that can provide
`a clock signalat the desired frequency, the D/Q flip flop 412
`and other components for dividing the frequency may not be
`needed.It will be apparent to one of ordinary skill in the art
`that an oscillator circuit may be used for providing a clock
`signal at a frequency other than 1.024 MHz, depending on
`the needs of the components of the modem or MTA.
`
`FIG. 4B illustrates a schematic of a SLIC reset
`[0036]
`circuit, according to an embodiment. The SLIC reset circuit
`is used to reset the SLIC 123 when switching from the clock
`generated bythe oscillator circuit 301 to the clock generated
`by the processor 122 after the processor 122 comes out of
`reset. For example, after switching to the clock generated by
`the processor 122 and after the processor 122 comes out of
`reset, the SLIC 123 may be locked up and does not respond
`to the processor 122. Thus, the processor 122 resets the
`SLIC 123 using the SLIC reset circuit. The SLIC reset
`circuit includes an input 450 from the processor 122. The
`input 450 may be connected to an I/O line from the proces-
`sor 122 that indicates when to reset the SLIC 123. The
`
`outputs 451 and 452 of the SLICreset circuit are connected
`to the SLIC 123 for resetting the SLIC 123 when enabled.
`
`[0037] After reset of the processor 122, the SLIC 123 is
`initialized. For example, the processor 122 loads the cali-
`bration data stored in the NV memory 128 shown in FIG. 2A
`
`12
`
`12
`
`

`

`US 2007/0206776 Al
`
`Sep. 6, 2007
`
`into the SLIC 123 to initialize the SLIC 123. During
`initialization,
`the SLIC 123 may not maintain the line
`voltage on the loop line 140. However, using the calibration
`data stored in the NV memory 128 minimizes the initial-
`ization time to an acceptable amount, such as less than 500
`ms.
`
`[0038] FIGS. 5A-Billustrates a method 500 for providing
`a clock signal to a SLIC during a soft reset to maintain line
`voltage, according to an embodiment. The method 500 is
`described with respect to FIGS. 1-4B by way of example and
`notlimitation.
`
`[0039] At step 501, a soft reset is detected. For example,
`the processor 122 shown in FIG. 2A detects a soft reset.
`
`[0040] At step 502, the processor 122 stores the SLIC
`calibration data in the NV memory 128. Calibration data
`may include current measurements, voltage drop measure-
`ments, and other known calibration data that is needed for
`proper performance of the modem 120. Typically, during
`power-up, calibration is performed and the calibration data
`is stored in FLASHorother volatile memory. The calibra-
`tion data may be overwritten with new calibration data when
`a new calibration is performed. At step 502, the calibration
`data is copied to NV memory 128, so that the calibration
`data may be quickly loaded wheninitializing the SLIC 123
`after a soft reset.
`
`[0041] At step 503, the processor 122 determines whether
`the SLIC 123 is in on-hook status. If on-hook status is
`
`detected, the processor 122 performsa reset at step 504. If
`talk mode, also known as off-hook status, is detected, the
`processor 122 waits until on-hook status is detected before
`executing a reset, so as not to drop a call in progress. The
`processoris reset at the step 504. This may include returning
`to a default state. Clearing registers and other functions for
`returning to the default state may be performed by the
`processor 122 executing the reset.
`
`[0042] At step 505, the auxiliary clock circuit 124 detects
`the soft reset. For example, the auxiliary clock circuit 124 is
`connected to the I/O line of the processor 122, shown as 420
`in FIG. 4A, to detect that the processor 122 is in reset.
`
`[0043] At step 506, the auxiliary clock circuit 124 controls
`the switch 301 shown in FIG. 3 to switch to a clock signal
`generated by the auxiliary clock circuit 124 instead of a
`clock signal generated by another circuit, such as the clock
`signal generated by the processor 122. Using the switch 301
`prevents the SLIC 123 from receiving two clock signals.
`Thus, after the soft reset is detected, the SLIC 123 receives
`the clock signal from the auxiliary clock circuit 124 instead
`of the processor 122. When providing a clock signal to the
`SLIC 123 when the processor 122 is in reset, the SLIC 123
`is able to maintain the line voltage on the loop line 140.
`
`[0044] At step 507, the auxiliary clock circuit 124 detects
`that the processor 122 is no longerin reset. For example, the
`auxiliary clock circuit 124 detects a low impedancestate of
`the I/O line from the processor 122 to determine that the
`processor 122 is not in reset.
`
`[0046] At step 509, the processor 122 resets the SLIC 123,
`for example, using the SLIC reset circuit shown in FIG. 4B.
`
`[0047] At step 510, the SLIC 123 is initialized after the
`soft reset. During initialization, the processor 122 loads the
`SLIC 123 with the calibration data determined at step 501.
`After initialization, the SLIC 123 resumes normal operation
`and generates the line voltage on the loop line 140.
`
`[0048] One or more of the steps of the method 500 and
`other steps described herein and software described herein
`may be implemented as software embedded or stored on a
`computer readable medium, such as the NV memory 128
`shown in FIGS. 2A-B or other storage. Steps of detecting a
`soft reset, generating a signal
`indicating a soft reset for
`switching to a clock signal generated by the clock circuit 124
`shown in FIGS. 2A-B, and steps for initialization the SLIC
`123 are some examples of steps may be performed or
`initiated by software. The steps may be embodied by a
`computer program, which may exist in a variety of forms
`both active and inactive. For example, they may exist as
`software program(s) comprised of program instructions in
`source code, object code, executable code or other formats
`for performing someof the steps when executed. Modules
`include software, such as programs, subroutines, objects,
`etc. Any of the above may bestored on a computer readable
`medium, which include storage devices and signals,
`in
`compressed or uncompressed form. Examples of suitable
`computer readable storage devices include conventional
`computer system RAM (random access memory), ROM
`(read only memory), EPROM (erasable, programmable
`ROM), EEPROM (electrically erasable, programmable
`ROM), and magnetic or optical disks or tapes. Examples of
`computer readable signals, whether modulated using a car-
`rier or not, are signals that a computer system hosting or
`running the computer program may be configured to access,
`including signals downloaded through the Internet or other
`networks. Concrete examples of the foregoing include dis-
`tribution of the programs on a CD ROM or via Internet
`download.Ina sense, the Internet itself, as an abstract entity,
`is a computer readable medium. The sameis true of com-
`puter networks in general. It is therefore to be understood
`that those functions enumerated herein may be performed by
`any electronic device capable of executing the above-de-
`scribed functions.
`
`[0049] While the embodiments have been described with
`reference to examples, those skilled in the art will be able to
`make various modifications to the described embodiments
`without departing from the true spirit and scope. The terms
`and descriptions used herein are set forth by way ofillus-
`tration only and are not meant as limitations. In particular,
`although the methods have been described by examples,
`steps of the methods may be performed in different orders
`than illustrated or simultaneously. Those skilled in the art
`will recognize that these and other variations are possible
`within the spirit and scope as defined in the following claims
`and their equivalents.
`
`Whatis claimedis:
`
`1. An apparatus comprising:
`
`[0045] At step 508, the auxiliary clock circuit 124 controls
`a first clock signal generated byafirst circuit;
`the switch 301 shown in FIG. 3 to switch to a clock signal
`generated by a circuit, such as the processor 122, other than
`the auxiliary clock circuit 124.
`
`a second clock signal generated by an auxiliary clock
`circuit;
`
`13
`
`13
`
`

`

`US 2007/0206776 Al
`
`Sep. 6, 2007
`
`a subscriber line integrated circuit (SLIC) generating a
`line voltage on a loop line if the SLIC is receiving the
`first clock signal or the second clock signal;
`
`a switch controlling whether the SLIC receives the first
`clock signal or the second clock signal based on
`whether a soft reset is detected.
`
`2. The apparatus of claim 1, wherein the switch switches
`to the first clock signal if a soft reset is not detected and
`switches to the second clock signal if the soft reset
`is
`detected.
`3. The apparatus of claim 2, wherein the first circuit is a
`processor and the soft reset is detected by the processor.
`4. The apparatus of claim 3, wherein the SLICis reset by
`the processor andinitialized after the soft reset using cali-
`bration data copied to nonvolatile memory.
`5. The apparatus of claim 4, wherein the nonvolatile
`memory stores error checking data for the calibration data,
`and the SLIC determines whether the calibration data is
`
`valid using the error checking data.
`6. The apparatus of claim 2, wherein the processor per-
`formsa reset if the soft reset is detected and the SLIC is in
`an on-hookstatus, the processor reset causing the switch to
`switch to the second clock signal.
`7. The apparatus of claim 1, wherein the apparatus com-
`prises a modem with an embedded multimedia terminal
`adaptor.
`8. The apparatus of claim 1, wherein the apparatus com-
`prises a standalone multimedia terminal adaptor.
`9. The apparatus of claim 3, wherein the switch comprises
`a buffer that outputs the first clock signal only if the buffer
`is enabled, wherein the buffer is enabled if the processoris
`not in reset.
`
`10. The apparatus of claim 3, wherein the auxiliary clock
`circuit comprises an oscillator circuit that is enabled only if
`the processoris in reset.
`11. A modem with an embedded multimedia terminal
`
`adaptor comprising:
`
`a processor operable to generate a first clock signal and
`control functions of the modem;
`
`an auxiliary clock circuit means for generating a second
`clock signal;
`
`a switch means for switching between the first clock
`signal and a second clock signal based on whether a
`soft reset is detected; and
`
`a SLIC operable to generate a line voltage on a loop line
`if the SLIC means is receiving either the first clock
`signal or the second clock signal.
`12. The modem of claim 11, further comprising:
`
`clock signal when the processoris in reset so as not to
`consume power from the power supply or the battery
`back-up when the processor is not in reset.
`14. A method of controlling a clock signal for a SLIC in
`a multimedia terminal adaptor, the method comprising:
`
`receiving a first clock signal at a SLIC;
`
`detecting a soft reset;
`
`switching from the first clock signal to a second clock
`signal generated by an auxiliary clock circuit
`in
`response to detecting the soft reset; and
`
`receiving the second clock signal at the SLIC, wherein the
`SLIC generates a line voltage within predetermined
`tolerances on a loop line at a customer premises if the
`SLIC is receiving the first clock signal or the second
`clock signal.
`15. The m