UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`
`Case No.: IPR2021-01550
`U.S. Patent No. 10,950,300
`Original Issue Date: March 16, 2021
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 10,950,300
`PURSUANT TO 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`I.
`II.
`
` Page
`TABLE OF CONTENTS
`INTRODUCTION ..............................................................................................1
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW .............3
` Grounds for Standing (37 C.F.R. §42.104(a)) .........................................3
` Notice of Lead and Backup Counsel and Service Information (37
`C.F.R. §§ 42.8(b)(3-4), 42.10(a)) .............................................................3
` Notice of Real Party-in-Interest (37 C.F.R. § 42.8(b)(1))........................4
` Notice of Related Matters (37 C.F.R. § 42.8(b)(2)) .................................4
`
`Fee for Inter Partes Review .....................................................................5
`
`Proof of Service ........................................................................................5
`IDENTIFICATION OF CLAIMS BEING CHALLENGED (37 C.F.R.
`§ 42.104(B)) ........................................................................................................5
`IV. THE BOARD SHOULD NOT EXERCISE ITS DISCRETION TO
`DENY INSTITUTION .......................................................................................7
`
`The Parallel District Court Litigation Does Not Weigh Against
`Institution ..................................................................................................7
`Petitioner’s Arguments Are Not Duplicative ........................................ 12
`
`THE 300 PATENT .......................................................................................... 12
`
`Technological Background ................................................................... 12
`1.
`Volatile, Non-volatile, and Flash Memory ................................. 12
`2.
`Programming Flash, and SLC and MLC Flash Memory
`Cells............................................................................................. 13
`Flash Architecture ....................................................................... 14
`Caching ....................................................................................... 15
`Logical Addresses, Physical Addresses, Bad Block
`Replacement, and Wear Leveling ............................................... 16
`Flash Translation Layer (“FTL”) ................................................ 17
`Speed and Wear-Leveling Considerations for MLC and
`SLC Cells .................................................................................... 18
`-i-
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`
`3.
`4.
`5.
`
`III.
`
`V.
`
`6.
`7.
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`Data Integrity Tests ..................................................................... 19
`8.
`Summary of the 300 Patent’s Disclosure .............................................. 19
`
`The 300 Patent’s Prosecution History ................................................... 21
`
`VI. CLAIM CONSTRUCTION ............................................................................ 23
`
`“data integrity test” (claims 1 and 12) ................................................... 23
`
`“comparing the stored data to the retained data in the random
`access volatile memory” (claims 1 and 12) ........................................... 25
`“periodically” ........................................................................................ 27
`
` Other Terms ........................................................................................... 28
`VII. HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE ................. 28
`
`Prior Art Overview ................................................................................ 28
`1.
`Dusija .......................................................................................... 28
`2.
`Sutardja ....................................................................................... 30
`Level of Ordinary Skill in the Art ......................................................... 31
`
` Ground 1: Dusija In View Of The Knowledge Of A POSA
`Renders Obvious Claims 1-9 And 11-12 .............................................. 31
`1.
`Claim 1 ........................................................................................ 32
`a.
`[1.PRE] “A system for storing data comprising:” ............ 32
`b.
`[1.A.1] “memory space containing volatile memory
`space and nonvolatile memory space;” ............................ 33
`[1.A.2] “wherein the nonvolatile memory space
`includes both multilevel cell (MLC) memory space
`and single level cell (SLC) memory space;” .................... 37
`[1.B] “at least one controller to operate memory
`elements and associated memory space;”......................... 38
`[1.C] “at least one MLC nonvolatile memory element
`that can be mapped into the MLC memory space;” ......... 40
`[1.D] “at least one SLC nonvolatile memory element
`that can be mapped into the SLC memory space;” .......... 41
`
`c.
`
`d.
`
`e.
`
`f.
`
`-ii-
`
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`

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`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`g.
`h.
`
`i.
`
`j.
`
`k.
`
`l.
`
`m.
`
`[1.E] “at least one random access volatile memory;” ...... 42
`[1.F] “an FTL flash translation layer, wherein the at
`least one controller, or FTL, or a combination of both
`maintain an address table in one or more of the
`memory elements and random access volatile
`memory” ........................................................................... 42
`[1.G.1] “the controller controlling access of the MLC
`and SLC nonvolatile memory elements and the
`random access volatile memory for storage of data
`therein” ............................................................................. 46
`[1.G.2] “the controller, in at least a Write access
`operation to the MLC nonvolatile memory element,
`operable to store data in the MLC nonvolatile
`memory element and retain such stored data in the
`random access volatile memory;” .................................... 47
`[1.H] “the controller performing a data integrity test
`on stored data in the MLC nonvolatile memory
`element after at least a Write access operation
`performed thereon by comparing the stored data to
`the retained data in the random access volatile
`memory;” .......................................................................... 48
`[1.I] “wherein the address table maps logical and
`physical addresses adaptable to the system, wherein
`the mapping is performed as necessitated by the
`system to maximize lifetime, and wherein the
`mapping maps blocks, pages, or bytes of data in
`either volatile or nonvolatile, or both, memories;
`and” ................................................................................... 50
`[1.J] “wherein a failure of the data integrity test
`performed by the controller results in a remapping of
`the address space to a different physical range of
`addresses and transfer of data corresponding to the
`stored data to those remapped physical addresses
`from those determined to have failed the data
`integrity test to achieve enhanced endurance.” ................ 52
`-iii-
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
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`2.
`
`3.
`
`4.
`
`Claim 2: “The system of claim 1, wherein the FTL flash
`translation layer is a software module, or a firmware
`module containing software updates.” ........................................ 54
`Claim 3: “The system of claim 1, wherein at least one of the
`random access volatile memory or the MLC and SLC
`nonvolatile memory elements are embedded in the at least
`one controller.” ............................................................................ 54
`Claim 4: “The system of claim 1, wherein the MLC and
`SLC nonvolatile memory elements comprise flash
`memory.” ..................................................................................... 55
`Claim 5: “The system of claim 1, wherein the random
`access volatile memory is dynamic random access
`memory.” ..................................................................................... 55
`Claim 6: “The system of claim 1, wherein the random
`access volatile memory is static random access memory.” ........ 56
`Claim 7: “The system of claim 1, wherein the controller,
`upon detection of a failure of the data integrity test, remaps
`the data to the SLC nonvolatile memory element.” .................... 57
`Claim 8: “The system of claim 7, wherein the SLC memory
`element has a higher endurance than the MLC memory
`element.” ..................................................................................... 57
`Claim 9: “The system of claim 1, wherein the MLC is a
`multilevel cell, wherein the multilevel cell stores at least 2
`bits per cell.” ............................................................................... 58
`10. Claim 11: “The system of claim 1 wherein the MLC allows
`a single cell to store multiple bits.” ............................................. 58
`11. Claim 12: ..................................................................................... 58
`a.
`[12.PRE] “A system for storing data comprising:” .......... 58
`b.
`[12.A] “memory space containing volatile memory
`space and nonvolatile memory space, wherein the
`nonvolatile memory space includes both multilevel
`cell (MLC) space and single level cell (SLC) space;” ..... 59
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`-iv-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`c.
`
`d.
`
`e.
`
`f.
`g.
`
`h.
`
`i.
`
`[12.B] “at least one controller to operate memory
`elements and associated memory space, and to
`maintain an address table in one or more of the
`memory elements;” ........................................................... 59
`[12.C] “at least one MLC nonvolatile memory
`element that can be mapped into the nonvolatile
`memory space;” ................................................................ 59
`[12.D] “at least one SLC nonvolatile memory
`element that can be mapped into the nonvolatile
`memory space;” ................................................................ 59
`[12.E] “at least one random access volatile memory;” .... 60
`[12.F] “the controller controlling access of the MLC
`and SLC nonvolatile memory elements and the
`random access volatile memory for storage of data
`therein, the controller, in at least a Write access
`operation to the MLC nonvolatile memory element,
`operable to store data in the MLC nonvolatile
`memory element and retain such stored data in the
`random access volatile memory;” .................................... 60
`[12.G] “the controller performing a data integrity test
`on stored data in the MLC nonvolatile memory
`element after at least a Write access operation
`performed thereon by comparing the stored data to
`the retained data in the random access volatile
`memory;” .......................................................................... 60
`[12.H] “wherein the address table maps logical and
`physical addresses adaptable to the system, wherein
`the mapping is performed as necessitated by the
`system to maximize lifetime, and wherein the
`mapping maps blocks, pages, or bytes of data in
`either volatile or nonvolatile, or both, memories;
`and” ................................................................................... 60
`
`-v-
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`j.
`
`[12.I] “wherein a failure of the data integrity test
`performed by the controller results in a remapping of
`the address space to a different physical range of
`addresses and transfer of data corresponding to the
`stored data to those remapped physical addresses
`from those determined to have failed the data
`integrity test to achieve enhanced endurance.” ................ 61
` Ground 2: Dusija In View Of Sutardja And The Knowledge Of A
`POSA Renders Obvious Claim 10 ........................................................ 61
`1.
`Claim 10: “The system of claim 1, wherein the contents of
`frequently accessed portions of the memory space are
`periodically moved from the MLC space to the SLC space.” .... 61
`2. Motivation to Combine ............................................................... 63
`VIII. CONCLUSION ................................................................................................ 65
`
`-vi-
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Apple Inc. v. Maxell, Ltd.,
`IPR2020-00204, Paper 11, 15-17 (PTAB June 19, 2020) .................................. 10
`Apple v. Fintiv,
`IPR2020-00019, Paper 11, 11 ......................................................................passim
`Juniper Networks, Inc. v. WSOU Investments LLC,
`IPR2021-00538, Paper 9, 13 (PTAB Aug. 18, 2021) ..................................... 9, 11
`Nvidia Corp. v. Invensas Corp.,
`IPR2020-00603, Paper 11, 23 (PTAB Sept. 3, 2020)......................................... 11
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 23
`Sand Revolution II, LLC v. Continental Intermodal Grp. – Trucking
`LLC,
`IPR2019-01393, Paper 24, 11-12 (PTAB June 16, 2020) ............................ 10, 12
`Vervain, LLC v. Micron Technology, Inc. et al.,
`Case No. 6:21-cv-00487 (W.D. Tex., filed May 10, 2021)
` ................................................................................................................. 4, 5, 7, 10
`Vervain, LLC v. Western Digital Corporation,
`Case No. 6:21-cv-00488 (W.D. Tex., filed May 10, 2021) .................................. 5
`Statutes
`35 U.S.C. § 314(a) ..................................................................................................... 7
`35 U.S.C. § 314(a) and § 325(d) ................................................................................ 5
`Other Authorities
`37 C.F.R. § 42.10(b) .................................................................................................. 4
`37 C.F.R. § 42.15(a) ................................................................................................... 5
`
`-vii-
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`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`37 C.F.R. §42.104(a) .................................................................................................. 3
`37 C.F.R. § 42.104(B) ................................................................................................ 5
`37 C.F.R. § 42.108(a). Section IV ............................................................................. 5
`157 Cong. Rec. S5429 (Sept. 8, 2011) (statement of Sen. Kyl) ................................ 8
`
`-viii-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`LISTING OF EXHIBITS
`
`Exhibit Description
`
`1001-1006
`
`Intentionally omitted
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`U.S. Patent No. 10,950,300 (“300 patent”)
`
`File History of U.S. Patent No. 10,950,300
`
`Declaration of Dr. David Liu (“Liu Decl.”) – IPR2021-01550
`
`U.S. Patent Application Publication No. 2011/0099460 (“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`Intentionally omitted
`
`Intentionally omitted
`
`Betty Prince, Semiconductor Memories – A Handbook of Design,
`Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617 (“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed. 2010)
`(“Micheloni”)
`
`U.S. Patent Application Publication No. 2011/0115192 (“Y. Lee”)
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601 (“Gavens”)
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`-ix-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`Exhibit Description
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`1036
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition of
`read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition, 2006,
`definition of periodic
`
`Intentionally omitted
`
`U.S. Patent Application Publication No. 2010/0172180 (“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650 (“Chin”)
`
`European Patent Specification No. EP 2.291.746 B1 (“Radke”)
`
`Intentionally omitted
`
`U.S. Patent Application Publication No. 2006/0053246 (“S. Lee”)
`
`Complaint for Patent Infringement, Dkt. No. 1, Vervain, LLC v.
`Micron Technology, Inc., Micron Semiconductor Products, Inc.,
`and Micron Technology Texas, LLC, Case No. 6:21-cv-00487-
`ADA (May 10, 2021 W.D. Tex.)
`
`Agreed Scheduling Order, Dkt. No. 24, dated September 16, 2021,
`in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas, LLC,
`Case No. 6:21-cv-00487-ADA
`
`Vervain’s Preliminary Infringement Contentions, dated August 6,
`2021, in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas, LLC,
`Case No. 6:21-cv-00487-ADA
`
`1037
`
`Judge Albright, Order Governing Proceedings - Patent Cases (OGP
`3.4), dated June 24, 2021
`
`-x-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`Exhibit Description
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`Scott McKeown, “WDTX ‘Implausible Schedule’ & Cursory
`Markman Order Highlighted,” Ropes & Gray, Patents Post-Grant,
`Inside Views & News Pertaining to the Nation’s Busiest Patent
`Court, June 2, 2021
`
`Dani Kass, Judge Albright Now Oversees 20% of New U.S. Patent
`Cases, Law360, March 10, 2021
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`1044-1046
`
`Intentionally omitted
`
`1047
`
`1048
`
`1049
`
`1050
`
`1051
`
`1052
`
`1053
`
`1054
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definitions of
`static RAM and volatile memory
`
`U.S. Patent No. 5,936,971 (“Harari”)
`
`PCT Publication No. WO 03/027828 (“Gorobets WO”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`address space
`
`U.S. Patent Application Publication No. 2009/0300269 (“Radke
`Appl.”)
`
`U.S. Patent No. 8,250,333 (“Gorobets II”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition of
`firmware
`
`-xi-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`I.
`
`INTRODUCTION
`Petitioner Micron Technology, Inc. (“Micron” or “Petitioner”) respectfully
`
`requests inter partes review of claims 1-12 (the “Challenged Claims”) of U.S. Patent
`
`No. 10,950,300 (Ex. 1007, “300 patent”) which, according to USPTO records, is
`
`assigned to Vervain, LLC (“Vervain” or “Patent Owner”). There is more than a
`
`reasonable likelihood that Petitioner will prevail with respect to at least one
`
`Challenged Claim.
`
`The 300 patent relates to flash memory devices that include both multi-level
`
`cell (MLC) and single-level cell (SLC) memory spaces. Flash memory devices with
`
`both MLC and SLC were well known and understood long before the 300 patent was
`
`filed, and the 300 patent does not contend otherwise. Instead, the 300 patent purports
`
`to improve the reliability of such devices by performing a “data integrity test” on
`
`data stored in MLC and, if the test fails, transferring the data elsewhere. During
`
`prosecution, the Examiner had rejected the 300 patent’s claims, which included a
`
`data integrity test, as obvious. In response, the Applicant amended the independent
`
`claims to specify how the data integrity test is performed. Specifically, the amended
`
`claims recite performing a data integrity test by: (1) retaining data to be written in
`
`volatile memory; (2) writing the data to non-volatile (e.g., flash) memory (a “write
`
`access operation”); (3) after the write access operation, reading back the stored data;
`
`-1-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`and (4) comparing the retained data with the stored data. After this amendment, the
`
`300 patent’s claims were allowed.
`
`The Applicant did not disclose to the Examiner, nor did the Examiner cite,
`
`U.S. Pat. Pub. No. 2011/0099460 to Dusija. Dusija teaches performing a data
`
`integrity test using a “post-write read.” As part of the test, one copy of data is cached
`
`in volatile memory while another copy of the data is written to flash memory. Then,
`
`after the write, the written data is read back and compared to the retained data. If
`
`too many errors are detected, the data is rewritten to another memory location.
`
`Dusija discloses, or at least renders obvious in view of the knowledge of a person of
`
`ordinary skill in the art, the other well-known limitations of the independent claims.
`
`Except for dependent claim 10, the 300 patent’s dependent claims are
`
`disclosed by—or represent well-understood, obvious modifications to—Dusija.
`
`Dependent claim 10 adds a “hot blocks limitation” in which “the contents of
`
`frequently accessed portions of the memory space are periodically moved from the
`
`MLC space to the SLC space.” Sutardja, which Applicant did not disclose to the
`
`Examiner and which the Examiner did not cite, squarely discloses this feature (which
`
`was well known in memory systems with MLC and SLC memory spaces).
`
`The 300 patent’s claims thus represent nothing new or non-obvious. As such,
`
`Petitioner respectfully requests that the Board institute an inter partes review of the
`
`Challenged Claims and hold them to be unpatentable.
`
`-2-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`II.
`
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW
`Grounds for Standing (37 C.F.R. §42.104(a))
`Petitioner certifies that the 300 patent is available for IPR and that Petitioner
`
`is not barred or estopped from requesting IPR of the Challenged Claims on the
`
`grounds identified herein.
`
`Notice of Lead and Backup Counsel and Service Information (37
`C.F.R. §§ 42.8(b)(3-4), 42.10(a))
`Pursuant to 37 C.F.R. §§ 42.8(b)(3-4) and 42.10(a), Petitioner provides the
`
`following designation of Lead and Back-Up counsel:
`
`Lead Counsel
`Jeremy Jason Lang
`Registration No. 73,604
`(jlang@orrick.com)
`
`Back-Up Counsel
`Jared Bobrow
`(jbobrow@orrick.com)
`Pro Hac Vice to be submitted
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`T: 650-614-7400; F: 650-614-7401
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`T: 650-614-7400; F: 650-614-7401
`
`Parth Sagdeo
`Registration No. 71,275
`(psagdeo@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`222 Berkeley St.
`Suite 2000
`Boston, MA 02116
`T: 617-880-1800; F: 617-880-1801
`
`-3-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`Christopher Childers
`Registration No. 75,237
`(cchilders@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1152 15th St. NW
`Washington, DC 20005
`T: 202-339-8441; F: 202-339-8500
`
`Petitioner consents to service by electronic mail at the following addresses:
`
`PTABDocketJ3B3@orrick.com,
`
`PTABDocketJJL2@orrick.com,
`
`PTABDocketP2S7@orrick.com, PTABDocketC4C8@orrick.com, and Micron-
`
`Vervain_OHS@orrick.com.
`
`Pursuant to 37 C.F.R. § 42.10(b), Petitioner’s Power of Attorney is attached.
`
`Notice of Real Party-in-Interest (37 C.F.R. § 42.8(b)(1))
`Petitioner Micron Technology, Inc.—along with its subsidiaries—is the real
`
`party-in-interest.
`
`Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`According to USPTO assignment records, the 300 patent is currently assigned
`
`to Vervain. Vervain has asserted the 300 patent and U.S. Patent Nos. 8,981,298,
`
`9,196,385, and 9,997,240 in a co-pending litigation, Vervain, LLC v. Micron
`
`Technology, Inc. et al., Case No. 6:21-cv-00487 (W.D. Tex., filed May 10, 2021)
`
`(“Co-Pending Litigation”). Vervain also has asserted the 300 patent and U.S. Patent
`
`Nos. 8,981,298, 9,196,385, and 9,997,240 against Western Digital Corporation,
`
`-4-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`Western Digital Technologies, Inc., and HGST, Inc. in Vervain, LLC v. Western
`
`Digital Corporation, Case No. 6:21-cv-00488 (W.D. Tex., filed May 10, 2021).
`
`In addition to this Petition, Petitioner is filing petitions for inter partes review
`
`to challenge the three other asserted patents in the Co-Pending Litigation: Petition
`
`for Inter Partes Review of U.S. Patent No. 8,981,298, IPR2021-01547, Petition for
`
`Inter Partes Review of U.S. Patent No. 9,196,385, IPR2021-01548, and Petition for
`
`Inter Partes Review of U.S. Patent No. 9,997,240, IPR2021-01549.
`
`The Director and the Board should allow this Petition under 35 U.S.C.
`
`§ 314(a) and § 325(d) and/or 37 C.F.R. § 42.108(a). Section IV.
`
`Fee for Inter Partes Review
`The Director is authorized to charge the fee specified by 37 C.F.R. § 42.15(a),
`
`and any other required fees, to Deposit Account No. 15-0665.
`
`Proof of Service
`Proof of service of this Petition on the Patent Owner at the correspondence
`
`addresses of record for the 300 patent is attached.
`
`III.
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED (37 C.F.R.
`§ 42.104(B))
`Petitioner requests IPR of claims 1-12.
`
`The 300 patent was filed on June 12, 2018. The patent also makes a facial
`
`claim of priority to a July 19, 2011 Provisional Application No. 61/509,257. 300
`
`patent, p. 2. For purposes of this petition only, it is assumed that the 300 patent’s
`
`-5-
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`

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`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`claims are entitled to the benefit of this July 19, 2011 date.
`
`Petitioner’s grounds rely on the following references:
`
`(1) U.S. Patent Application Publication No. 2011/0099460 (Ex. 1010,
`
`“Dusija”): Dusija was filed on December 18, 2009 and published on April 28, 2011.
`
`It is prior art to the 300 patent under at least §§ 102(a) and (e).
`
`(2) U.S. Patent Application Publication No. 2008/0140918 (Ex. 1011,
`
`“Sutardja”): Sutardja was filed on December 7, 2007 and published on June 12,
`
`2008. Sutardja is prior art to the 300 patent under at least §§ 102(a), (b), and (e).
`
`Petitioner challenges the claims on the following grounds:
`
`Ground 1: Claims 1-9 and 11-12 are obvious over Dusija in view of the
`
`knowledge of a person of ordinary skill in the art (a “POSA”);
`
`Ground 2: Claim 10 is obvious over Dusija and Sutardja in view of the
`
`knowledge of a POSA.
`
`None of the above references are cited on the face of the 300 patent and none
`
`were considered during prosecution of the 300 patent.
`
`These grounds are supported by the declaration of Dr. David Liu (Ex. 1009,
`
`“Liu Decl.”).
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`-6-
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`IV. THE BOARD SHOULD NOT EXERCISE ITS DISCRETION TO
`DENY INSTITUTION
`The Parallel District Court Litigation Does Not Weigh Against
`Institution
`Petitioner respectfully requests that the Board not exercise its discretion to
`
`deny institution pursuant to 35 U.S.C. § 314(a). On May 10, 2021, Vervain sued
`
`Micron, Micron Semiconductor Products, Inc., and Micron Technology Texas, LLC
`
`in the Western District of Texas, asserting the 300 patent and three other patents.
`
`Ex. 1034. Micron had no pre-suit notice of the 300 patent. Nevertheless,
`
`approximately four and a half months later, Micron filed this Petition as well as
`
`petitions on the three other asserted patents. At the time of filing this Petition, no
`
`substantial litigation activity has occurred.1 On August 6, 2021, Vervain served its
`
`preliminary infringement contentions, which identify the claims it is asserting.
`
`Given that the Co-Pending Litigation is still in its very early stages, and discovery
`
`has not commenced, Petitioner’s diligence weighs heavily in favor of institution.
`
`Should Patent Owner argue that the Board should deny institution in its
`
`discretion under the “the Fintiv factors,” and if the Board were to entertain such an
`
`1 On July 9, 2021, Micron filed a Rule 12(b)(6) Motion to Dismiss the Complaint
`
`because the Complaint is devoid of any factual allegations that plausibly allege
`
`infringement. The Court has not ruled on this motion.
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`-7-
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`argument, Petitioner respectfully requests that it be afforded an opportunity to
`
`submit a responsive brief to Patent Owner’s arguments.
`
`In any event, the Board should not exercise its discretion to deny this Petition.
`
`First, doing so would unfairly close the Board’s doors to Petitioner. Micron was
`
`extraordinarily diligent in analyzing the prior art and preparing this Petition (along
`
`with three others) to file as early as it did.
`
`Second, the Fintiv factors weigh in favor of institution. Under Fintiv factor
`
`three (investment in the parallel proceeding), Fintiv notes: “[i]f the evidence shows
`
`that the petitioner filed the petition expeditiously, such as promptly after becoming
`
`aware of the claims being asserted, this fact has weighed against exercising the
`
`authority to deny institution under NHK.” Apple v. Fintiv, IPR2020-00019, Paper
`
`11, 11. Here, Petitioner filed approximately four and a half months after receipt of
`
`the complaint and approximately six weeks after infringement contentions were
`
`served (which identified the asserted claims for the first time).2 Moreover, to date,
`
`no court resources have been devoted to analyzing prior art, invalidity, or any other
`
`substantive issue in this proceeding. No claim construction has occurred, a motion
`
`2 Denying institution would negate Congressional intent to “afford defendants a
`
`reasonable opportunity to identify and understand the patent claims that are relevant
`
`to the litigation.” 157 Cong. Rec. S5429 (Sept. 8, 2011) (statement of Sen. Kyl).
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`-8-
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`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`to dismiss is pending, and there has been no meaningful fact or expert discovery.
`
`When the Board issues its institution decision on this Petition, fact discovery will be
`
`in its infancy. See Ex. 1035 (fact discovery to begin January 21, 2022 and close
`
`August 12, 2022). Further, expert discovery is not to be completed until October 7,
`
`2022. Id. And any district court claim construction proceedings that occur before
`
`institution would add to the efficiency of this IPR proceeding because the parties
`
`will submit any district court claim construction materials to the Board. On facts
`
`nearly identical to these, the Board found this factor to weigh substantially against
`
`exercising discretion to deny institution because “while the scheduled date for a
`
`Markman hearing ha[d] passed, much of the invested effort [wa]s unconnected to
`
`the patentability challenges.” Juniper Networks, Inc. v. WSOU Investments LLC,
`
`IPR2021-00538, Paper 9, 13 (PTAB Aug. 18, 2021) (granting institution and stating
`
`that “the substantial work that remains on invalidity issues in the parallel district
`
`court litigation and Petitioner’s expeditious filing of its Petition substantially
`
`outweighs the minimal investment so far”).
`
`Under Fintiv factor six (other considerations), Fintiv notes that if the merits
`
`of the Petition are strong, which is the case here, institution of a trial may “serve the
`
`interest of overall system efficiency and integrity because it allows the proceeding
`
`to continue in the event that the parallel proceeding settles or fails to resolve the
`
`patentability question presented in the PTAB proceeding.” Apple v. Fintiv,
`
`-9-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,300
`
`IPR2020-00019, Paper 11, 15. Vervain has already brought two patent infringement
`
`lawsuits against two memory manufacturers, and others are likely in line. What’s
`
`more, Micron’s petition challenges more claims than Vervain is asserting in district
`
`court, so an IPR trial will resolve is