Declaration of Dr. David Liu
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`VERVAIN, LLC,
`Patent Owner
`
`
`
`
`Case No.: IPR2021-01550
`U.S. Patent No. 10,950,300
`Original Issue Date: March 16, 2021
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`
`
`
`DECLARATION OF DR. DAVID LIU
`
`
`
`
`
`
`
`
`
`
`
`Micron Ex. 1009, p. 1
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Declaration of Dr. David Liu
`
`
`
`
`I.
`II.
`
`Page
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 8 
`EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS ............................................................... 8 
`III. ASSIGNMENT AND MATERIALS CONSIDERED ................................ 11 
`IV. UNDERSTANDING OF THE LAW ........................................................... 14 
`V.
`LEVEL OF SKILL IN THE ART ................................................................ 18 
`VI. THE 300 PATENT’S EFFECTIVE FILING DATE ................................... 19 
`VII. THE 300 PATENT ....................................................................................... 19 
`A.
`Technological Background ................................................................ 19 
`1.
`Volatile, Non-volatile, and Flash Memory .............................. 19 
`2.
`Programming Flash, and SLC and MLC Flash Memory
`Cells.......................................................................................... 21 
`Flash Architecture .................................................................... 23 
`Caching .................................................................................... 26 
`Logical Addresses, Physical Addresses, Bad Block
`Replacement, and Wear Leveling ............................................ 27 
`Flash Translation Layer (“FTL”) ............................................. 36 
`Speed and Durability Considerations for MLC and SLC
`Cells.......................................................................................... 40 
`Data Integrity Tests .................................................................. 41 
`8.
`Summary of the 300 Patent’s Disclosure ........................................... 41 
`B.
`The 300 Patent’s Prosecution History ................................................ 44 
`C.
`VIII. CLAIM CONSTRUCTION ......................................................................... 48 
`A.
`“data integrity test” (claims 1 and 12) ................................................ 49 
`B.
`“comparing the stored data to the retained data in the random
`access volatile memory” (claims 1 and 12) ........................................ 50 
`“periodically” ..................................................................................... 53 
`C.
`D. Other Terms ........................................................................................ 54 
`
`3.
`4.
`5.
`
`6.
`7.
`
`
`
`2
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`Micron Ex. 1009, p. 2
`Micron v. Vervain
`IPR2021-01550
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`

`

`Declaration of Dr. David Liu
`
`c.
`
`d.
`
`e.
`
`
`IX. HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE .............. 54 
`A.
`Prior Art Overview ............................................................................. 54 
`1.
`Dusija ....................................................................................... 54 
`2.
`Sutardja .................................................................................... 57 
`B. Ground 1: Dusija In View Of The Knowledge Of A POSA
`Renders Obvious Claims 1-9 And 11-12 ........................................... 59 
`1.
`Claim 1 ..................................................................................... 59 
`a.
`[1.PRE] “A system for storing data comprising:” ......... 59 
`b.
`[1.A.1] “memory space containing volatile
`memory space and nonvolatile memory space;” ........... 60 
`[1.A.2] “wherein the nonvolatile memory space
`includes both multilevel cell (MLC) memory space
`and single level cell (SLC) memory space;” ................. 66 
`[1.B] “at least one controller to operate memory
`elements and associated memory space;” ...................... 68 
`[1.C] “at least one MLC nonvolatile memory
`element that can be mapped into the MLC memory
`space;” ............................................................................ 70 
`[1.D] “at least one SLC nonvolatile memory
`element that can be mapped into the SLC memory
`space;” ............................................................................ 74 
`[1.E] “at least one random access volatile
`memory;” ....................................................................... 75 
`[1.F] “an FTL flash translation layer, wherein the
`at least one controller, or FTL, or a combination of
`both maintain an address table in one or more of
`the memory elements and random access volatile
`memory” ........................................................................ 76 
`[1.G.1] “the controller controlling access of the
`MLC and SLC nonvolatile memory elements and
`the random access volatile memory for storage of
`data therein” ................................................................... 80 
`
`f.
`
`g.
`
`h.
`
`i.
`
`
`
`3
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`Micron Ex. 1009, p. 3
`Micron v. Vervain
`IPR2021-01550
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`

`

`
`
`
`
`2.
`
`3.
`
`4.
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`Declaration of Dr. David Liu
`
`j.
`
`k.
`
`l.
`
`m.
`
`[1.G.2] “the controller, in at least a Write access
`operation to the MLC nonvolatile memory
`element, operable to store data in the MLC
`nonvolatile memory element and retain such stored
`data in the random access volatile memory;” ................ 82 
`[1.H] “the controller performing a data integrity
`test on stored data in the MLC nonvolatile memory
`element after at least a Write access operation
`performed thereon by comparing the stored data to
`the retained data in the random access volatile
`memory;” ....................................................................... 83 
`[1.I] “wherein the address table maps logical and
`physical addresses adaptable to the system,
`wherein the mapping is performed as necessitated
`by the system to maximize lifetime, and wherein
`the mapping maps blocks, pages, or bytes of data
`in either volaile or nonvolatile, or both, memories;
`and” ................................................................................ 85 
`[1.J] “wherein a failure of the data integrity test
`performed by the controller results in a remapping
`of the address space to a different physical range
`of addresses and transfer of data corresponding to
`the stored data to those remapped physical
`addreses from those determined to have failed the
`data integrity test to achieve enhanced endurance.” ...... 88 
`Claim 2: “The system of claim 1, wherein the FTL flash
`translation layer is a software module, or a firmware
`module containing software updates.” ..................................... 91 
`Claim 3: “The system of claim 1, wherein at least one of
`the random access volatile memory or the MLC and SLC
`nonvolatile memory elements are embedded in the at
`least one controller.” ................................................................ 91 
`Claim 4: “The system of claim 1, wherein the MLC and
`SLC nonvolatile memory elements comprise flash
`memory.” .................................................................................. 92 
`
`4
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`Micron Ex. 1009, p. 4
`Micron v. Vervain
`IPR2021-01550
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`

`

`Claim 5: “The system of claim 1, wherein the random
`access volatile memory is dynamic random access
`memory.” .................................................................................. 92 
`Claim 6: “The system of claim 1, wherein the random
`access volatile memory is static random access memory.” ..... 93 
`Claim 7: “The system of claim 1, wherein the controller,
`upon detection of a failure of the data integrity test,
`remaps the data to the SLC nonvolatile memory
`element.” .................................................................................. 94 
`Claim 8: “The system of claim 7, wherein the SLC
`memory element has a higher endurance than the MLC
`memory element.” .................................................................... 95 
`Claim 9: “The system of claim 1, wherein the MLC is a
`multilevel cell, wherein the multilevel cell stores at least
`2 bits per cell.” ......................................................................... 95 
`10. Claim 11: “The system of claim 1 wherein the MLC
`allows a single cell to store multiple bits.” .............................. 95 
`11. Claim 12: .................................................................................. 96 
`a.
`[12.PRE] “A system for storing data comprising:” ....... 96 
`b.
`[12.A] “memory space containing volatile memory
`space and nonvolatile memory space, wherein the
`nonvolatile memory space includes both multilevel
`cell (MLC) space and single level cell (SLC)
`space;” ............................................................................ 96 
`[12.B] “at least one controller to operate memory
`elements and associated memory space, and to
`maintain an address table in one or more of the
`memory elements;” ........................................................ 96 
`[12.C] “at least one MLC nonvolatile memory
`element that can be mapped into the nonvolatile
`memory space;” ............................................................. 97 
`[12.D] “at least one SLC nonvolatile memory
`element that can be mapped into the nonvolatile
`memory space;” ............................................................. 97 
`
`c.
`
`d.
`
`e.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`
`
`
`
`Declaration of Dr. David Liu
`
`5
`
`Micron Ex. 1009, p. 5
`Micron v. Vervain
`IPR2021-01550
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`

`

`Declaration of Dr. David Liu
`
`f.
`
`g.
`
`h.
`
`[12.E] “at least one random access volatile
`memory;” ....................................................................... 97 
`[12.F] “the controller controlling access of the
`MLC and SLC nonvolatile memory elements and
`the random access volatile memory for storage of
`data therein, the controller, in at least a Write
`access operation to the MLC nonvolatile memory
`element, operable to store data in the MLC
`nonvolatile memory element and retain such stored
`data in the random access volatile memory;” ................ 97 
`[12.G] “the controller performing a data integrity
`test on stored data in the MLC nonvolatile memory
`element after at least a Write access operation
`performed thereon by comparing the stored data to
`the retained data in the random access volatile
`memory;” ....................................................................... 98 
`[12.H] “wherein the address table maps logical and
`physical addresses adaptable to the system,
`wherein the mapping is performed as necessitated
`by the system to maximize lifetime, and wherein
`the mapping maps blocks, pages, or bytes of data
`in either volatile or nonvolatile, or both, memories;
`and” ................................................................................ 98 
`[12.I] “wherein a failure of the data integrity test
`performed by the controller results in a remapping
`of the address space to a different physical range
`of addresses and transfer of data corresponding to
`the stored data to those remapped physical
`addresses from those determined to have failed the
`data integrity test to achieve enhanced endurance.” ...... 98 
`C. Ground 2: Dusija In View Of Sutardja And The Knowledge Of
`A POSA Renders Obvious Claim 10 ................................................. 98 
`1.
`Claim 10: “The system of claim 1, wherein the contents
`of frequently accessed portions of the memory space are
`periodically moved from the MLC space to the SLC
`space.” ...................................................................................... 99 
`2. Motivation to Combine .......................................................... 103 
`
`i.
`
`j.
`
`6
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`
`
`
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`Micron Ex. 1009, p. 6
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Declaration of Dr. David Liu
`
`
`X. OBJECTIVE INDICIA OF NON-OBVIOUSNESS .................................. 106 
`XI. DECLARATION ........................................................................................ 107 
`
`
`
`
`
`
`
`7
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`Micron Ex. 1009, p. 7
`Micron v. Vervain
`IPR2021-01550
`
`

`

`
`
`I.
`
`Declaration of Dr. David Liu
`
`I, Dr. David Liu, hereby declare as follows:
`
`INTRODUCTION
`1.
`I have been retained by Micron Technology, Inc. (“Micron”) as an
`
`independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office (“PTO”). I am not an employee of Micron or any affiliate
`
`or subsidiary of Micron.
`
`2.
`
`I have been asked to consider whether certain references teach or
`
`suggest the features recited in certain claims of U.S. Patent No. 10,950,300, which
`
`I refer to herein as the 300 Patent, and whether certain claims of the 300 Patent are
`
`unpatentable as obvious.
`
`3. My opinions and the bases for my opinions are set forth below.
`
`4.
`
`I am being compensated at $550 per hour for my work, plus
`
`reimbursement for any reasonable expenses. My compensation is based solely on
`
`the amount of time that I devote to activity related to this case and is in no way
`
`contingent on the nature of my findings, the presentation of my findings in
`
`testimony, or the outcome of this or any other proceeding. I have no other
`
`financial interest in this proceeding.
`
`II. EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS
`5. My curriculum vitae (“CV”) is attached hereto as Attachment A and
`
`provides an accurate identification of my background and experience. Among
`
`
`
`8
`
`Micron Ex. 1009, p. 8
`Micron v. Vervain
`IPR2021-01550
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`

`

`
`other things, my CV includes a list of my issued patents and publications for at
`
`Declaration of Dr. David Liu
`
`least the last 30 years. My curriculum vitae also includes information about my
`
`expert witness experience, with case numbers where available.
`
`6.
`
`I received a Bachelor of Science in Electrical Engineering from the
`
`University of California, Berkeley, in 1983. I received a Master of Science and
`
`Ph.D. degrees in Electrical Engineering from Stanford University in 1985 and
`
`1989, respectively.
`
`7.
`
`From 1989 to 1992, I was a member of technical staff at Texas
`
`Instruments, Inc. At Texas Instruments, my job responsibilities included process
`
`integration, device modeling, high-voltage CMOS process integration, and
`
`investigating novel source-side injection mechanisms for Flash EPROM channel
`
`hot-electron programming.
`
`8.
`
`From 1992 to 1995, I was a member of the technical staff at Advanced
`
`Micro Devices, Inc. (AMD) where I was a key contributor in optimizing Flash cell
`
`and periphery devices in AMD’s CMOS-based 0.5um and 0.35um Flash EPROM
`
`technology. My job responsibilities at AMD also included process integration,
`
`device modeling, and development of triple-well process technology for x-decoder
`
`transistors and high voltage transistors for negative gate erase operation. While at
`
`AMD, I was awarded a Spotlight Award for developing a method of manufacturing
`
`a self-aligned source (SAS) etch for a NOR flash memory.
`
`
`
`9
`
`Micron Ex. 1009, p. 9
`Micron v. Vervain
`IPR2021-01550
`
`

`

`
`
`Declaration of Dr. David Liu
`
`9.
`
`I spent the next five years of my career in managerial and director
`
`roles at several California-based semiconductor companies. I was responsible for
`
`increasing yield and for leading teams of engineers working to develop next-
`
`generation memory devices.
`
`10.
`
`In 2000, I co-founded Progressant Technologies in Fremont,
`
`California. Progressant Technologies developed IP for negative differential
`
`resistance transistor technology and was eventually acquired by Synopsys, Inc.
`
`11. From 2000 to 2004, I was a Senior Manager at Xilinx, Incorporated,
`
`where I was responsible for developing nonvolatile memory process technology
`
`for flash and CPLD product applications, as well as advanced CMOS process
`
`technology (specifically 75nm CMOS technology node, a half node version
`
`between 90nm and 65nm).
`
`12. From 2004 to 2007, I was a Senior Scientist at Maxim Integrated
`
`Products where I was responsible for developing Embedded Non-volatile Memory
`
`process technology for Power Management product applications.
`
`13. Since 2007, I have served as a technical consultant where I have
`
`provided expert advice regarding Flash memory technology, CMOS process
`
`technology, and semiconductor device physics.
`
`14.
`
`I am not now and have never been an employee of the Petitioner.
`
`
`
`10
`
`Micron Ex. 1009, p. 10
`Micron v. Vervain
`IPR2021-01550
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`

`

`
`III. ASSIGNMENT AND MATERIALS CONSIDERED
`15.
`I have been asked to provide analysis and explain the subject matter of
`
`Declaration of Dr. David Liu
`
`the 300 Patent, including the state of the art when the 300 Patent application was
`
`filed. I have also been asked to consider, analyze, and explain certain prior art to
`
`the 300 Patent including how that art relates to the challenged claims of the 300
`
`Patent and to provide my opinions regarding whether that art invalidates the
`
`claimed subject matter.
`
`16. The opinions expressed in this declaration are not exhaustive of my
`
`opinions regarding the unpatentability of the claims of the 300 Patent. Therefore,
`
`the fact that I do not address a particular point should not be understood to indicate
`
`an agreement on my part that any claim complies with the requirements of any
`
`applicable patent or other rule.
`
`17.
`
`I reserve the right to amend and supplement this declaration in light of
`
`additional evidence, arguments, or testimony presented during this IPR or related
`
`proceedings on the 300 Patent.
`
`18.
`
`In forming the opinions set forth in this declaration, I have considered
`
`and relied upon my education, knowledge of the relevant field, knowledge of
`
`scientific and engineering principles, and my experience. I have also reviewed and
`
`considered the 300 Patent (Exhibit 1007), its prosecution history (Exhibit 1008),
`
`and the following additional materials:
`
`
`
`11
`
`Micron Ex. 1009, p. 11
`Micron v. Vervain
`IPR2021-01550
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`

`

`Exhibit
`
`Description
`
`Declaration of Dr. David Liu
`
`1010
`
`1011
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`U.S. Patent Application Publication No. 2011/0099460
`(“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`Betty Prince, Semiconductor Memories – A Handbook of
`Design, Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617
`(“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
`
`U.S. Patent Application Publication No. 2011/0115192
`(“Y. Lee”)
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601
`(“Gavens”)
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition,
`2006, definition of periodic
`
`12
`
`
`
`
`
`Micron Ex. 1009, p. 12
`Micron v. Vervain
`IPR2021-01550
`
`

`

`Exhibit
`
`Description
`
`Declaration of Dr. David Liu
`
`1028
`
`1029
`
`1030
`
`1031
`
`1033
`
`1040
`
`1041
`
`1042
`
`1043
`
`1047
`
`1048
`
`1049
`
`1050
`
`1051
`
`1052
`
`U.S. Patent Application Publication No. 2010/0172180
`(“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650
`(“Chin”)
`
`European Patent Specification No. EP 2.291.746 B1 (“Radke”)
`
`U.S. Patent Application Publication No. 2006/0053246
`(“S. Lee”)
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002,
`definitions of static RAM and volatile memory
`
`U.S. Patent No. 5,936,971 (“Harari”)
`
`PCT Publication No. WO 03/027828 (“Gorobets WO”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of address space
`
`U.S. Patent Application Publication No. 2009/0300269
`(“Radke Appl.”)
`
`1053
`
`U.S. Patent No. 8,250,333 (“Gorobets II”)
`
`13
`
`
`
`
`
`Micron Ex. 1009, p. 13
`Micron v. Vervain
`IPR2021-01550
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`

`

`
`
`Exhibit
`
`Description
`
`Declaration of Dr. David Liu
`
`1054
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of firmware
`
`IV. UNDERSTANDING OF THE LAW
`19.
`I am not an attorney, but I have been instructed in and applied the law
`
`as described in this section.
`
`20.
`
`I understand that the first step in comparing an asserted claim to the
`
`prior art is for the claim to be properly construed. I address how a person of
`
`ordinary skill in the art would have understood the claims of the alleged invention
`
`in Section IX below.
`
`21.
`
`I have been further instructed and understand that a patent claim is
`
`unpatentable and invalid as obvious if the subject matter of the claim as a whole
`
`would have been obvious to a person of ordinary skill in the art of the claimed
`
`subject matter as of the time of the invention at issue. I understand that when
`
`assessing the obviousness of claimed subject matter, the following factors are
`
`evaluated: (1) the scope and content of the prior art; (2) the difference or
`
`differences between each claim of the patent and the prior art; and (3) the level of
`
`ordinary skill in the art at the time the patent was filed.
`
`22.
`
`I understand that claimed subject matter may be obvious in view of
`
`more than one item of prior art. I understand, however, that it is not enough to
`
`show simply that all the limitations of the claimed subject matter are spread
`14
`
`
`
`Micron Ex. 1009, p. 14
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`throughout the prior art. Instead, for claimed subject matter to be obvious over
`
`Declaration of Dr. David Liu
`
`multiple references, there must be some reason or motivation for one of ordinary
`
`skill in the art to combine the prior art references to arrive at the claimed subject
`
`matter.
`
`23.
`
`I have been informed that, in seeking to determine whether an
`
`invention that is a combination of known elements would have been obvious to a
`
`person of ordinary skill in the art at the time of the invention, one must consider
`
`the references in their entirety to ascertain whether the disclosures in those
`
`references render the combination obvious to such a person.
`
`24.
`
`I have been informed and understand that, while not required, the
`
`prior art references themselves may provide a teaching, suggestion, motivation, or
`
`reason to combine, but other times the motivation linking two or more prior art
`
`references is common sense to a person of ordinary skill in the art at the time of the
`
`invention.
`
`25.
`
`I understand that a particular combination may be proven obvious
`
`merely by showing that it was obvious to try the combination. I have been
`
`informed that, if a technique has been used to improve one device, and a person of
`
`ordinary skill in the art would recognize that it would improve similar devices in
`
`the same way, using the technique is obvious unless its actual application is
`
`beyond his or her skill.
`
`
`
`15
`
`Micron Ex. 1009, p. 15
`Micron v. Vervain
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`
`
`Declaration of Dr. David Liu
`
`26.
`
`I further understand that an obviousness analysis recognizes that
`
`market demand, rather than scientific literature, often drives innovation, and that a
`
`motivation to combine references also may be supplied by the direction of the
`
`marketplace. For example, when there is a design need or market pressure to solve
`
`a problem and there are a finite number of identified, predictable solutions, a
`
`person of ordinary skill has good reason to pursue the known options within his or
`
`her technical grasp because the result is likely the product not of innovation but of
`
`ordinary skill and common sense.
`
`27.
`
`I have been informed that the combination of familiar elements
`
`according to known methods is likely to be obvious when it does no more than
`
`yield predictable results. Thus, where all of the elements of a claim are used in
`
`substantially the same manner, in devices in the same field of endeavor, the claim
`
`is likely obvious.
`
`28. Additionally, I understand that a patent is likely to be invalid for
`
`obviousness if a person of ordinary skill can implement a predictable variation or if
`
`there existed at the time of the invention a known problem for which there was an
`
`obvious solution encompassed by the patent’s claims. Therefore, when a work is
`
`available in one field of endeavor, design incentives and other market forces can
`
`prompt variations of it, either in the same field or a different one.
`
`
`
`16
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`Micron Ex. 1009, p. 16
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`
`
`Declaration of Dr. David Liu
`
`29.
`
`I further understand that combining embodiments related to each other
`
`in a single prior art reference would not ordinarily require a leap of inventiveness.
`
`30.
`
`I also understand that one of ordinary skill in the art must have had a
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`reasonable expectation of success when combining references for claimed subject
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`matter to be obvious.
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`31.
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`I have been informed and I understand that factors referred to as
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`“objective indicia of non-obviousness” or “secondary considerations” are also to
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`be considered when assessing obviousness when such evidence is available. I
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`understand that these factors can include: (1) commercial success; (2) long-felt but
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`unresolved needs; (3) copying of the invention by others in the field; (4) initial
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`expressions of disbelief by experts in the field; (5) failure of others to solve the
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`problem the claimed subject matter solved; and (6) unexpected results.
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`32.
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`I also understand that evidence of objective indicia of non-
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`obviousness must be commensurate in scope with the claimed subject matter. I
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`further understand that there must be a relationship, sometimes referred to as a
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`“nexus,” between any such secondary indicia and the claimed invention.
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`33. Finally, I have been informed that one cannot use hindsight to
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`determine that an invention was obvious.
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`34.
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`I provide my opinions in this declaration based on the guidelines set
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`forth above.
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`V. LEVEL OF SKILL IN THE ART
`35.
`I have been informed and understand that the level of ordinary skill in
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`Declaration of Dr. David Liu
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`the relevant art at the time of the invention is relevant to inquiries such as the
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`meaning of claim terms, the meaning of disclosures found in the prior art, and the
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`reasons one of ordinary skill in the art may have for combining references.
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`36.
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`I have been informed and understand that factors that may be
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`considered in determining the level of ordinary skill include: (1) the education of
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`the inventor; (2) the type of problems encountered in the art; (3) prior art solutions
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`to those problems; (4) rapidity with which innovations are made; (5) sophistication
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`of the technology; and (6) education level of active workers in the relevant field. I
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`have been further informed and understand that a person of ordinary skill in the art
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`is also a person of ordinary creativity.
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`37. A person of ordinary skill in the art (“POSA”) at the time of the
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`alleged invention would have had at least a Bachelor of Science degree in electrical
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`engineering, computer engineering, or a closely related field, along with at least 3-
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`5 years of experience designing non-volatile memory devices. An individual with
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`an advanced degree in a relevant field would require less experience designing
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`non-volatile memory devices.
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`38.
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`In view of my educational background (e.g., a Ph.D. in Electrical
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`Engineering obtained in 1989) and decades of experience designing of non-volatile
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`
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`18
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`memories, as discussed in Section II, I was a person of more than the ordinary
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`Declaration of Dr. David Liu
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`level of skill in the art as of July 2011. My opinions herein, however, were formed
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`considering the perspective of an ordinarily skilled artisan.
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`VI. THE 300 PATENT’S EFFECTIVE FILING DATE
`39.
`I understand that the application leading to the 300 Patent was filed on
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`June 12, 2018.
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`40. Based on my review of the 300 Patent, I note that it also refers to a
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`July 19, 2011 Provisional Application.
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`41. For purposes of this declaration, I have been instructed to use July 19,
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`2011 as the effective filing date of the 300 Patent. My opinions in this declaration
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`were formed from the perspective of a person of ordinary skill in the art as of July
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`19, 2011, including both the knowledge of a person or ordinary skill in the art at
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`that time as well as how a person of ordinary skill in the art would have understood
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`the prior art.
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`VII. THE 300 PATENT
`A. Technological Background
`1.
`Volatile, Non-volatile, and Flash Memory
`42. Computer system memory comes in several varieties. Generally,
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`computer memories store data (e.g., programs and user data) in what is known as
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`“binary” code, i.e., zeros and ones. In one of the simplest forms of memory, a
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`certain number of electrons may be stored on a capacitor to represent a binary 0
`19
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`while a different number represents a binary 1. The number of electrons will
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`Declaration of Dr. David Liu
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`manifest themselves either as a distinct voltage level or current level that can be
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`obtained from the capacitor.
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`43. Memory may either be “volatile” or “non-volatile.” Volatile memory,
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`such as dynamic random access memory (DRAM), needs continuous power to
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`preserve stored data. That is, volatile memory loses its contents when the
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`computer’s power is turned off. Non-volatile memory (sometimes called NVM or
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`NV memory), such as Flash memory and disk drive storage, maintains its contents
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`when power is turned off. Unlike volatile memory, non-volatile storage does not
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`require a continuous availability of power in order to retain its data. See Ex. 1040,
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`Dipert & Levy at 21.
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`44. Flash memory has been a known memory type for several decades. It
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`is often found in USB flash drives, MP3 players, digital cameras, digital phones,
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`and more recently, in personal computers and servers. See Ex. 1018, Axelson at
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`17-18, 22-23. One early type of flash memory was known as electrically erasable
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`programmable read only memory (“EEPROM”). Flash has the advantage of being
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`a non-volatile memory, while also being able to be made smaller than traditional
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`non-volatile storage, e.g., disk drives. In addition, unlike disk drives, flash
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`memories do not have mechanical moving parts and thus are more able to
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`withstand sudden movement, making them better suited for portable devices.
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`
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`20
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`Declaration of Dr. David Liu
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`45. As shown below, many flash memory cells use floating gate
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`transistors to store information. Ex. 1014, Prince at 54-55.
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`
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`46. Other flash memory cells use what is known as “charge trap”
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`technology, which is a distinct but similar technology for storing charge in a flash
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`memory cell. Ex. 1019, Micheloni at 115. In both floating gate and charge trap
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`flash memory cells, the amount of charge stored in the cell represents information.
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`For example, a large amount of charge may represent a value of “0,” whereas a
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`small amount of charge may represent a value of “1.” Id. at 20.
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`2.
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`Programming Flash, and SLC and MLC Flash Memory
`Cells
`47. The charge on the floating gate indicates the value that the cell stores
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`by affecting the threshold voltage of the memory cell. The threshold voltage of the
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`memory cell refers to the voltage at which the transistor will begin to conduct
`
`
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`21
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`substantial current across the channel. As described below, the threshold voltage
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`Declaration of Dr. David Liu
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`can be set such that the cell stores two values, i.e., either a 0 or 1 (single-level cell,
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`“SLC”) or such that the cell stores more than two values (multi-level cell, “MLC”).
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`For example, a multi-level cell may sto