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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_____________
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`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`VERVAIN, LLC,
`Patent Owner
`_____________
`
`Case: IPR2021-01550
`U.S. Patent No. 10,950,300
`_____________
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`PATENT OWNER’S SUR-REPLY
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`IPR2021-01550
`U.S. Patent No. 10,950,300
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`
`CONTENTS
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`I.
`
`II.
`
`A.
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`
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`
`
`B.
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`C.
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`D.
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`E.
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`F.
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`INTRODUCTION ......................................................................................... 1
`
`THE CITED PRIOR ART DOES NOT RENDER THE
`CHALLENGED CLAIMS UNPATENTABLE .......................................... 1
`
`PETITIONER’S FOUR-LINE ANALYSIS FOR LIMITATION [1.E] IS
`DEFICIENT. .................................................................................................. 2
`
`PETITIONER’S LIMITATION [1.E] ANALYSIS IS UNCLEAR. ......... 2
`
`PETITIONER HAS NOT ESTABLISHED THAT A POSITA WOULD
`HAVE SOUGHT TO MAKE THE PROPOSED OBVIOUSNESS
`MODIFICATION. ......................................................................................... 9
`
`PETITIONER IGNORES THAT DUSIJA’S PREFERRED
`EMBODIMENT INCLUDES A FLASH CACHE. ..................................15
`
`PETITIONER’S ANALYSIS FOR LIMITATION [1.G.2] IS
`DEFICIENT. ................................................................................................18
`
`PETITIONER’S ANALYSIS FOR LIMITATION [1.H] IS
`DEFICIENT. ................................................................................................19
`
`PETITIONER’S ANALYSIS FOR INDEPENDENT CLAIM 12 IS
`DEFICIENT. ................................................................................................20
`
`PETITIONER’S ANALYSIS FOR DEPENDENT CLAIMS 2-9 AND 11
`IS DEFICIENT. ...........................................................................................21
`
`PETITIONER’S ANALYSIS IN GROUND 2 REGARDING CLAIM 10
`IS DEFICIENT. ...........................................................................................21
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`III. PETITIONER’S EXPERT IS NOT CREDIBLE .....................................21
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`IV. CONCLUSION ............................................................................................25
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`i
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`IPR2021-01550
`U.S. Patent No. 10,950,300
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`
`TABLE OF AUTHORITIES
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` Page(s)
`
`Cases
`
`Amazon Web Services, Inc. v. Saint Regis Mohawk Tribe,
`IPR2019-00103, Paper No. 22 (PTAB May 10, 2019) ........................................ 4
`
`Corning Inc. v. Danjou’s DSM IP Assets B.V.,
`Case No. IPR2013-00043, Paper No. 95 (PTAB May 1, 2014) ........................... 4
`
`Fantasia Trading LLC v. Cognipower, LLC,
`No. IPR2021-00071, 2022 WL 1616533 (PTAB. May 11, 2022) ..................... 23
`
`Intelligent Bio-Systems, Inc. v. Illumina Cambridge, Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) ................................................................ 5, 12, 14
`
`Liberty Mutual Ins. Co. v. Progressive Casualty Ins. Co.,
`CBM2012-00003, Paper No. 8 (PTAB Oct. 25, 2012) ........................................ 5
`
`Ultratec, Inc. v. CaptionCall, LLC,
`872 F.3d 1267 (Fed. Cir. 2017) .......................................................................... 23
`
`Xilinx, Inc. v. Analog Devices, Inc.,
`No. IPR2020-01564, 2022 WL 947004 (PTAB Mar. 11, 2022) ........................ 24
`
`Statutes
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`35 U.S.C. §§ 314(a), 316(e) ....................................................................................... 9
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`ii
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`
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`Exhibit
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`EXHIBIT LIST
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`Description
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`Ex. 2001 Declaration of Dr. Sunil Khatri
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`IPR2021-01550
`U.S. Patent No. 10,950,300
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`
`Previously
`Submitted
`X
`
`Ex. 2002 Chen et al., Ultra MLC Technology Introduction,
`Advantech Technical White Paper (Oct. 5, 2012)
`(“Chen”)
`
`Ex. 2003 Excerpts from Micheloni et al., Inside NAND Flash
`Memories (1st ed. 2010) (“Micheloni”)
`
`Ex. 2004 Intentionally omitted
`
`Ex. 2005 Microsoft Computer Dictionary definition for “data
`integrity”
`
`Ex. 2006 Hargrave’s Communications Dictionary definition for
`“data integrity”
`
`Ex. 2007 https://www.law360.com/articles/1381597/albright-says-
`he-ll-very-rarely-put-cases-on-hold-for-ptab
`
`Ex. 2008 Docket Sheet for Case. No. 6:21-cv-487-ADA; Vervain v.
`Micron Technology et al.; U.S. District Court, Western
`District of Texas.
`
`Ex. 2009 Exhibit D-3, Invalidity Claim Chart for the ’300 Patent
`based on U.S. Patent Application Pub. No. 2011/0099460
`(“Dusija”)
`
`Ex. 2010 Exhibit D-18, Invalidity Claim Chart for the ’300 Patent
`based on U.S. Patent Application Pub. No. US
`2008/0140918 (“Sutardja”)
`
`Ex. 2011 Intentionally omitted
`
`Ex. 2012 Claim Construction Order in Vervain v. Micron Tech.,
`Inc., No. 6:21-cv-487-ADA (W.D. Tex.) and Vervain v.
`Western Digital Corp., No. 6:21-cv-488-ADA (W.D.
`
`iii
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`X
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`X
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`X
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`X
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`X
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`X
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`X
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`X
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`X
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`
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`IPR2021-01550
`U.S. Patent No. 10,950,300
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`Tex.) (Jan. 24, 2022)
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`Ex. 2013 Micron’s Preliminary Invalidity Contentions for U.S.
`Patent Nos. 8,891,298; 9,196,385; 9,997,240; and
`10,950,300; Case. No. 6:21-cv-487-ADA; Vervain v.
`Micron Technology et al.; U.S. District Court, Western
`District of Texas.
`
`Ex. 2014 Declaration of Dr. Sunil Khatri in Support of Patent
`Owner’s Response
`
`Ex. 2015 Transcript of June 10, 2022 Deposition of Dr. David Liu
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`Ex. 2016 Intentionally omitted
`
`Ex. 2017 U.S. Patent No. 5,721,862
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`Ex. 2018 Intentionally omitted
`
`Ex. 2019 U.S. Patent No. 5,535,399
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`Ex. 2020 Transcript of November 3, 2022 Deposition of Dr. David
`Liu
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`X
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`X
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`X
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`X
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`X
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`X
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`X
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`iv
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`IPR2021-01550
`U.S. Patent No. 10,950,300
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`I.
`
`INTRODUCTION
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`Pursuant to the Board’s Scheduling Order (Paper No. 12) and the parties’ joint
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`Notice of Stipulation to Change to Due Dates 2 and 3 (Paper No. 20), Patent Owner
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`Vervain, LLC (“Patent Owner” or “PO”) files this Sur-Reply. In its Reply (Paper
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`No. 21), Micron (“Petitioner”) sidesteps Dusija’s clear statements regarding the
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`undesirability of placing its cache outside the flash memory of Dusija’s system in a
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`manner such as that proposed by Petitioner. This presents a fatal impediment to the
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`Petition’s (Paper No. 1) analysis for limitation [1.E] of the challenged patent, which
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`carries through to deficiencies in the Petition for limitations [1.G.2] and [1.H], too.
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`Petitioner makes various arguments that essentially amount to ignoring and/or
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`discrediting the disclosure of Dusija—the prior art reference that Petitioner itself
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`chose. Petitioner’s arguments do not establish by a preponderance of the evidence
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`that the challenged claims (claims 1-12) are unpatentable. Further, the deposition
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`testimony of Petitioner’s expert indicates that he is not credible, and the Board
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`should give his opinions little or no weight. The Board should confirm the
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`patentability of the challenged claims.
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`II. THE CITED PRIOR ART DOES NOT RENDER THE
`CHALLENGED CLAIMS UNPATENTABLE
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`PO explained in its Response (Paper No. 16, “Response”) that the Petition is
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`flawed in several respects, primarily stemming from its deficient analysis for
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`1
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`limitation [1.E]. In its Reply, Petitioner makes various scattered arguments, mainly
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`regarding limitation [1.E]. The Reply attempts to clean up the Petition’s mess,
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`largely by impermissibly adding new arguments (as discussed below in Section III).
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`But as explained below, Petitioner’s Reply does not change that Petitioner has failed
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`to meet its burden regarding the “random access volatile memory” limitation that is
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`first introduced in limitation [1.E] and then recited in limitations [1.G.2] and [1.H].
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`A.
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`Petitioner’s Four-Line Analysis for Limitation [1.E] is Deficient.
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`Below, Petitioner addresses various arguments that the Reply makes
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`regarding limitation [1.E]—and which were notably not made in the Petition—and
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`it is evident that the Petition is deficient with respect to this limitation. As explained
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`below in Sections II.B-C, such deficiencies regarding limitation [1.E] propagate to
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`limitations [1.G.2] and [1.H]. In the following subsections, PO notes various
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`problems with Petitioner’s effort to salvage the Petition’s faulty analysis of
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`limitation [1.E].
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`
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`Petitioner’s Limitation [1.E] Analysis is Unclear.
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`It is unsurprising that Petitioners devoted so much space in their Reply—
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`nearly twenty pages—to claim limitation [1.E]. Reply, 3-22. That is because the
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`Petition’s analysis (or lack thereof) regarding the “at least one random access volatile
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`memory” recited in limitation [1.E] is deeply flawed, as PO explained in its
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`Response. Response, 33-47. But what is surprising is that Petitioner devoted so
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`2
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`little attention to that limitation in the Petition—a miniscule four lines. Specifically,
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`Petitioner’s limitation [1.E] discussion consists of the following:
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`As discussed above, Dusija discloses or renders obvious “[a]
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`system comprising . . . at least one random access volatile
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`memory.” See limitation [1.A.1] (describing that Dusija would
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`have been understood, or it would have been obvious, for its
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`controller to include RAM and for its cache to be RAM). Liu
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`Decl., ¶ 158.
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`Petition, 42.
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`Thus, for limitation [1.E], instead of providing any substantive analysis, the
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`Petition merely provides a conclusory sentence, a citation to an earlier claim
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`limitation that does not even recite “random access volatile memory” (limitation
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`[1.A.1] recites “memory space containing volatile memory space and nonvolatile
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`memory space,” see Petition, 33, and a parenthetical. In leading off its Reply with
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`an argument that “PO’s Objections to the Specificity of the Petition Lack Merit”
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`(Reply, 3), Petitioner points to the Petition’s statement that “it would have been
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`obvious to employ Dusija’s controller with RAM and [to] implement Dusija’s cache
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`as RAM” as allegedly providing a “clear mapping” of the claims (Reply, 3-4), but
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`even that statement does not actually appear in the Petition’s section regarding
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`limitation [1.E].
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`3
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`Thus, the Petition is forcing the Board to “play archaeologist,” to go back to
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`the Petition’s discussion of an earlier limitation (that does not contain the same
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`language as limitation [1.E]) to figure out what mapping Petitioner might intend for
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`limitation [1.E]. Such a cursory treatment of limitation [1.E] is insufficiently clear.
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`See Corning Inc. v. Danjou’s DSM IP Assets B.V., Case No. IPR2013-00043, Paper
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`No. 95 at 13 (PTAB May 1, 2014) (citing the 7th Circuit’s statement that “[a] brief
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`must make all arguments accessible to the judges, rather than ask them to play
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`archaeologist with the record.”); Amazon Web Services, Inc. v. Saint Regis Mohawk
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`Tribe, IPR2019-00103, Paper No. 22 at 17 (PTAB May 10, 2019) (“By failing to
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`address whether Lange teaches [various features], Petitioner has placed the burden
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`on the Board to ascertain how the prior art allegedly reads on the challenged
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`claims—a task we do not undertake.”); see also id. (“The burden is on Petitioner,
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`not the Board, to specify with particularity how Lange teaches [various claimed
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`features].”).
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`The Reply states that “PO contends that Petitioner has not sufficiently
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`identified the location of the ‘random access volatile memory’” and “[i]n making
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`this argument, PO attacks a straw man, because the claims do not require the random
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`access volatile memory to be in any specific location.” Reply, 3. But Petitioner
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`ignores that PO made the foregoing statements in the context of arguing that
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`Petitioner’s mapping and analysis are
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`insufficiently clear.
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` Petitioner’s
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`4
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`characterization of PO’s argument as a straw man is inapt because regardless of
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`whether the claims recite a specific location, the Petition’s mapping and analysis
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`require clarity, and the vagueness of Petitioner’s limitation [1.e] analysis is a defect
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`of the Petition.1 See Liberty Mutual Ins. Co. v. Progressive Casualty Ins. Co.,
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`CBM2012-00003, Paper No. 8 at 10 (PTAB Oct. 25, 2012) (stating that the Board
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`is required to “address only the basis, rationale, and reasoning put forth by the
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`Petitioner in the petition, and resolve all vagueness and ambiguity in Petitioner’s
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`arguments against the Petitioner”). Moreover, to the extent Petitioner is relying on
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`obviousness for limitation [1.E], PO’s observations about the lack of clarity provided
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`by Petitioner and its declarant regarding the location of the “random access volatile
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`memory” in the proposed obviousness implementation are indeed relevant because
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`such observations address the need for Petitioner to have demonstrated (which it has
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`not done) a reasonable expectation of success regarding its obviousness
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`implementation. Response, 2.
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`1 Petitioner additionally makes an argument that claim 3 supports Petitioner’s
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`position, but that is a new argument not previously presented in the Petition. Reply,
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`3. Intelligent Bio-Systems, Inc. v. Illumina Cambridge, Ltd., 821 F.3d 1359, 1366,
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`1369-71 (Fed. Cir. 2016).
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`5
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` As noted above, the Petition is exceedingly vague as to the mapping for
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`limitation [1.E], deferring to its discussion of a different limitation [1.A.1]. And at
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`its discussion of limitation [1.A.1], the Petition still leaves unclear what exactly is
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`being relied upon for limitation [1.E]. As noted in the Reply, there are two different
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`relevant components—a controller (which Dusija discloses as being outside of flash
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`memory), and a cache (which Dusija discloses as being in the flash memory). Reply,
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`4-5; Ex. 1010, FIGS. 16A-16C. But that still leaves the open the questions: does
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`Petitioner’s obviousness modification involve adding a cache (e.g., that implements
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`cache-related functionality disclosed in Dusija) at the controller (in which case there
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`would be two caches, seemingly redundantly)? Does the obviousness modification
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`instead involve replacing Dusija’s flash-based cache with one located at the
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`controller (or in other words, moving Dusija’s flash-based cache to be outside of
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`flash memory)? The Petition (apparently at its discussion of limitation [1.A.1],
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`because there is no analysis regarding this for limitation [1.E]) is unclear on these
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`points, and so was Dr. Liu in deposition. Ex. 2015, 87:6-88:11.
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`The Reply states that “Petitioner’s theory is simple: it would have been
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`obvious to modify Dusija to add a RAM cache at the controller (i.e., use the
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`conventional controller’s RAM to implement the cache).” Reply, 4. The Petition
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`(which is where all of Petitioner’s arguments are to have been made, and with
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`appropriate clarity) does not set forth Petitioner’s theory “simp[ly].” Moreover, if
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`6
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`Petitioner truly wished to get across its “simple” theory, it should have done so in
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`the Petition’s section regarding limitation [1.E].
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`In any event, to the extent Petitioner is now streamlining its obviousness
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`theory to be about “add[ing]” a RAM cache in a manner that leaves in place Dusija’s
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`existing cache, Petitioner has not adequately explained why a person of ordinary
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`skill in the art (POSITA) would have implemented two caches, particularly, when
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`(as discussed below) Dusija explicitly states that locating its cache outside of flash
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`memory is undesirable.2 To the extent Petitioner contends that the RAM cache is
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`added as a replacement for Dusija’s flash-based cache (i.e., with Petitioner’s
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`obviousness implementation moving the cache to be outside of the flash memory),
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`Petitioner has not adequately established why a POSITA would have sought to do
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`so against the guidance of Dusija. To the extent Petitioner contends that flash-based
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`caching is only disclosed in the context of an “alternative” embodiment Dusija
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`(Petition, 33 n.6), that is incorrect—paragraph [0131] of Dusija clearly discloses that
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`2 Dr. Khatri, when asked at his deposition to explain his position on Figure 16 of
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`Dusija (Ex. 1060, 145:9-153:18), explained that Petitioner’s positioning of the cache
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`outside of flash memory would result in an additional delay of one T (duration of
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`toggling of data from the flash chip to the off-chip cache) in the best case and two
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`Ts in the worst case, compared to Dusija’s approach (id., 151:22–153:7).
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`7
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`its “preferred” embodiment includes caching. And to the extent Petitioner contends
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`that Dusija’s silence on the location of a cache in the context of Dusija’s discussion
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`of FIGS. 14A-14B means that the cache is in RAM, that is incorrect because Dusija
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`only mentions RAM a single time—in its background section, where RAM is
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`contrasted with the teaching of Dusija’s disclosure. Ex. 1010, ¶[0003]. Dusija could
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`have described a cache in the context of FIGS. 14A-14B as being in RAM, but did
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`not do so. Instead, Dusija clearly describes its cache as being a flash cache.
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`PO in its Petition addressed two mappings out of an abundance of caution.
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`Petitioner’s argument that the Preliminary Response (Paper No. 9) does not address
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`two mappings is of no consequence (Reply, 5-6), because this IPR trial only began
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`with the institution decision, and PO is entitled to make different arguments in its
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`Response than its Preliminary Response. Similarly, the institution decision is not
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`the end of the story as Petitioner apparently suggests (Reply, 6), but rather the
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`beginning. Even if Petitioner only intended to have one mapping (instead of two
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`mappings) in the Petition for limitation [1.E] (actually, at limitation [1.A.1] but
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`apparently incorporated into the limitation [1.E] analysis in an unclear manner), that
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`still does not cure the Petition’s failure to establish motivation to modify Dusija to
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`implement limitation [1.E]. Petitioner has not adequately rebutted PO’s arguments
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`(from the Response) that a POSITA would not have sought to implement a cache
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`8
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`outside of Dusija’s flash memory—in particular, at Dusija’s controller—as
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`explained below.
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`
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`Petitioner Has Not Established That a POSITA Would
`Have Sought to Make the Proposed Obviousness
`Modification.
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`Petitioner presents several arguments in its Reply about its obviousness
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`theory, but has not established that a POSITA would have implemented Petitioner’s
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`proposed obviousness modification of Dusija’s system. Many of Petitioner’s
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`arguments are misleading strawman arguments that deflect from the proper inquiry
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`and/or mischaracterize PO’s arguments.
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`Petitioner states that “[t]he POR’s core argument—that a POSA would not
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`have been motivated to use a RAM cache with Dusija’s controller—was already
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`considered and rejected by the Board in its ID.” Reply, 6. But that statement is
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`irrelevant, because similar to the fallacy noted above, Petitioner incorrectly assumes
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`the institution decision is dispositive. There are different standards of proof at the
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`institution stage versus the final written decision stage—reasonable likelihood of
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`success at the former, preponderance of the evidence at the latter. 35 U.S.C. §§
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`314(a), 316(e).
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`Petitioner discusses various statements made by the Board in the institution
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`decision (Reply, 7-8), including the Board’s statement that “one of ordinary skill in
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`the art would have been motivated to add RAM to Dusija’s controller to perform
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`9
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`data integrity tests.” Id., 8. But the relevant issue is not merely about adding RAM
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`in general—Petitioner has specifically proposed an “implement[ation] [of] Dusija’s
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`cache as RAM,” which would fundamentally change how Dusija would work
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`regarding usage of a cache. Response, 46 (citing Petition, 36, emphasis added). And
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`as explained in the Response, Petitioner’s proposed obviousness implementation
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`would detract from the performance of Dusija’s system. Response, 46 (citing Ex.
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`2014, ¶84); Ex. 1060, 145:9-153:18 (discussed above in footnote 2).
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`Instead of addressing these points head-on, Petitioner mischaracterized PO’s
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`arguments for limitation [1.E] as being about teaching away. Reply, 6-22 (section
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`of Reply under the header “The POR’s Teaching-Away Argument Lacks Merit”);
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`see also id., 13 (“PO’s teaching-away argument fails…”), 14 (“PO argues that Dusija
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`teaches away…”). PO’s Response explains for limitation [1.G.2] that Petitioner’s
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`obviousness modification is counseled against by Dusija (Response, 52), and further
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`explains for limitation [1.H] that Dusija expressly teaches away from Petitioner’s
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`proposed modification, id., 54-57, but PO did not set forth a teaching-away argument
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`for limitation [1.E]. Id., 33-37. Rather, PO explained for limitation [1.E] that a
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`POSITA would not have sought to move Dusija’s cache to be outside of flash
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`memory (Response, 43-46), but did not argue teaching-away per se. Thus, the
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`section of the Reply on which Petitioner spends most of its pages for limitation [1.E]
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`misunderstands and/or mischaracterizes PO’s arguments.
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`10
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`The Reply states that “Dusija expressly discloses embodiments in which
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`toggling and rewrites are required, contradicting the notion that avoiding these steps
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`is ‘fundamental’ to Dusija.” Reply, 11. But PO did not argue that merely avoiding
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`toggles/rewrites is the fundamental aspect of Dusija—rather, PO mentioned the
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`“fundamental principle of Dusija’s operation with respect to cache usage,” i.e., how
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`Dusija uses its cache to achieve certain functionality. Response, 43; see also id., 46
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`(“change the fundamental principle of Dusija’s operation with respect to using the
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`cache (e.g., unnecessarily move the cache outside the flash memory in which it is
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`conveniently situated according to Dusija)”). And Petitioner’s statement that
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`“Dusija never characterizes avoiding toggling as ‘fundamental’” (Reply, 18)
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`mischaracterizes PO’s argument. PO’s point is not that Dusija actually uses the word
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`“fundamental.” Similarly, Petitioner states that “Dusija does not characterize
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`avoiding a rewrite of data when excessive error bits are detected as ‘fundamental’”
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`(id., 19). That statement, too, ignores that (1) Dusija does not need to actually use
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`the word “fundamental”; and (2) PO’s point is not that avoiding rewrites is the
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`fundamental aspect of Dusija; rather, it is performing caching in the manner
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`described in Dusija (namely, in flash memory).
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`According to Petitioner, “nowhere does Dusija state that the alternative—that
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`is, making the comparison at the controller—would not work.” Id., 17. But that is
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`yet another a strawman argument. Petitioner is setting up an extreme standard—
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`11
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`asking whether Dusija states that performing the comparison at the controller
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`(something Dusija does not teach) would not work—and then knocking that down
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`and claiming victory. But inoperability is not required for PO to prevail on its
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`argument regarding no motivation to modify Dusija. PO’s Response adequately
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`addresses the performance degradation that Dusija explicitly mentions. See, e.g.,
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`Response, 44-46; supra n.2. Petitioner states that that “the proposed combination
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`would equally, if not more so, improve reliability.” Reply, 18. But Dusija does not
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`disclose that reliability is a countervailing consideration that somehow turns
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`Petitioner’s proposed modification (which Dusija actually criticizes, Ex. 1010,
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`¶[0136]) into something desirable, and thus Petitioner apparently gives more weight
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`to a speculative consideration not disclosed in Dusija than a clear warning actually
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`disclosed in Dusija. Moreover, Petitioner’s argument about reliability is an
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`impermissible new argument. Intelligent Bio-Systems, 821 F.3d at 1366.
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`Similarly, Petitioner states that “PO fails to acknowledge the many drawbacks
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`of a flash memory cache.” Reply, 20. Petitioner misses the point. PO has noted in
`
`its Response what Dusija itself—Petitioner’s chosen reference—decided to devote
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`ink to. Dusija presumably found it necessary and/or relevant to discuss performance
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`degradation when explaining why not to move Dusija’s comparison (involving
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`cached data) outside the flash memory chip. Petitioner, with its foregoing statement,
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`seeks to distract from what Dusija actually discloses. Incredibly, Petitioner is now
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`12
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`arguing that Dusija’s own usage of flash cache is bad—despite that being the focal
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`point of Dusija’s disclosure, and described in great detail in Dusija’s figures and text.
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`For example, Petitioner states that “a POSA would have known that a flash memory
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`cache would lead to slower performance than a RAM cache.” Reply, 21. But that
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`ignores, and is counter to, Dusija’s explicit guidance that performing comparisons
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`regarding cached data at the controller (where Petitioner contends the RAM cache
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`is situated in Petitioner’s obviousness implementation) is undesirable due to
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`performance reasons. Ex. 1010, ¶[0136]; see also Ex. 2014, ¶¶83, 91, 97 (Dr. Khatri
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`discussing Dusija’s disclosures of data transfer sizes in chips being 64k or greater,
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`which would result in much performance degradation if transfers were incurred
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`between RAM of Petitioner’s proposed implementation and the flash memory chip).
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`Similarly, Petitioner states that “the use of a flash memory cache in Dusija would
`
`lead to greater cost and complexity” (Reply, 21) and “a POSA would have
`
`recognized a performance disadvantage in putting the comparison logic on a flash
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`memory chip” (id., 22). But Petitioner ignores that Dusija is already doing precisely
`
`those things. Petitioner’s attempts to denigrate its own chosen reference should be
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`rejected.
`
`Petitioner states that PO’s argument that the proposed obviousness
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`modification set forth in the Petition would require “an additional component (a
`
`RAM separate from flash memory)” (Petition, 45) “is incorrect because a POSA
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`13
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`would have understood Dusija’s controller to have RAM.” The Petition mentions a
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`RAM cache, Petition, 33 n.6, and Dusija simply does not disclose a RAM cache—
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`and only mentions RAM once, at its background section, where Dusija contrasts
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`RAM with Dusija’s disclosure. Ex. 1010, ¶[0003]. Petitioner’s argument that “[a]
`
`POSA would have recognized that Dusija’s controller already had RAM, at least
`
`because RAM was the standard way to implement other of Dusija’s functions”
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`(Reply, 16-17) is incorrect, because even if RAM was the “standard” way, that does
`
`not mean that Dusija’s controller necessarily includes RAM. In any event, PO also
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`explained that Petitioner’s proposed modification would unnecessarily and
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`unreasonably require an additional processing step (some mechanism to transfer the
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`cached data to the flash memory), Response, 45, and Petitioner’s Reply has not
`
`addressed that point.
`
`Petitioner states that “the challenged patent never suggests any unpredictable
`
`result from the use of a RAM cache.” Reply, 13. First, that is a new argument
`
`improperly raised in the Reply. Intelligent Bio-Systems, 821 F.3d at 1366. Second,
`
`claim 1 describes various functionality (in the context of, e.g., limitations [1.G.2]
`
`and [1.H]) that have to be performed, and under Petitioner’s proposed modification
`
`such functionality would have to be performed by the RAM cache of the modified
`
`Dusija system. But as PO explained for limitations [1.G.2] and [1.H], Dusija
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`provides explicit guidance that such functionality is not desirably implemented at a
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`14
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`cache outside flash memory. Petitioner only makes the foregoing statement
`
`regarding limitation [1.E] and not regarding limitations [1.G.2] and [1.H].
`
`
`
`Petitioner Ignores that Dusija’s Preferred Embodiment
`Includes a Flash Cache.
`
`In its Petition and Reply, Petitioner makes a series of incorrect statements and
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`unjustified logical leaps regarding Dusija’s disclosure of caching. For example, the
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`Petition states:
`
`Dusija states that its “cache” could be, “[i]n an alternative
`
`embodiment,” flash memory (what Dusija calls the “first
`
`portion). Dusija, [0020]. This only reinforces that the primary
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`embodiments (not “alternative”) would be understood to employ
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`a RAM cache and certainly does not act to limit the claim scope.
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`Petition, 33 n.6.
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`But Petitioner ignores that Dusija clearly states that:
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`In the preferred embodiment, the first portion [of a flash memory
`
`array, described at paragraph [0130] of Dusija] is further
`
`provided with a first section and a second section. The incoming
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`data is cached in the first section of the first portion and a first
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`copy of the data is written to the second portion.
`
`Ex. 1010, ¶[0131]; see also id., ¶[0021] (same).
`
`Therefore, when Petitioner points to Dusija’s caching as being in an
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`“alternative embodiment” and argues that such disclosure “strongly suggests that
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`there is at least one embodiment in which the ‘first portion’ is not used for the cache”
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`15
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`(Reply, 16), Petitioner is missing or ignoring the clear teaching of Dusija that flash-
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`based caching is also part of Dusija’s preferred embodiment.3 The Reply does not
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`even acknowledge this teaching of Dusija. Indeed, the Reply cites paragraph [0131]
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`exactly once—at page 14—but even there mischaracterizes Dusija by mentioning in
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`a parenthetical only an “alternative embodiment” and not what paragraph [0131]
`
`discloses about “the preferred embodiment.” Accordingly, Petitioner’s arguments
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`regarding Dusija allegedly disclosing RAM-based caching should be rejected.
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`Notably, the Reply does not mention Dr. Liu’s puzzling deposition testimony about
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`a “preferred embodiment within the alternative embodiment”—which is not
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`particularly surprising, because that testimony confirmed that Petitioner’s entire
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`embodiment-focused analysis about Dusija’s caching rests on an untenable
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`foundation. Ex. 2015, 45:13-46:6, 61:21-63:1 (emphasis added); see also id., 64:17-
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`65:6; Response, 39-42; infra Section III.
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`Moreover, Petitioner’s statement that “Dusija’s silence as to the location of
`
`the cache in Figures 14A-14B suggests that the cache is not in flash memory” is far-
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`fetched. Reply, 15 (emphasis in original). Indeed, Dusija is silent as to the location
`
`
`3 The Reply states that “[e]ven Dr. Khatri admitted as much,” Reply, 16, but Dr.
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`Khatri merely stated that there is no description of the first portion being labeled a
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`cache. Ex. 1060, 129:11-20.
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`16
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`of its cache in Figures 14A-14B, and as Dr. Khatri explained, that is because Dusija
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`later provides details regarding the cache (in the context of Figure 16). Ex. 1060,
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`134:12-140:9. Dusija shows great detail and attention to describing the cache and
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`its location and chose to do so with respect to Figure 16. To the extent Petitioner is
`
`criticizing PO for relying on what Dusija actually discloses, Petitioner’s criticisms
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`are misplaced and boil down to dissatisfaction with unhelpful (to Petitioner) gaps in
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`Dusija’s disclosure.
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`Furthermore, the fact that Dusija only mentions RAM once (in its background
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`section, Ex. 1010, ¶[0003], where Dusija distinguishes RAM from the rest of its
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`disclosure using flash), is telling. If Dusija wanted to describe the cache of Figures
`
`14A-14B as a RAM cache then Dusija surely could have done so, and indeed it is
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`revealing that for Figures 16A-16C and 20 Dusija did provide elaborate cache-
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`related details in text and figures.
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`Petitioner is basically asking the Board to accept a giant leap of faith—that at
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`some places Dusija shows and describes a cache in great detail (in figures, and also
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`in text, regarding Figures 16A-16C and 20) but at another place Dusija is silent as to
`
`the location of its cache and somehow omitted describing the cache as being in
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`Dusija’s controller—which Dusija explicitly addresses in a negative light, see Ex.
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`1010, ¶[013
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