UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`
`Case No.: IPR2021-01550
`U.S. Patent No. 10,950,300
`Original Issue Date: March 16, 2021
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`_________________________________________________________________
`
`PETITIONER’S REPLY
`_________________________________________________________________
`
`

`

`3.
`
`2.
`
`TABLE OF CONTENTS
`Introduction ..................................................................................................... 1
`I.
`Claim Construction ......................................................................................... 3
`II.
`III. Ground 1: Vervain Has Not Rebutted Micron’s Showing That Dusija
`in View of the Knowledge of a POSA Renders Claims 1-9 and 11-12
`Obvious ........................................................................................................... 3
`A.
`Limitation [1.E] .................................................................................... 3
`1.
`PO’s Objections to the Specificity of the Petition Lack
`Merit ........................................................................................... 3
`Contrary to PO’s Characterization, Petitioner’s
`Obviousness Theory Does Not Rely on Two Distinct
`“Mapping[s]” ............................................................................. 4
`The POR’s Teaching-Away Argument Lacks Merit ................. 6
`(a) The POR Is Deficient as a Matter of Law ....................... 6
`(1)
`In the Institution Decision, the Board Found
`That a POSA Would Have Been Motivated
`to Use a RAM Cache with Dusija ......................... 6
`(2) The POR Does Not Dispute the Factual
`Basis for the Institution Decision’s
`Motivation-to-Combine Finding ........................... 8
`(3) The POR’s Factual Contentions, Even If
`Accepted, Do Not Disturb the Board’s
`Obviousness Conclusion ....................................... 9
`(4) The “Random Access Volatile Memory”
`Cannot Render the Challenged Claims
`Patentable ............................................................ 12
`(b) The Record Evidence Establishes a Motivation to
`Combine Dusija’s Controller with a RAM Cache ......... 13
`(1) The Proposed Combination Is Not Contrary
`to Dusija’s Teachings .......................................... 14
`(2) A POSA Would Have Known That a Flash
`Memory Cache Has Many Disadvantages
`When Compared to a Cache in Controller
`RAM .................................................................... 20
`
`i
`
`

`

`Limitation [1.G.2]............................................................................... 23
`B.
`Limitation [1.H] .................................................................................. 24
`C.
`IV. Ground 2: Vervain Does Not Challenge Micron’s Showing That
`Dusija in View of Sutardja and the Knowledge of a POSA Render
`Claim 10 Obvious ......................................................................................... 25
`Conclusion .................................................................................................... 25
`
`V.
`
`ii
`
`

`

`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`In re Fulton,
`391 F.3d 1195 (Fed. Cir. 2004) .................................................................... 12, 22
`In re Ratti,
`270 F.2d 810, 813 (CCPA 1959) ........................................................................ 10
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 13
`
`iii
`
`

`

`LISTING OF EXHIBITS
`
`Exhibit Description
`
`1001-1006
`
`Intentionally omitted
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`U.S. Patent No. 10,950,300 (“300 patent”)
`
`File History of U.S. Patent No. 10,950,300
`
`Declaration of Dr. David Liu (“Liu Decl.”) – IPR2021-01550
`
`U.S. Patent Application Publication No. 2011/0099460 (“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`U.S. Patent Application Publication No. 2009/0327591
`(“Moshayedi”)
`
`Intentionally omitted
`
`Betty Prince, Semiconductor Memories – A Handbook of Design,
`Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617 (“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed. 2010)
`(“Micheloni”)
`
`U.S. Patent Application Publication No. 2011/0115192 (“Y. Lee”)
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601 (“Gavens”)
`
`iv
`
`

`

`Exhibit Description
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`1036
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition of
`read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition, 2006,
`definition of periodic
`
`Intentionally omitted
`
`U.S. Patent Application Publication No. 2010/0172180 (“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650 (“Chin”)
`
`European Patent Specification No. EP 2.291.746 B1 (“Radke”)
`
`Intentionally omitted
`
`U.S. Patent Application Publication No. 2006/0053246 (“S. Lee”)
`
`Complaint for Patent Infringement, Dkt. No. 1, Vervain, LLC v.
`Micron Technology, Inc., Micron Semiconductor Products, Inc.,
`and Micron Technology Texas, LLC, Case No. 6:21-cv-00487-
`ADA (May 10, 2021 W.D. Tex.)
`
`Agreed Scheduling Order, Dkt. No. 24, dated September 16, 2021,
`in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas, LLC,
`Case No. 6:21-cv-00487-ADA
`
`Vervain’s Preliminary Infringement Contentions, dated August 6,
`2021, in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas, LLC,
`Case No. 6:21-cv-00487-ADA
`
`v
`
`

`

`Exhibit Description
`
`1037
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`Judge Albright, Order Governing Proceedings - Patent Cases (OGP
`3.4), dated June 24, 2021
`
`Scott McKeown, “WDTX ‘Implausible Schedule’ & Cursory
`Markman Order Highlighted,” Ropes & Gray, Patents Post-Grant,
`Inside Views & News Pertaining to the Nation’s Busiest Patent
`Court, June 2, 2021
`
`Dani Kass, Judge Albright Now Oversees 20% of New U.S. Patent
`Cases, Law360, March 10, 2021
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`1044-1046
`
`Intentionally omitted
`
`1047
`
`1048
`
`1049
`
`1050
`
`1051
`
`1052
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definitions of
`static RAM and volatile memory
`
`U.S. Patent No. 5,936,971 (“Harari”)
`
`PCT Publication No. WO 03/027828 (“Gorobets WO”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`address space
`
`U.S. Patent Application Publication No. 2009/0300269 (“Radke
`Appl.”)
`
`1053
`
`U.S. Patent No. 8,250,333 (“Gorobets II”)
`
`vi
`
`

`

`Exhibit Description
`
`1054
`
`1055
`
`1056
`
`1057
`
`1058
`
`1059
`
`1060
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition of
`firmware
`
`Intentionally omitted
`
`Declaration of Jared Bobrow in Support of Petitioner’s Motion for
`Admission Pro Hac Vice - IPR2021-01550
`
`Reply Declaration of Dr. David Liu (“Liu Reply”) – IPR2021-
`01550
`
`Curriculum vitae of Dr. David Liu
`
`Intentionally omitted
`
`Deposition Transcript of Sunil Khatri (September 2, 2022) –
`IPR2021-01550
`
`1061 –
`1067
`
`Intentionally omitted
`
`1068
`
`U.S. Patent No. 8,010,873 (“Kirschner”)
`
`vii
`
`

`

`I.
`
`INTRODUCTION
`
`In the Patent Owner Response (“POR”), Patent Owner (“PO”) doubles down
`
`on arguments that were already considered—and rejected—in the Board’s
`
`Institution Decision (“ID”). As in the Patent Owner Preliminary Response
`
`(“POPR”), PO argues that although the primary prior art reference, Dusija,
`
`discloses a “cache,” it does not disclose implementing that cache using a “random
`
`access volatile memory” (“RAM,” for short). And, as before, PO argues that a
`
`POSA would have been discouraged from using a RAM cache with Dusija’s
`
`system because, PO contends, a RAM cache has disadvantages relative to a cache
`
`in flash memory.
`
`The Board already explained why these arguments lack merit. The Board
`
`stated that Dusija’s lack of an express disclosure of a RAM cache is irrelevant
`
`because Petitioner’s theory is obviousness, not anticipation. The Board also
`
`rejected PO’s argument that Dusija taught away from using a RAM cache. In
`
`doing so, the Board relied on three key and undisputed facts. First, a POSA
`
`“would have known of the use of volatile memory for caching and would have
`
`considered such a use to be typical and well understood.” Paper 11 (“ID”), 26-27.
`
`Second, a POSA “would have known of the benefits of using RAM or other
`
`volatile memory,” such as “superior write endurance” and “increased speed.”
`
`ID, 30. Third, “there would have been a reasonable expectation of success in
`
`1
`
`

`

`using volatile memory as cache because such a usage was considered to be
`
`‘typical’ and thus, would not have required undue experimentation to implement.”
`
`Id. Although PO has submitted expert testimony and has cross-examined
`
`Petitioner’s expert, PO does not dispute any of these facts. Nor does the POR
`
`provide any evidence to counter these facts. Accordingly, the full record confirms
`
`the Board’s motivation-to-combine finding at the institution phase.
`
`PO argues, as it did before, that Dusija teaches away from the Petition’s
`
`proposed combination because the combination “degrades performance.” Paper 16
`
`(“POR”), 45. But the Board found this argument unpersuasive, reasoning that
`
`Patent Owner’s expert did not explain why the alleged inefficiencies outweighed
`
`the known benefits of a RAM cache over a flash memory cache. Following
`
`institution, PO has again failed to perform this weighing in its POR. PO’s alleged
`
`“performance degradation” cannot defeat Petitioner’s obviousness challenge.
`
`The POR manufactures various meritless objections to the form of the
`
`Petition and, substantively, rests on a legally erroneous belief that a combination is
`
`not obvious unless it is superior in all respects to a disclosed embodiment. The
`
`Board should reject the POR’s meritless arguments and hold all challenged claims
`
`unpatentable.
`
`2
`
`

`

`II.
`
`CLAIM CONSTRUCTION
`
`Petitioner agrees that express claim constructions are not necessary to
`
`resolve the remaining issues in this proceeding. ID, 14-15.
`
`III. GROUND 1: VERVAIN HAS NOT REBUTTED MICRON’S
`SHOWING THAT DUSIJA IN VIEW OF THE KNOWLEDGE OF A POSA
`RENDERS CLAIMS 1-9 AND 11-12 OBVIOUS
`
`A.
`
`Limitation [1.E]
`
`1.
`
`PO’s Objections to the Specificity of the Petition Lack Merit
`
`PO’s allegation that the Petition is not sufficiently specific lacks merit. PO
`
`contends that Petitioner has not sufficiently identified the location of the “random
`
`access volatile memory.” See POR, 34. In making this argument, PO attacks a
`
`straw man, because the claims do not require the random access volatile memory
`
`to be in any specific location. Ex. 1057 (“Liu Reply”), ¶ 13. The independent
`
`claims merely recite “[a] system for storing data comprising … at least one random
`
`access volatile memory.” Ex. 1007, claim 1. And claim 3, which potentially limits
`
`the “random access volatile memory” to being “embedded” in the controller,
`
`confirms that the independent claims have no such requirement. PO’s contention
`
`that Petitioner failed to map the RAM to a specific location is thus of no moment.
`
`POR, 34; Liu Reply, ¶ 14.
`
`Regardless, Petitioner does sufficiently explain how the claimed “random
`
`access volatile memory” is rendered obvious. For example, the Petition explained
`
`3
`
`

`

`that Dusija discloses a “cache,” and that “it would have been obvious to employ
`
`Dusija’s controller with RAM and [to] implement Dusija’s cache as RAM.”
`
`Petition, 36. Contrary to PO’s position, this is a “clear mapping” of the claims.
`
`POR, 34.
`
`Contrary to PO’s Characterization, Petitioner’s
`2.
`Obviousness Theory Does Not Rely on Two Distinct “Mapping[s]”
`
`PO’s characterization of Petitioner’s obviousness theory is both confusing
`
`and wrong. PO speculates that Petitioner may be making two arguments in the
`
`alternative for limitations [1.E], [1.G.2], and [1.H]. POR, 37. To PO, Petitioner’s
`
`so-called “first mapping” is that it would have been obvious to modify Dusija’s
`
`controller to add a random access volatile memory. Id., 47-50, 53-57. To PO,
`
`Petitioner’s so-called “second mapping” is that it would have been obvious to
`
`modify Dusija’s cache, which PO insists must be in flash memory, to be a random
`
`access volatile memory. Id., 50-52, 57-59.
`
`This misstates Petitioner’s position. Petitioner’s theory is simple: it would
`
`have been obvious to modify Dusija to add a RAM cache at the controller (i.e., use
`
`the conventional controller’s RAM to implement the cache). Petition, 49 (“[D]ata
`
`is retained in Dusija’s ‘cache,’ which would have been understood, and at least
`
`obvious, to be the controller’s RAM.”); id. at 33 (“A POSA would have
`
`understood (and certainly would have found it obvious) that a cache is typically
`
`implemented in random access volatile memory.”); id. at 36 (“[I]t would have been
`
`4
`
`

`

`obvious to employ Dusija’s controller with RAM and implement Dusija’s cache as
`
`RAM”).
`
`The POR’s mischaracterization of Petitioner’s theory is especially
`
`problematic because it disconnects the role of Dusija’s controller and the role of
`
`Dusija’s cache in Petitioner’s proposed combination. PO’s “first mapping”
`
`correctly notes that, in the proposed combination, Dusija’s controller would use
`
`RAM. But PO’s “first mapping” incorrectly ignores that, in the proposed
`
`combination, the controller RAM would be used to implement Dusija’s cache.
`
`POR, 47-49 (arguing that because the Petition’s discussion of a limitation
`
`purportedly mentions a “cache” but not a “controller,” it cannot relate to
`
`Petitioner’s “first mapping”). The POR’s “second mapping” correctly notes that
`
`latter point—that, in the proposed combination, Dusija’s cache would be
`
`implemented with RAM. But PO’s “second mapping” incorrectly assumes that, in
`
`the proposed combination, the RAM is in the flash memory. POR, 51 (arguing that
`
`“Dusija’s cache is within flash memory”). In fact, the RAM is controller RAM.
`
`Each of PO’s “mapping[s]” is thus an inaccurate characterization of Petitioner’s
`
`actual obviousness theory.
`
`PO’s attempt to sow confusion as to the Petition’s obviousness theory is
`
`belied by the filings in this proceeding. The POPR did not break up the Petition
`
`into a so-called “first mapping” and “second mapping,” but instead consistently
`
`5
`
`

`

`described Petition’s obviousness theory as “modify[ing] Dusija to add a RAM
`
`cache at the controller.” E.g., Paper 9, (“POPR”), 47. Nor did the ID describe the
`
`Petition as advancing two distinct “mappings.” The POR’s manufactured
`
`mischaracterization of the Petition’s obviousness theory should be rejected.
`
`3.
`
`The POR’s Teaching-Away Argument Lacks Merit
`
`(a)
`
`The POR Is Deficient as a Matter of Law
`
`The POR’s core argument—that a POSA would not have been motivated to
`
`use a RAM cache with Dusija’s controller—was already considered and rejected
`
`by the Board in its ID. In arriving at its conclusion, the Board noted several
`
`undisputed facts regarding the prevalence and recognized advantages of RAM
`
`caches in flash memory controllers. The POR does not dispute the factual basis for
`
`the ID. And the factual contentions the POR does make, even if accepted, are not
`
`sufficient to avoid unpatentability. Because undisputed facts render the challenged
`
`claims obvious, the Board should adopt the reasoning in its ID and hold that the
`
`challenged claims are unpatentable.
`
`In the Institution Decision, the Board Found
`(1)
`That a POSA Would Have Been Motivated to Use a
`RAM Cache with Dusija
`
`In the POPR, PO opposed the Petition on two primary grounds: (1) that the
`
`cited prior art references did not expressly disclose a RAM cache, POPR, 45-51;
`
`6
`
`

`

`and (2) that a POSA would not have been motivated to use a RAM cache with
`
`Dusija’s controller. Id., 51-61.
`
`The Board considered and rejected these arguments. The Board explained
`
`that PO’s argument that no cited prior art reference expressly disclosed a RAM
`
`cache, even if correct, was unpersuasive because Petitioner had made an
`
`obviousness (not anticipation) challenge. ID, 26-27. And the Board rejected PO’s
`
`contention that a POSA would not have been motivated to use a RAM cache with
`
`Dusija’s controller. In doing so, the Board made three key factual findings.
`
`First, the Board found that a POSA “would have known of the use of
`
`volatile memory for caching and would have considered such a use to be typical
`
`and well understood.” ID, 26-27. Second, the Board found that a POSA “would
`
`have known of the benefits of using RAM or other volatile memory,” and that a
`
`POSA would have known these benefits to include “superior write endurance” and
`
`“increased speed.” Id., 29-30. Third, the Board found that a POSA would have
`
`had “a reasonable expectation of success in using volatile memory as cache
`
`because such a usage was considered to be ‘typical’ and thus[] would not have
`
`required undue experimentation to implement.” Id., 30. In reaching these
`
`conclusions, the Board relied on voluminous record evidence. E.g., Ex. 1048, 497,
`
`558; Ex. 1008, 48, 78; Ex. 1028, Fig. 1, ¶¶ 119, 197; Ex. 1049, 12:20-35, 13:24-22,
`
`13:58-14:11; Ex. 1009 (“Liu Decl.”), ¶¶ 129-132.
`
`7
`
`

`

`The Board thus concluded that “one of ordinary skill in the art would have
`
`been motivated to add RAM to Dusija’s controller to perform data integrity tests.”
`
`ID, 30.
`
`The POR Does Not Dispute the Factual Basis
`(2)
`for the Institution Decision’s Motivation-to-Combine
`Finding
`
`The POR does not challenge any of the factual bases underlying the Board’s
`
`finding that a POSA would have been motivated to add RAM to Dusija’s
`
`controller. The POR does not dispute that Dusija discloses all claim elements
`
`besides a “random access volatile memory” and that “random access volatile
`
`memory” (i.e., “RAM”) was known to a POSA. The POR does not dispute, and
`
`offers no evidence to counter the fact, that a POSA would have understood that
`
`RAM caches were typically used in conjunction with flash memory controllers,
`
`that RAM caches’ advantages of superior write endurance and speed were well
`
`understood, or that a POSA would have known how to implement a RAM cache
`
`with a flash memory controller. In fact, PO’s expert, Dr. Sunil Khatri, expressly
`
`admitted many of these facts at deposition:
`
` A POSA would have known that RAM could be used with an SSD
`
`controller, and had highly desirable properties for functionalities that
`
`were typical in SSDs controllers such as logical-to-physical address
`
`8
`
`

`

`translation and controller code execution. Ex. 1060, Khatri Dep.,
`
`58:14-15, 62:16-19, 68:18-19, 69:1-15, 73:4-9.
`
` A POSA would have known that DRAM and SRAM have greater
`
`write endurance than flash memory. Id., 86:8-12, 89:6-14.
`
` A POSA would have known that writes to flash memory were
`
`generally slower than writes to RAM, and that frequently updated data
`
`would preferentially be stored in a faster memory like RAM. Id.,
`
`69:1-15.
`
`Far from contradicting the factual basis for the ID’s motivation-to-combine
`
`findings, the testimony from POR’s own expert actually confirms them.
`
`The POR’s Factual Contentions, Even If
`(3)
`Accepted, Do Not Disturb the Board’s Obviousness
`Conclusion
`
`The POR makes various factual assertions that, to PO, support a finding of
`
`patentability here. But even assuming that these factual assertions were correct
`
`(they are not), they are insufficient as a matter of law to defeat the Petition’s
`
`showing that a POSA would have been motivated to use a RAM cache with
`
`Dusija’s controller (the Board’s conclusion at the institution phase).
`
`9
`
`

`

`PO’s Assertions That Each Cache
`(i)
`Described in Dusija Is in Flash Memory, and
`that the Proposed Combination Requires
`Adding a Component to Dusija, Even If
`Accepted, Are of No Consequence to the
`Obviousness Analysis
`
`PO asserts that each “cache” described in Dusija must be a flash memory
`
`cache. E.g., POR, 43-44. As explained in Section III.A.3(b)(1)(i), below, the
`
`premise of PO’s argument is incorrect because not all of Dusija’s embodiments are
`
`described as using a flash memory cache. PO further asserts that the proposed
`
`combination would require “an additional component (a RAM separate from flash
`
`memory).” As explained in Section III.A.3(b)(1)(ii), below, this too is incorrect
`
`because a POSA would have understood Dusija’s controller to have RAM.
`
`Even assuming that PO’s characterization of Dusija were correct, it does not
`
`call into question the ID’s reasoning. As the ID noted, Petitioner’s challenge is
`
`one of obviousness, not anticipation. ID, 26. PO does not dispute the multiple
`
`reasons in the record for using a RAM cache with Dusija’s controller. See Section
`
`III.A.3(a)(2). And PO does not contend that the use of a RAM cache would make
`
`the proposed combination inoperable—PO dropped that argument after it was
`
`rejected in the ID. POPR, 57-58; ID, 31. PO’s reliance on In re Ratti, which
`
`involved a proposed combination that the Court found “cannot function,” is thus
`
`misplaced. 270 F.2d 810, 813 (CCPA 1959). Thus, PO’s assertion, even if
`
`credited, is of no consequence to the obviousness analysis.
`
`10
`
`

`

`PO’s Assertion That the Use of a
`(ii)
`Controller RAM Cache with Dusija Would
`Detract from Performance, Even If Accepted, Is
`Insufficient to Avoid Unpatentability
`
`PO asserts that a POSA would not have been motivated to use a RAM cache
`
`with Dusija because doing so would “change the fundamental principle of Dusija’s
`
`operation … in a manner that detracts from performance.” POR, 45-46. First, PO
`
`asserts that the use of a RAM cache would require “toggling” (i.e., transferring)
`
`data from flash memory to the controller and, if too many errors are detected,
`
`toggling the corrected data from the controller back to the flash memory. Id., 45,
`
`49-50, 55. To PO, this toggling is avoided (saving time) if a flash memory cache is
`
`used. Second, PO asserts that the use of a flash memory cache enables, in the
`
`event of excessive errors, redirection of accesses to the cached copy without the
`
`need for a further rewrite. Id., 44-45. As explained in Section III.A.3(b)(1)(iii),
`
`below, Dusija expressly discloses embodiments in which toggling and rewrites are
`
`required, contradicting the notion that avoiding these steps is “fundamental” to
`
`Dusija. In addition, as explained in Section III.A.3(b)(2), PO’s contention that the
`
`proposed combination degrades performance relative to a flash memory cache is
`
`unsubstantiated because it fails to account for the well-known disadvantages of a
`
`flash memory cache.
`
`Even if PO’s assertions as to the proposed combination’s performance were
`
`credited, they are insufficient as a matter of law to avoid unpatentability. As the
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`Federal Circuit has explained, “a known or obvious composition does not become
`
`patentable simply because it has been described as somewhat inferior to some
`
`other product for the same use.” In re Fulton, 391 F.3d 1195, 1200 (Fed. Cir.
`
`2004). The correct question “is whether there is something in the prior art as a
`
`whole to suggest the desirability, and thus the obviousness, of making the
`
`combination, not whether there is something in the prior art as a whole to suggest
`
`that the combination is the most desirable combination available.” Id. (emphasis
`
`in original). PO does not dispute that a POSA would have known: (1) that RAM
`
`could be used to implement caches, such as Dusija’s cache; and (2) that RAM has
`
`advantages over a flash memory, including superior write endurance and speed.
`
`See Section III.A.3(a)(2). Undisputed evidence thus establishes the desirability of
`
`using a RAM cache with Dusija. PO’s argument, which at best amounts to an
`
`assertion that the use of a RAM cache with Dusija is not the “most desirable
`
`combination,” is insufficient to make the claims patentable. See Fulton, 391 F.3d
`
`at 1200.
`
`The “Random Access Volatile Memory”
`(4)
`Cannot Render the Challenged Claims Patentable
`
`At its core, the POR’s argument is that the claimed invention’s use of a
`
`“random access volatile memory,” as opposed to Dusija’s flash memory cache,
`
`renders the claims nonobvious. But “when a patent claims a structure already
`
`known in the prior art that is altered by the mere substitution of one element for
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`another known in the field, the combination must do more than yield a predictable
`
`result.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Here, PO claims
`
`patentability based on the substitution of one element (a flash memory cache) with
`
`another known in the field (a RAM cache). But the challenged patent never
`
`suggests any unpredictable result from the use of a RAM cache. Liu Reply, ¶ 61-
`
`62. For example, the challenged patent never suggests how it would avoid the
`
`“toggling” that, according to PO, would have discouraged a POSA from using a
`
`RAM cache with Dusija. POR, 56; Liu Reply, ¶ 61. Because “random access
`
`volatile memory” was known and its use with Dusija’s controller had predictable
`
`results, “random access volatile memory” cannot render the claims nonobvious.
`
`Liu Reply, ¶¶ 58-63.
`
`The Record Evidence Establishes a Motivation to
`(b)
`Combine Dusija’s Controller with a RAM Cache
`
`As the ID found, a POSA would have been motivated by the well-
`
`understood advantages of RAM to use a RAM cache with Dusija’s controller.
`
`ID, 30. PO’s teaching-away argument fails because a POSA knew that controller
`
`RAM was typically used to implement caches, had well understood advantages as
`
`compared to a flash memory cache, and could be used to perform Dusija’s data
`
`integrity tests. Liu Decl., ¶¶ 129-30; Liu Reply, ¶¶ 15-63. The fact that a
`
`controller RAM cache may have some disadvantages as compared to a flash
`
`memory cache does not render the challenged claims patentable.
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`The Proposed Combination Is Not Contrary to
`(1)
`Dusija’s Teachings
`
`PO argues that Dusija teaches away from Petitioner’s proposed combination
`
`because, to PO, the use of a controller RAM cache “changes the fundamental
`
`principle of Dusija’s operation.” POR, 43. For the following reasons, PO’s
`
`arguments should be rejected.
`
`Contrary to PO’s Assertion, Dusija Does
`(i)
`Not Require the Use of the Flash Memory
`Cache
`
`PO argues that “Dusija’s cache is disclosed as being part of flash memory
`
`array 200; yet Petitioner’s obviousness theory apparently seeks to shift that cache
`
`to a separate structure outside of memory array 200.” POR, 44. Even assuming
`
`that PO were correct, its assertion is insufficient to render the claims patentable
`
`because Petitioner’s challenge is one of obviousness, not anticipation. See Section
`
`III.A.3(a)(3)(i).
`
`Regardless, PO’s argument is based on the faulty premise that Dusija’s
`
`cache is always disclosed as “being part of flash memory array 200.” POR, 44.
`
`While it is true that some embodiments of Dusija use non-volatile memory as
`
`cache, PO fails to recognize that Dusija also discloses embodiments in which the
`
`location of the cache is not specified. Liu Reply, ¶ 17. The POR repeatedly cites
`
`paragraphs [0127]-[0131] (associated with an “alternative embodiment” of Figure
`
`15) and paragraphs [0132]-[0150] (associated with Figures 16A-C). POR, 37-38,
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`14
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`

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`42-44. These embodiments, to be sure, describe the use of the non-volatile
`
`memory for caching. However, Dusija discloses a separate set of embodiments,
`
`discussed in paragraphs [0108]-[0118] (associated with Figures 14A-B) and
`
`[0119]-[0126] (associated with the primary embodiment of Figure 15). Indeed, the
`
`Petition relies on Figures 14A-B and the primary embodiment of Figure 15, not the
`
`“alternative embodiment” of Figure 15 and Figures 16A-C (on which PO relies).
`
`See Petition, 48 (citing paragraphs [0111]-[0116], [0119]-[0124]). A POSA
`
`reviewing Dusija would have recognized that, in Figures 14A-B and the primary
`
`embodiment of Figure 15, Dusija left the location of the cache open.
`
`First, Dusija’s silence as to the location of the cache in Figures 14A-B
`
`suggests that the cache is not in flash memory. Figures 16A-C of Dusija depict a
`
`flash memory and expressly show the cache inside. So do Figures 20A-C of
`
`Dusija. However, Figures 14A-B show a flash memory but do not depict a cache
`
`at all. The description associated with Figures 14A-B (specifically, paragraph
`
`[0112]) notes that “cached” data may be used to verify a post-write read operation,
`
`but Dusija does not specify where the cache is. Ex. 1010 (“Dusija”), [0112]. In
`
`light of Dusija’s decision to show the cache inside the flash memory in Figures
`
`16A-C and 20A-C, a POSA would have understood Dusija’s decision to show
`
`Figure 14A-B’s flash memory without a cache and to not specify the location of
`
`the cache in paragraph [0112] to mean that the cache location in those
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`embodiments is left open. Liu Reply, ¶¶ 18, 20. And a POSA would have
`
`immediately thought of controller RAM as a common and desirable location for
`
`the cache referenced in paragraph [0112]. Id.
`
`Second, regarding Figure 15, Dusija states that “in an alternative
`
`embodiment, the first portion [of the flash memory] serves as a cache for incoming
`
`data, so a cache[d] input data is programmed into the cache.” Dusija, [0127]. That
`
`the use of the “first portion” for the cache is an “alternative embodiment” strongly
`
`suggests that there is at least one embodiment in which the “first portion” is not
`
`used for the cache. Even Dr. Khatri admitted as much. Ex. 1060, 129:11-20. This
`
`contradicts the POR’s position that the non-volatile memory must be used for the
`
`cache. Liu Reply, ¶ 19.
`
`Thus, the proposed combination does not involve “replacing Dusija’s cache
`
`with a fundamentally different component,” POR, 46. Liu Reply, ¶ 21.
`
`(ii) Contrary to the PO’s Assertion, a POSA
`Would Have Understood Dusija’s “Controller”
`to Have RAM
`
`PO asserts that the proposed combination fails because it would “requir[e]
`
`an additional component,” namely, controller RAM. POR, 45. Even if PO were
`
`correct, that is of no consequence because Petitioner’s theory is one of
`
`obviousness, not anticipation. See Section III.A.3(a)(3)(i). And PO’s assertion is
`
`in fact wrong. A POSA would have recognized that Dusija’s controller already
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`had RAM, at least because RAM was the standard way to implement other of
`
`Dusija’s functions such as code execution and logical-to-physical address
`
`translation. Liu Decl., ¶ 130; Liu Reply, ¶¶ 22-26.
`
`(iii) Contrary to PO’s Assertion, the Proposed
`Combination Does Not “Change the
`Fundamental Principle of Dusija’s Operation”
`
`PO asserts that the proposed combination “change[s] the fundamental
`
`principle of Dusija’s operation with respect to using the cache … in a manner that
`
`detracts from performance.” POR, 46. PO’s assertion—even if accepted—is
`
`insufficient to render the challenged claims patentable. See Section III.A.3(a)(3).
`
`And PO’s assertion lacks merit because the use of a flash memory cache is not
`
`“fundamental” to Dusija.
`
`First, PO does not dispute that the use of a controller RAM cache with
`
`Dusija would be operable. The Petition lays out exactly how the proposed
`
`combination would work to improve data integrity in a flash memory system. See
`
`generally Petition, 16, 32-53; Liu Decl., ¶¶ 61, 129-130. The POPR had argued
`
`that the proposed combination would be inoperable. POPR, 57-58. But the ID
`
`rejected that argument (ID, 30) and the POR has dropped it. Nor does PO contend
`
`that using