EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`
`U.S. Patent Application Publication No. 2011/0099460 (“Dusija”) was filed on December 18, 2009 and published on April 28, 2011.
`Dusija is prior art to the ’300 patent under at least 35 U.S.C. §§ 102(a), (e) (pre-AIA). The asserted claims of the ’300 patent are
`anticipated by Dusija expressly and/or inherently or rendered obvious, either alone or in combination with other references, as set
`forth in the cover pleading for Micron’s Initial Invalidity Contentions and as further explained in the chart below.
`
`This chart is based on Defendants’ present understanding of Plaintiff’s apparent positions as to the scope of the asserted claims. By
`including prior art that invalidates the claims of the patent based on Plaintiff’s claim construction and infringement positions,
`Defendants are neither adopting nor acceding in any manner to Plaintiff’s claim construction and infringement positions.
`Furthermore, nothing stated herein shall be treated as an admission or suggestion that Defendants agree with Plaintiff regarding either
`the scope of any of the asserted claims or the claim constructions Plaintiff advances in its infringement allegations or anywhere else.
`Nor shall anything in this chart be treated as an admission that any of Defendants’ accused technology meets any limitations of the
`claims.
`
`Claim 1
`[1.Pre] A system for storing
`data comprising:
`
`[1.A.1] memory space
`containing volatile memory
`space and nonvolatile
`memory space
`
`U.S. Pat. No. 10,950,300
`Disclosure in Dusija
`To the extent the preamble is limiting, Dusija discloses and/or renders obvious a system for storing
`data.
`
`See, e.g.,
`
`
`
`Dusija discloses and/or renders obvious memory space containing volatile memory space and
`nonvolatile memory space.
`
`See, e.g.,
`
`
`
`[0059]
` FIG. 1
`
` FIG. 1
`
`[0059]
`
`[0068]
`
`[0111]–[0117]
`
`
`
`1
`
`Vervain Ex. 2009, p. 1
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`[1.A.2] wherein the
`nonvolatile memory space
`includes both multilevel cell
`(MLC) memory space and
`single level cell (SLC)
`memory space
`
`[1.B] at least one controller to
`operate memory elements and
`associated memory space
`
`[1.C] at least one MLC
`nonvolatile memory element
`that can be mapped into the
`MLC memory space
`
`U.S. Pat. No. 10,950,300
`
`[0062]
`[0020]-[0023] (cache)
`
`
`
`
`
`See also Claim limitation [1.A.2] and accompanying citations.
`
`Dusija discloses and/or renders obvious wherein the nonvolatile memory space includes both
`multilevel cell (MLC) memory space and single level cell (SLC) memory space.
`
`See, e.g.,
`
`
` FIG. 14B
`
`[0109]
`
`
`Dusija discloses and/or renders obvious at least one controller to operate memory elements and
`associated memory space.
`
`See, e.g.,
`
`
` FIG. 1
`
`[0060]
`
`[0062]
`
`[0117]
`
`
`See also Claim limitations [1.A.1-2] and accompanying citations.
`
`Dusija discloses and/or renders obvious at least one MLC nonvolatile memory element that can be
`mapped into the MLC memory space.
`
`See, e.g.,
`
`
`2
`
`
`
`
`
`Vervain Ex. 2009, p. 2
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`U.S. Pat. No. 10,950,300
`
`
`[0059]
`
`[0060]
`
`[0117]
`
`[0120]
` FIG. 14B
`
`
`See also Claim limitations [1.A.2, 1.C] and accompanying citations.
`
`Dusija discloses and/or renders obvious at least one random access volatile memory.
`
`See, e.g.,
`
`
` FIG. 1
`
`[0059]
`
`[0068]
`
`[0111]–[0117]
`
`[0062]
`
`3
`
`
`See also Claim limitation [1.A.2] and accompanying citations.
`
`Dusija discloses and/or renders obvious at least one SLC nonvolatile memory element that can be
`mapped into the SLC memory space.
`
`See, e.g.,
`
`
`
`
`
`
`
`
`[0117]
`[0129]
`[0059]
`[0109]
`[0120]
`
`
`
`
`
`[1.D] at least one SLC
`nonvolatile memory element
`that can be mapped into the
`SLC memory space
`
`
`[1.E] at least one random
`access volatile memory
`
`Vervain Ex. 2009, p. 3
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`U.S. Pat. No. 10,950,300
`[0020]-[0023] (cache)
`
`
`
`
`See also Claim limitation [1.A.1] and accompanying citations.
`
`Dusija discloses and/or renders obvious the controller controlling access of the MLC and SLC
`nonvolatile memory elements and the random access volatile memory for storage of data therein.
`
`See, e.g.,
`
`
` FIG. 1
`
`[0059]
`
`[0060]
`
`[0117]
`
`See also Claim limitation [1.A.1] and accompanying citations.
`
`Dusija discloses and/or renders obvious the controller, in at least a Write access operation to the MLC
`
`4
`
`
`See also Claim limitation [1.A.1] and accompanying citations.
`
`Dusija discloses and/or renders obvious an FTL flash translation layer, wherein the at least one
`controller, or FTL, or a combination of both maintain an address table in one or more of the memory
`elements and random access volatile memory.
`
`See, e.g.,
`
`
`
`
`
`
`
`[0017]
`[0059]
`[0060]
`[0117]
`
`
`
`
`
`[1.F] an FTL flash translation
`layer, wherein the at least one
`controller, or FTL, or a
`combination of both maintain
`an address table in one or
`more of the memory elements
`and random access volatile
`memory
`
`[1.G.i] the controller
`controlling access of the MLC
`and SLC nonvolatile memory
`elements and the random
`access volatile memory for
`storage of data therein
`
`[1.G.ii] the controller, in at
`
`Vervain Ex. 2009, p. 4
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`least a Write access operation
`to the MLC nonvolatile
`memory element, operable to
`store data in the MLC
`nonvolatile memory element
`and retain such stored data in
`the random access volatile
`memory
`
`[1.H] the controller
`performing a data integrity
`test on stored data in the MLC
`nonvolatile memory element
`after at least a Write access
`operation performed thereon
`by comparing the stored data
`to the retained data in the
`random access volatile
`memory
`
`[1.I] wherein the address table
`maps logical and physical
`addresses adaptable to the
`system, wherein the mapping
`is performed as necessitated
`
`
`
`
`
`U.S. Pat. No. 10,950,300
`nonvolatile memory element, operable to store data in the MLC nonvolatile memory element and
`retain such stored data in the random access volatile memory.
`
`See, e.g.,
`
`
`
`
`
`
`[0060]
`[0111]-[0116]
`[0119]-[0124]
`
`
`See also Claim limitation [1.A.1] and accompanying citations.
`
`Dusija discloses and/or renders obvious the controller performing a data integrity test on stored data in
`the MLC nonvolatile memory element after at least a Write access operation performed thereon by
`comparing the stored data to the retained data in the random access volatile memory.
`
`See, e.g.,
`
`
` FIG. 1
`
`[0062]
`
`[0111]-[0116]
`
`[0119]-[0124]
`
`[0203]
`
`See also Claim limitation [1.G.2] and accompanying citations.
`
`Dusija discloses and/or renders obvious wherein the address table maps logical and physical addresses
`adaptable to the system, wherein the mapping is performed as necessitated by the system to maximize
`lifetime, and wherein the mapping maps blocks, pages, or bytes of data in either volatile or
`nonvolatile, or both, memories.
`
`
`5
`
`Vervain Ex. 2009, p. 5
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`by the system to maximize
`lifetime, and wherein the
`mapping maps blocks, pages,
`or bytes of data in either
`volatile or nonvolatile, or
`both, memories; and
`
`[1.J] wherein a failure of the
`data integrity test performed
`by the controller results in a
`remapping of the address
`space to a different physical
`range of addresses and
`transfer of data corresponding
`to the stored data to those
`remapped physical addresses
`from those determined to
`have failed the data integrity
`
`
`
`
`
`U.S. Pat. No. 10,950,300
`
`See, e.g.,
`
`
`
`[0016]
`
`[0027]
`
`[0059]
`
`[0060]
`
`[0101]
`
`[0109]-[0111]
`
`[0117]
`
`[0120]
`
`[0153]
`
`[0159]
`
`[0162]-[0163]
`
`[0166]-[0174]
`
`[0204]
` FIG. 14B
`
`
`See also Claim limitations [1.C, F, 1.J] and accompanying citations.
`
`Dusija discloses and/or renders obvious wherein a failure of the data integrity test performed by the
`controller results in a remapping of the address space to a different physical range of addresses and
`transfer of data corresponding to the stored data to those remapped physical addresses from those
`determined to have failed the data integrity test to achieve enhanced endurance.
`
`See, e.g.,
`
`
`
`
`
`
`
`[0109]
`[0111]
`[0112]
`[0116]
`
`6
`
`Vervain Ex. 2009, p. 6
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`U.S. Pat. No. 10,950,300
`
`
`
`
`[0117]
`[0119]-[0124]
`
`
`
`test to achieve enhanced
`endurance
`
`Claim 2
`[2] The system of claim 1,
`wherein the FTL flash
`translation layer is a software
`module, or a firmware
`module containing software
`updates
`
`Claim 3
`[3] The system of claim 1,
`wherein at least one of the
`random access volatile
`memory or the MLC and SLC
`nonvolatile memory elements
`are embedded in the at least
`one controller
`
`Claim 4
`[4] The system of claim 1,
`wherein the MLC and SLC
`nonvolatile memory elements
`
`
`
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the FTL flash translation layer
`is a software module, or a firmware module containing software updates.
`
`See, e.g.,
`
`
`
`
`
`[0117]
`[0060]
`
`
`See also Claim limitation [1.F] and accompanying citations.
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein at least one of the random
`access volatile memory or the MLC and SLC nonvolatile memory elements are embedded in the at
`least one controller.
`
`See, e.g.,
`
`
` FIG. 1
`
`[0062]
`
`See also Claim limitation [1.A.1] and accompanying citations.
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the MLC and SLC nonvolatile
`memory elements comprise flash memory.
`
`
`7
`
`Vervain Ex. 2009, p. 7
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`comprise flash memory.
`
`Claim 5
`[5] The system of claim 1,
`wherein the random access
`volatile memory is dynamic
`random access memory.
`
`Claim 6
`[6] The system of claim 1,
`wherein the random access
`volatile memory is static
`random access memory.
`
`
`
`
`
`U.S. Pat. No. 10,950,300
`
`See, e.g.,
`
`
`
`
`
`[0018] (“flash memory”)
`[0059], [0068], [0109] (MLC and SLC)
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the random access volatile
`memory is dynamic random access memory.
`
`See, e.g.,
`
`
` FIG. 1
`
`[0059]
`
`[0062]
`
`[0068]
`
`[0111]-[0117]
`
`
`See also Claim limitation [1.A.1] and accompanying citations.
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the random access volatile
`memory is static random access memory.
`
`See, e.g.,
`
`
` FIG. 1
`
`[0059]
`
`[0062]
`
`[0068]
`
`[0111]-[0117]
`
`8
`
`Vervain Ex. 2009, p. 8
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`U.S. Pat. No. 10,950,300
`
`
`See also Claim limitation [1.A.1] and accompanying citations.
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the controller, upon detection
`of a failure of the data integrity test, remaps the data to the SLC nonvolatile memory element.
`
`See, e.g.,
`
`
`
`
`
`
`
`[0060]
`[0109]
`[0116]-[0117]
`[0124]-[0125]
`
`See also Claim limitation [1.J] and accompanying citations.
`
`
`
`
`
`
`Claim 7
`[7] The system of claim 1,
`wherein the controller, upon
`detection of a failure of the
`data integrity test, remaps the
`data to the SLC nonvolatile
`memory element.
`
`Claim 8
`[8] The system of claim 7,
`wherein the SLC memory
`element has a higher
`endurance than the MLC
`memory element
`
`Claim 9
`[9] The system of claim 1,
`wherein the MLC is a
`multilevel cell, wherein the
`multilevel cell stores at least 2
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 7, wherein the SLC memory element has
`a higher endurance than the MLC memory element.
`
`See, e.g.,
`
`
`
`
`
`[0110]
`[0059]
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the MLC is a multilevel cell,
`wherein the multilevel cell stores at least 2 bits per cell
`
`See, e.g.,
`
`9
`
`Vervain Ex. 2009, p. 9
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`bits per cell.
`
`
`
`U.S. Pat. No. 10,950,300
`
`
`
`
`[0109]
`[0059]
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1, wherein the contents of frequently
`accessed portions of the memory space are periodically moved from the MLC space to the SLC space.
`
`See, e.g.,
`
`
`
`
`
`
`
`
`[0027] (threshold)
`[0153]-[0154]
`[0159]
`[0184]
`[0204]
`
`
`
`
`
`Claim 10
`[10] The system of claim 1,
`wherein the contents of
`frequently accessed portions
`of the memory space are
`periodically moved from the
`MLC space to the SLC space.
`
`Claim 11
`[11] The system of claim 1
`wherein the MLC allows a
`single cell to store multiple
`bits
`
`Claim 12
`[12.Pre] A system for storing
`data comprising:
`
`
`
`
`
`Disclosure in Dusija
`Dusija discloses and/or renders obvious the system of claim 1 wherein the MLC allows a single cell to
`store multiple bits.
`
`See, e.g.,
`
`
`
`
`
`[0109]
`[0059]
`
`
`
`Disclosure in Dusija
`To the extent the preamble is limiting, Dusija discloses and/or renders obvious a system for storing
`data.
`
`See Claim limitation [1.A] and accompanying citations.
`
`10
`
`Vervain Ex. 2009, p. 10
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`[12.A] memory space
`containing volatile memory
`space and nonvolatile
`memory space, wherein the
`nonvolatile memory space
`includes both multilevel cell
`(MLC) space and single level
`cell (SLC) space
`[12.B] at least one controller
`to operate memory elements
`and associated memory space,
`and to maintain an address
`table in one or more of the
`memory elements
`[12.C] at least one MLC
`nonvolatile memory element
`that can be mapped into the
`nonvolatile memory space
`
`[12.D] at least one SLC
`nonvolatile memory element
`that can be mapped into the
`SLC memory space
`
`[12.E] at least one random
`access volatile memory
`
`[12.F] the controller
`controlling access of the MLC
`
`U.S. Pat. No. 10,950,300
`
`
`Dusija discloses and/or renders obvious memory space containing volatile memory space and
`nonvolatile memory space, wherein the nonvolatile memory space includes both multilevel cell
`(MLC) space and single level cell (SLC) space.
`
`See Claim limitations [1.A.1-2] and accompanying citations.
`
`
`Dusija discloses and/or renders obvious at least one controller to operate memory elements and
`associated memory space, and to maintain an address table in one or more of the memory elements.
`
`See Claim limitations [1.B, 1.F] and accompanying citations.
`
`
`Dusija discloses and/or renders obvious at least one MLC nonvolatile memory element that can be
`mapped into the nonvolatile memory space.
`
`See Claim limitations [1.C-D] and accompanying citations.
`
`Dusija discloses and/or renders obvious at least one SLC nonvolatile memory element that can be
`mapped into the nonvolatile memory space.
`
`See Claim limitations [1.C-D] and accompanying citations.
`
`Dusija discloses and/or renders obvious at least one random access volatile memory.
`
`See Claim limitation [1.E] and accompanying citations.
`
`Dusija discloses and/or renders obvious the controller controlling access of the MLC and SLC
`nonvolatile memory elements and the random access volatile memory for storage of data therein, the
`
`11
`
`
`
`
`
`Vervain Ex. 2009, p. 11
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`and SLC nonvolatile memory
`elements and the random
`access volatile memory for
`storage of data therein, the
`controller, in at least a Write
`access operation to the MLC
`nonvolatile memory element,
`operable to store data in the
`MLC nonvolatile memory
`element and retain such stored
`data in the random access
`volatile memory
`[12.G] the controller
`performing a data integrity
`test on stored data in the MLC
`nonvolatile memory element
`after at least a Write access
`operation performed thereon
`by comparing the stored data
`to the retained data in the
`random access volatile
`memory
`[12.H] wherein the address
`table maps logical and
`physical addresses adaptable
`to the system, wherein the
`mapping is performed as
`necessitated by the system to
`maximize lifetime, and
`wherein the mapping maps
`blocks, pages, or bytes of data
`
`U.S. Pat. No. 10,950,300
`controller, in at least a Write access operation to the MLC nonvolatile memory element, operable to
`store data in the MLC nonvolatile memory element and retain such stored data in the random access
`volatile memory.
`
`See Claim limitations [1.G.1-2] and accompanying citations.
`
`
`
`Dusija discloses and/or renders obvious the controller performing a data integrity test on stored data in
`the MLC nonvolatile memory element after at least a Write access operation performed thereon by
`comparing the stored data to the retained data in the random access volatile memory.
`
`See Claim limitation [1.H] and accompanying citations.
`
`
`
`Dusija discloses and/or renders obvious wherein the address table maps logical and physical addresses
`adaptable to the system, wherein the mapping is performed as necessitated by the system to maximize
`lifetime, and wherein the mapping maps blocks, pages, or bytes of data in either volatile or
`nonvolatile, or both, memories.
`
`See Claim limitation [1.I] and accompanying citations.
`
`
`
`12
`
`
`
`
`
`Vervain Ex. 2009, p. 12
`Micron v. Vervain
`IPR2021-01550
`
`

`

`EXHIBIT D-3
`INVALIDITY CLAIM CHART FOR THE ’300 PATENT
`BASED ON U.S. PATENT APPLICATION PUB. NO. 2011/009460 (“Dusija”)
`
`U.S. Pat. No. 10,950,300
`
`Dusija discloses and/or renders obvious wherein a failure of the data integrity test performed by the
`controller results in a remapping of the address space to a different physical range of addresses and
`transfer of data corresponding to the stored data to those remapped physical addresses from those
`determined to have failed the data integrity test to achieve enhanced endurance.
`
`See Claim limitation [1.J] and accompanying citations.
`
`
`
`in either volatile or
`nonvolatile, or both,
`memories; and
`[12.I] wherein a failure of the
`data integrity test performed
`by the controller results in a
`remapping of the address
`space to a different physical
`range of addresses and
`transfer of data corresponding
`to the stored data to those
`remapped physical addresses
`from those determined to
`have failed the data integrity
`test to achieve enhanced
`endurance
`
`13
`
`
`
`
`
`
`
`Vervain Ex. 2009, p. 13
`Micron v. Vervain
`IPR2021-01550
`
`