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`
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`Declaration of Dr. David Liu
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`VERVAIN, LLC,
`Patent Owner
`
`
`
`
`Case No.: IPR2021-01549
`U.S. Patent No. 9,997,240
`Original Issue Date: June 12, 2018
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`
`
`
`DECLARATION OF DR. DAVID LIU
`
`
`1
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`Micron Ex. 1009, p. 1
`Micron v. Vervain
`IPR2021-01549
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`Declaration of Dr. David Liu
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`I.
`II.
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`Page
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 6
`EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS ............................................................... 6
`III. ASSIGNMENT AND MATERIALS CONSIDERED .................................. 9
`IV. UNDERSTANDING OF THE LAW ........................................................... 12
`V.
`LEVEL OF SKILL IN THE ART ................................................................ 16
`VI. THE 240 PATENT’S EFFECTIVE FILING DATE ................................... 17
`VII. THE 240 PATENT ....................................................................................... 17
`A.
`Technological Background ................................................................ 17
`1.
`Volatile, Non-volatile, and Flash Memory .............................. 17
`2.
`SLC and MLC Flash Memory Cells ........................................ 19
`3.
`Flash Architecture .................................................................... 21
`4.
`Logical Addresses, Physical Addresses, Bad Block
`Replacement, and Wear Leveling ............................................ 24
`Caching .................................................................................... 32
`Speed and Durability Considerations for MLC and SLC
`Cells.......................................................................................... 33
`Operations Based On A Collective Write Count ..................... 34
`7.
`Data Integrity Tests .................................................................. 36
`8.
`Summary of the 240 Patent’s Disclosure ........................................... 36
`B.
`The 240 Patent’s Prosecution History ................................................ 38
`C.
`VIII. CLAIM CONSTRUCTION ......................................................................... 40
`A.
`“data integrity test” (claim 1) ............................................................. 41
`B.
`“on a periodic basis” .......................................................................... 42
`C. Other Terms ........................................................................................ 43
`IX. HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE .............. 43
`A.
`Prior Art Overview ............................................................................. 43
`1.
`Dusija ....................................................................................... 43
`
`5.
`6.
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`2
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`2.
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`3.
`
`c.
`
`Sutardja .................................................................................... 46
`2.
`Chin .......................................................................................... 48
`3.
`B. Ground 1: Dusija And Sutardja In View Of The Knowledge Of
`A POSA Renders Obvious Claims 1-2 And 6-7 Of The 240
`Patent .................................................................................................. 49
`i.
`Individual counts interpretation .......................... 76
`ii.
`Collective count interpretation ............................ 81
`iii.
`[1.G.iii] and which determined blocks in the
`SLC are determined in accordance with the
`next equivalent range of physical addresses
`determined by the controller. .............................. 88
`Claim 2: “The system of claim 1, wherein the MLC and
`SLC each comprise flash memories.” ...................................... 91
`Claim 6 ..................................................................................... 91
`a.
`[6.PRE] “A system for storing data comprising:” ......... 91
`b.
`[6.A] “at least one MLC non-volatile memory
`module comprising a plurality of individually
`erasable blocks;” ............................................................ 91
`[6.B] “at least one SLC non-volatile memory
`module comprising a plurality of individually
`erasable blocks” ............................................................. 92
`[6.C] “a controller coupled to the at least one MLC
`non-volatile memory module and the at least one
`SLC non-volatile memory module” .............................. 92
`[6.D.i] “the controller maintaining an address map
`of at least one of the MLC and SLC non-volatile
`memory modules, the address map comprising a
`list of logical address ranges accessible by a
`computer system, [6.D.ii] the list of logical address
`ranges having a minimum quanta of addresses,
`[6.D.iii] wherein each entry in the list of logical
`address ranges maps to a similar range of physical
`addresses within either the at least one SLC non-
`volatile memory module or within the at least one
`MLC non-volatile memory module;” ............................ 92
`
`d.
`
`e.
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`3
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`f.
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`g.
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`[6.E] “wherein the controller allocates those blocks
`that receive frequent writes into the SLC non-
`volatile memory module as hot blocks and those
`blocks that only receive infrequent writes into the
`MLC non-volatile memory module as cold blocks;
`and” ................................................................................ 93
`[6.F] “wherein the controller is adapted to
`determine if a range of addresses listed by an entry
`and mapped to a similar range of physical
`addresses within the at least one MLC non-volatile
`memory module, fails a data integrity test, and in
`the event of such a failure, the controller remaps
`the entry to the next available equivalent range of
`physical addresses within the at least one SLC
`non-volatile memory module;” ...................................... 94
`[6.G.i] “wherein the controller is further adapted to
`maintain a count value of those blocks that are
`accessed most frequently, and [6.G.ii] and, on a
`periodic basis when the count value is a
`predetermined count value, transfer the contents of
`those counted blocks into the SLC non-volatile
`memory module, [6.G.iii] wherein the counted
`blocks transferred to after reaching the
`predetermined count value are determined in
`accordance with the next equivalent range of
`physical addresses determined by the controller.” ........ 94
`Claim 7: “The system of claim 6, wherein the MLC and
`SLC each comprise flash memories.” ...................................... 96
`5. Motivation to Combine ............................................................ 96
`C. Ground 2: Dusija, Sutardja, And Chin In View Of The
`Knowledge Of A POSA Renders Obvious Claims 1-2 and 6-7
`Of The 240 Patent ............................................................................... 99
`
`h.
`
`4.
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`4
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`a.
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`a.
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`[1.G] “[1.G.i] maintain a count value of the blocks
`in the MLC non-volatile memory module
`determined to have received frequent writes and
`that are accessed most frequently [1.G.ii] on a
`periodic basis when the count value is a
`predetermined count value transfer the contents of
`the counted blocks in the MLC non-volatile
`memory module determined to have received
`frequent writes after reaching the predetermined
`count value to the SLC non-volatile memory
`module and [1.G.iii] which determined blocks in
`the SLC are determined in accordance with the
`next equivalent range of physical addresses
`determined by the controller.” ..................................... 100
`[6.G.i] “wherein the controller is further adapted to
`maintain a count value of those blocks that are
`accessed most frequently, and [6.G.ii] and, on a
`periodic basis when the count value is a
`predetermined count value, transfer the contents of
`those counted blocks into the SLC non-volatile
`memory module, [6.G.iii] wherein the counted
`blocks transferred to after reaching the
`predetermined count value are determined in
`accordance with the next equivalent range of
`physical addresses determined by the controller.” ...... 106
`X. OBJECTIVE INDICIA OF NON-OBVIOUSNESS .................................. 111
`XI. DECLARATION ........................................................................................ 112
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`5
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`I.
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`Declaration of Dr. David Liu
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`I, Dr. David Liu, hereby declare as follows:
`
`INTRODUCTION
`1.
`I have been retained Micron Technology, Inc. (“Micron”) as an
`
`independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office (“PTO”). I am not an employee of Micron or any affiliate
`
`or subsidiary of Micron.
`
`2.
`
`I have been asked to consider whether certain references teach or
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`suggest the features recited in certain claims of U.S. Patent No. 9,997,240, which I
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`refer to herein as the 240 patent, and whether certain claims of the 240 patent are
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`unpatentable as obvious.
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`3. My opinions and the bases for my opinions are set forth below.
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`4.
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`I am being compensated at $550 per hour for my work, plus
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`reimbursement for any reasonable expenses. My compensation is based solely on
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`the amount of time that I devote to activity related to this case and is in no way
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`contingent on the nature of my findings, the presentation of my findings in
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`testimony, or the outcome of this or any other proceeding. I have no other
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`financial interest in this proceeding.
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`II. EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS
`5. My curriculum vitae (“CV”) is attached hereto as Attachment A and
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`provides an accurate identification of my background and experience. Among
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`6
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`other things, my CV includes a list of my issued patents and publications for at
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`Declaration of Dr. David Liu
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`least the last 30 years. My curriculum vitae also includes information about my
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`expert witness experience, with case numbers where available.
`
`6.
`
`I received a Bachelor of Science in Electrical Engineering from the
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`University of California, Berkeley, in 1983. I received a Master of Science and
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`Ph.D. degrees in Electrical Engineering from Stanford University in 1985 and
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`1989, respectively.
`
`7.
`
`From 1989 to 1992, I was a member of technical staff at Texas
`
`Instruments, Inc. At Texas Instruments, my job responsibilities included process
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`integration, device modeling, high-voltage CMOS process integration, and
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`investigating novel source-side injection mechanisms for Flash EPROM channel
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`hot-electron programming.
`
`8.
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`From 1992 to 1995, I was a member of the technical staff at Advanced
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`Micro Devices, Inc. (AMD) where I was a key contributor in optimizing Flash cell
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`and periphery devices in AMD’s CMOS-based 0.5um and 0.35um Flash EPROM
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`technology. My job responsibilities at AMD also included process integration,
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`device modeling, and development of triple-well process technology for
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`accommodate x-decoder transistors and high voltage transistors for negative gate
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`erase operation. While at AMD, I was awarded a Spotlight Award for developing
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`7
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`Micron Ex. 1009, p. 7
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`a method of manufacturing a self-aligned source (SAS) etch for a NOR flash
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`Declaration of Dr. David Liu
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`memory.
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`9.
`
`I spent the next five years of my career in managerial and director
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`roles at several California-based semiconductor companies. I was responsible for
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`increasing yield and for leading teams of engineers working to develop next-
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`generation memory devices.
`
`10.
`
`In 2000, I co-founded Progressant Technologies in Fremont,
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`California. Progressant Technologies developed IP for negative differential
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`resistance transistor technology and was eventually acquired by Synopsys, Inc.
`
`11. From 2000 to 2004, I was a Senior Manager at Xilinx, Incorporated,
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`where I was responsible for developing nonvolatile memory process technology
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`for flash and CPLD product applications, as well as advanced CMOS process
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`technology (specifically 75nm CMOS technology node, a half node version
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`between 90nm and 65nm).
`
`12. From 2004 to 2007, I was a Senior Scientist at Maxim Integrated
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`Products where I was responsible for developing Embedded Non-volatile Memory
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`process technology for Power Management product applications.
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`13. Since 2007, I have served as a technical consultant where I have
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`provided expert advice regarding Flash memory technology, CMOS process
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`technology, and semiconductor device physics.
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`8
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`Micron Ex. 1009, p. 8
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`14.
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`I am not now, and have never been an employee of the Petitioner.
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`III. ASSIGNMENT AND MATERIALS CONSIDERED
`15.
`I have been asked to provide analysis and explain the subject matter of
`
`the 240 patent, including the state of the art when the 240 patent application was
`
`filed. I have also been asked to consider, analyze, and explain certain prior art to
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`the 240 patent including how that art relates to the challenged claims of the 240
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`patent and to provide my opinions regarding whether that art invalidates the
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`claimed subject matter.
`
`16. The opinions expressed in this declaration are not exhaustive of my
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`opinions regarding the unpatentability of the claims of the 240 patent. Therefore,
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`the fact that I do not address a particular point should not be understood to indicate
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`an agreement on my part that any claim complies with the requirements of any
`
`applicable patent or other rule.
`
`17.
`
`I reserve the right to amend and supplement this declaration in light of
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`additional evidence, arguments, or testimony presented during this IPR or related
`
`proceedings on the 240 patent.
`
`18.
`
`In forming the opinions set forth in this declaration, I have considered
`
`and relied upon my education, knowledge of the relevant field, knowledge of
`
`scientific and engineering principles, and my experience. I have also reviewed and
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`9
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`Micron Ex. 1009, p. 9
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`considered the 240 patent (Exhibit 1005), its prosecution history (Exhibit 1006),
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`Declaration of Dr. David Liu
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`and the following additional materials:
`
`Exhibit
`
`Description
`
`1010
`
`1011
`
`1012
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`U.S. Patent Application Publication No. 2011/0099460
`(“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`U.S. Patent Application Publication No. 2009/0327591
`(“Moshayedi”)
`
`Betty Prince, Semiconductor Memories – A Handbook of
`Design, Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617
`(“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
`
`U.S. Patent Application Publication No. 2011/0115192 (“Y.
`Lee”)
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601
`(“Gavens”)
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`10
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`Micron Ex. 1009, p. 10
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`Exhibit
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`Description
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`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1040
`
`1041
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`1042
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`1043
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`1047
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`1049
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`1055
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition,
`2006, definition of periodic
`
`New Oxford American Dictionary, 3rd Edition, 2010, definition
`of module
`
`U.S. Patent Application Publication No. 2010/0172180
`(“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650
`(“Chin”)
`
`European Patent Specification No. EP 2.291.746 B1 (“Radke”)
`
`U.S. Patent Application Publication No. 2015/0214476
`(“Matsui”)
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`U.S. Patent No. 5,936,971 (“Harari”)
`
`New Oxford American Dictionary, 3rd Edition, 2010,
`definitions of frequency and threshold
`
`11
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`IV. UNDERSTANDING OF THE LAW
`19.
`I am not an attorney, but have been instructed in and applied the law
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`Declaration of Dr. David Liu
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`as described in this section.
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`20.
`
`I understand that the first step in comparing an asserted claim to the
`
`prior art is for the claim to be properly construed. I address how a person of
`
`ordinary skill in the art would have understood the claims of the alleged invention
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`in Section IX below.
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`21.
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`I have been further instructed and understand that a patent claim is
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`unpatentable and invalid as obvious if the subject matter of the claim as a whole
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`would have been obvious to a person of ordinary skill in the art of the claimed
`
`subject matter as of the time of the invention at issue. I understand that when
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`assessing the obviousness of claimed subject matter, the following factors are
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`evaluated: (1) the scope and content of the prior art; (2) the difference or
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`differences between each claim of the patent and the prior art; and (3) the level of
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`ordinary skill in the art at the time the patent was filed.
`
`22.
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`I understand that claimed subject matter may be obvious in view of
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`more than one item of prior art. I understand, however, that it is not enough to
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`show simply that all the limitations of the claimed subject matter are spread
`
`throughout the prior art. Instead, for claimed subject matter to be obvious over
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`multiple references, there must be some reason or motivation for one of ordinary
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`12
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`skill in the art to combine the prior art references to arrive at the claimed subject
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`Declaration of Dr. David Liu
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`matter.
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`23.
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`I have been informed that, in seeking to determine whether an
`
`invention that is a combination of known elements would have been obvious to a
`
`person of ordinary skill in the art at the time of the invention, one must consider
`
`the references in their entirety to ascertain whether the disclosures in those
`
`references render the combination obvious to such a person.
`
`24.
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`I have been informed and understand that, while not required, the
`
`prior art references themselves may provide a teaching, suggestion, motivation, or
`
`reason to combine, but other times the motivation linking two or more prior art
`
`references is common sense to a person of ordinary skill in the art at the time of the
`
`invention.
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`25.
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`I understand that a particular combination may be proven obvious
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`merely by showing that it was obvious to try the combination. I have been
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`informed that, if a technique has been used to improve one device, and a person of
`
`ordinary skill in the art would recognize that it would improve similar devices in
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`the same way, using the technique is obvious unless its actual application is
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`beyond his or her skill.
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`26.
`
`I further understand that an obviousness analysis recognizes that
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`market demand, rather than scientific literature, often drives innovation, and that a
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`motivation to combine references also may be supplied by the direction of the
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`Declaration of Dr. David Liu
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`marketplace. For example, when there is a design need or market pressure to solve
`
`a problem and there are a finite number of identified, predictable solutions, a
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`person of ordinary skill has good reason to pursue the known options within his or
`
`her technical grasp because the result is likely the product not of innovation but of
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`ordinary skill and common sense.
`
`27.
`
`I have been informed that the combination of familiar elements
`
`according to known methods is likely to be obvious when it does no more than
`
`yield predictable results. Thus, where all of the elements of a claim are used in
`
`substantially the same manner, in devices in the same field of endeavor, the claim
`
`is likely obvious.
`
`28. Additionally, I understand that a patent is likely to be invalid for
`
`obviousness if a person of ordinary skill can implement a predictable variation or if
`
`there existed at the time of the invention a known problem for which there was an
`
`obvious solution encompassed by the patent’s claims. Therefore, when a work is
`
`available in one field of endeavor, design incentives and other market forces can
`
`prompt variations of it, either in the same field or a different one.
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`29.
`
`I further understand that combining embodiments related to each other
`
`in a single prior art reference would not ordinarily require a leap of inventiveness.
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`30.
`
`I also understand that one of ordinary skill in the art must have had a
`
`reasonable expectation of success when combining references for claimed subject
`
`matter to be obvious.
`
`31.
`
`I have been informed and I understand that factors referred to as
`
`“objective indicia of non-obviousness” or “secondary considerations” are also to
`
`be considered when assessing obviousness when such evidence is available. I
`
`understand that these factors can include: (1) commercial success; (2) long-felt but
`
`unresolved needs; (3) copying of the invention by others in the field; (4) initial
`
`expressions of disbelief by experts in the field; (5) failure of others to solve the
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`problem the claimed subject matter solved; and (6) unexpected results.
`
`32.
`
`I also understand that evidence of objective indicia of non-
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`obviousness must be commensurate in scope with the claimed subject matter. I
`
`further understand that there must be a relationship, sometimes referred to as a
`
`“nexus,” between any such secondary indicia and the claimed invention.
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`33. Finally, I have been informed that one cannot use hindsight to
`
`determine that an invention was obvious.
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`34.
`
`I provide my opinions in this declaration based on the guidelines set
`
`forth above.
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`V. LEVEL OF SKILL IN THE ART
`35.
`I have been informed and understand that the level of ordinary skill in
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`Declaration of Dr. David Liu
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`the relevant art at the time of the invention is relevant to inquiries such as the
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`meaning of claim terms, the meaning of disclosures found in the prior art, and the
`
`reasons one of ordinary skill in the art may have for combining references.
`
`36.
`
`I have been informed and understand that factors that may be
`
`considered in determining the level of ordinary skill include: (1) the education of
`
`the inventor; (2) the type of problems encountered in the art; (3) prior art solutions
`
`to those problems; (4) rapidity with which innovations are made; (5) sophistication
`
`of the technology; and (6) education level of active workers in the relevant field. I
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`have been further informed and understand that a person of ordinary skill in the art
`
`is also a person of ordinary creativity.
`
`37. A person of ordinary skill in the art (“POSA”) at the time of the
`
`alleged invention would have had at least a Bachelor of Science degree in electrical
`
`engineering, computer engineering, or a closely related field, along with at least 3-
`
`5 years of experience in the design of non-volatile memory devices. An individual
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`with an advanced degree in a relevant field would require less experience in the
`
`design of non-volatile memory devices.
`
`38.
`
`In view of my educational background (e.g. a Ph.D. in Electrical
`
`Engineering obtained in 1989) and decades of experience in the design of non-
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`volatile memories, as discussed in Section II, I was a person of more than the
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`Declaration of Dr. David Liu
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`ordinary level of skill in the art as of July 2011. My opinions herein, however,
`
`were formed considering the perspective of an ordinarily skilled artisan.
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`VI. THE 240 PATENT’S EFFECTIVE FILING DATE
`39.
`I understand that the application leading to the 240 patent was filed on
`
`November 24, 2015.
`
`40. Based on my review of the 240 patent, I note that it also refers to a
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`July 19, 2011 provisional application.
`
`41. For purposes of this declaration, I have been instructed to use July 19,
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`2011 as the effective filing date of the 240 patent. My opinions in this declaration
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`were formed from the perspective of a person of ordinary skill in the art as of July
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`19, 2011, including both the knowledge of a person of ordinary skill in the art at
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`that time as well as how a person of ordinary skill in the art would have understood
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`the prior art.
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`VII. THE 240 PATENT
`A. Technological Background
`1.
`Volatile, Non-volatile, and Flash Memory
`42. Computer system memory comes in several varieties. Generally,
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`computer memories store data (e.g., programs and user data) in what is known as
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`“binary” code, i.e., zeros and ones. In one of the simplest forms of memory, a
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`certain number of electrons may be stored on a capacitor to represent a binary 0
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`while a different number represents a binary 1. The number of electrons will
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`manifest themselves either as a distinct voltage level or current level that can be
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`obtained from the capacitor.
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`43. Memory may either be “volatile” or “non-volatile.” Volatile memory,
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`such as dynamic random access memory (DRAM), needs continuous power to
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`preserve stored data. That is, volatile memory loses its contents when the
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`computer’s power is turned off. Non-volatile memory (sometimes called NVM or
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`NV memory), such as Flash memory and disk drive storage, maintains its contents
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`when power is turned off. Unlike volatile memory, non-volatile storage does not
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`require a continuous availability of power in order to retain its data. See Ex. 1040,
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`Dipert & Levy at 21.
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`44. Flash memory has been a known memory type for several decades. It
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`is often found in USB flash drives, MP3 players, digital cameras, digital phones,
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`and more recently, in personal computers and servers. See Ex. 1018, Axelson at
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`17-18, 22-23. One early type of flash memory was known as electrically erasable
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`programmable read only memory (“EEPROM”). Flash has the advantage of being
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`a non-volatile memory, while also being able to be made smaller than traditional
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`non-volatile storage, e.g., disk drives. In addition, unlike disk drives, flash
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`memories do not have mechanical moving parts and thus are more able to
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`withstand sudden movement, making them better suited for portable devices.
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`45. As shown below, many flash memory cells use floating gate
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`transistors to store information.
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`See also, Ex. 1014, Prince at 54-55.
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`46. Other flash memory cells use what is known as “charge trap”
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`technology, which is a distinct but similar technology for storing charge in a flash
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`memory cell. Ex. 1019, Micheloni at 115. In both floating gate and charge trap
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`flash memory cells, the amount of charge stored in the cell represents information.
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`For example, a large amount of charge may represent a value of “0,” whereas a
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`small amount of charge may represent a value of “1.” Id. at 20.
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`2.
`SLC and MLC Flash Memory Cells
`47. The charge on the floating gate indicates the value that the cell stores
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`by affecting the threshold voltage of the memory cell. The threshold voltage of the
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`memory cell refers to the voltage at which the transistor will begin to conduct
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`substantial current across the channel. As described below, the threshold voltage
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`can be set such that the cell stores two values, i.e., either a 0 or 1 (single-level cell,
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`“SLC”) or such that the cell stores more than two values (multi-level cell, “MLC”).
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`For example, a multi-level cell may store two bits, representing four values, i.e.,
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`00, 01, 10, or 11.
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`48. A typical way to program a Flash cell is to apply a voltage pulse to the
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`control gate, and to place the source and drain at ground. Then, electrons will be
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`injected onto the floating gate. This adds charge to the floating gate and, therefore,
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`changes the threshold voltage of the memory cell. Ex. 1019, Micheloni at 24.
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`49. During programming, the device will periodically perform a verify
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`operation on the cells being programmed. Ex. 1019, Micheloni at 62. After the
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`floating gate has been programmed for a period of time, the device will read the
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`state of the memory cell and attempt to verify that it has been programmed to the
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`proper threshold voltage. If the memory cell is read at the proper state, then
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`programming is complete. If the memory cell does not verify to the proper state,
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`then the programming process is repeated.
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`50. Different threshold voltages can correspond to different memory
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`states or digital values. For example, if the memory cell has a threshold voltage of
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`0 volts, this may correspond to a logical high value, whereas a threshold voltage of
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`1 volt may correspond to a logical low value. The threshold voltage is
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`programmable to various threshold values and these memory states can be
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`associated with different logical values. SLC refers to Flash cells that have two
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`states, whereas MLC refers to Flash cells that have more than two states.
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`Ex. 1019, Micheloni at 5-6; Ex. 1015, Varkony at 3:4-7, 7:24-35.
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`51. Flash memory cells, however, “wear out,” i.e., after a certain number
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`of erase and program (write) operations, they become defective and, e.g., remain
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`“stuck” at a 0 or 1 value. E.g., Ex. 1019, Micheloni at 41; Ex. 1016, Friedman at
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`1:19-37. While in other memories, such as DRAM, memory cells also become
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`defective, the problem is a much bigger issue in flash memories. Techniques to
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`deal with this wear have been around, in effect, since the creation of flash
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`memories.
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`3.
`Flash Architecture
`52. Flash memory is organized into “blocks,” “pages,” and/or “sectors.”
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`Ex. 1019, Micheloni at 27. A block is the smallest erasable unit; an erase
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`operation must occur, at minimum, on an entire block, not a subset of the block. A
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`block is made up of multiple pages. A page is the smallest programmable or
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`writable unit; in a read or write operation, an entire page, not a subset of the page,
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`must be read or written. A page may be made up of one or more sectors. The host
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`(not the flash device) defines the size of the sector. Ex. 1041, Gorobets at 2:57-66.
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`53. The size of a block and of a page are often influenced by constraints
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`in the physical design of the memory. For example, blocks in flash memory tend
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`to be bigger than pages because the hardware required to erase a cell tends to be
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`bigger than the hardware required to write some number of cells. Thus, 2,048 cells
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`might share the same write hardware (and therefore be in the same page), whereas
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`128 pages might share the same erase hardware (and therefore be in the same
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`block). In the context of flash memories, a sector is often the same size as a page.
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`Ex. 1019, Micheloni at 40.
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`54. Flash memories typically comprise many blocks. Because there are
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`multiple blocks, each read and write operation requires both a block address and a
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`page address. An erase operation, on the other hand, requires only a block address,
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`because the