UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`
`Case No.: IPR2021-01547
`U.S. Patent No. 8,891,298
`Original Issue Date: November 18, 2014
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,891,298
`PURSUANT TO 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`III.
`
`V.
`
`I.
`II.
`
` Page
`TABLE OF CONTENTS
`INTRODUCTION ..............................................................................................1
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW .............2
` Grounds for Standing (37 C.F.R. § 42.104(a)) ........................................2
` Notice of Lead and Backup Counsel and Service Information
`(37 C.F.R. §§ 42.8(b)(3-4), 42.10(a)) ......................................................2
` Notice of Real Party-in-Interest (37 C.F.R. § 42.8(b)(1))........................4
` Notice of Related Matters (37 C.F.R. § 42.8(b)(2)) .................................4
`
`Fee for Inter Partes Review .....................................................................5
`
`Proof of Service ........................................................................................5
`IDENTIFICATION OF CLAIMS BEING CHALLENGED (37 C.F.R.
`§ 42.104(B)) ........................................................................................................5
`IV. THE BOARD SHOULD NOT EXERCISE ITS DISCRETION TO
`DENY INSTITUTION .......................................................................................7
`
`The Parallel District Court Litigation Does Not Weigh Against
`Institution ..................................................................................................7
`Petitioner’s Arguments Are Not Duplicative ........................................ 12
`
`THE 298 PATENT .......................................................................................... 13
`
`Technological Background ................................................................... 13
`1.
`Volatile, Non-volatile, and Flash Memory ................................. 13
`2.
`Programming Flash, and SLC and MLC Flash Memory
`Cells............................................................................................. 14
`Flash Architecture ....................................................................... 15
`Logical Addresses, Physical Addresses, Bad Block
`Replacement, and Wear Leveling ............................................... 16
`Speed and Wear-Leveling Considerations for MLC and
`SLC Cells .................................................................................... 17
`Data Integrity Tests ..................................................................... 18
`6.
`Summary of the 298 Patent’s Disclosure .............................................. 18
`The 298 Patent’s Prosecution History ................................................... 21
`
`3.
`4.
`
`5.
`
`
`
`
`-i-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`VI. CLAIM CONSTRUCTION ............................................................................ 21
`
`“data integrity test” (claim 1) ................................................................ 22
`B.
`“on a periodic basis” (claim 11) ............................................................ 23
` Other Terms ........................................................................................... 23
`VII. HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE ................. 23
`
`Prior Art Overview ................................................................................ 23
`1.
`Dusija .......................................................................................... 23
`2.
`Sutardja ....................................................................................... 25
`3. Moshayedi ................................................................................... 26
`4.
`Li ................................................................................................. 27
`Level of Ordinary Skill in the Art ......................................................... 27
`
` Ground 1: Dusija And Sutardja In View Of The Knowledge Of A
`POSA Renders Obvious Claims 1-5 And 11 ........................................ 27
`1.
`Claim 1 ........................................................................................ 28
`a.
`[1.PRE] “A system for storing data comprising:” ...................... 28
`b.
`[1.A] “at least one MLC non-volatile memory module
`comprising a plurality of individually erasable blocks;” ............ 29
`[1.B] “at least one SLC non-volatile memory module
`comprising a plurality of individually erasable blocks; and” ..... 31
`[1.C] “a controller coupled to the at least one MLC non-
`volatile memory module and the at least one SLC non-
`volatile memory module wherein the controller is adapted
`to:” ............................................................................................... 33
`[1.D] “maintain an address map of at least one of the MLC
`and SLC non-volatile memory modules, the address map
`comprising a list of logical address ranges accessible by a
`computer system, [1.D.ii.] the list of logical address ranges
`having a minimum quanta of addresses, [1.D.iii.] wherein
`each entry in the list of logical address ranges maps to a
`similar range of physical addresses within either the at least
`one SLC non-volatile memory module or within the at least
`one MLC non-volatile memory module;” .................................. 35
`
`d.
`
`c.
`
`e.
`
`-ii-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`f.
`
`g.
`
`[1.E] “[1.E.i] determine if a range of addresses listed by an
`entry and mapped to a similar range of physical addresses
`within the at least one MLC non-volatile memory module,
`fails a data integrity test, and, [1.E.ii] in the event of such a
`failure, the controller remaps the entry to the next available
`equivalent range of physical addresses within the at least
`one SLC non-volatile memory module;” .................................... 38
`[1.F] “determine which of the blocks of the plurality of the
`blocks in the MLC and SLC non-volatile memory modules
`are accessed most frequently by maintaining a count of the
`number of times each one of the blocks is accessed; and” ......... 42
`[1.G] “allocate those blocks that receive the most frequent
`writes by transferring the respective contents of those
`blocks to the at least one SLC non-volatile memory
`module.” ...................................................................................... 43
`Claim 2: “The system of claim 1, wherein the minimum
`quanta of addresses is equal to one block.” ................................ 45
`Claim 3: “The system of claim 1, wherein the minimum
`quanta of addresses is equal to one page.”.................................. 45
`Claim 4: “The system of claim 1, wherein the MLC non-
`volatile memory module is NAND flash memory.” ................... 46
`Claim 5: “The system of claim 1, wherein the SLC non-
`volatile memory module is NAND flash memory.” ................... 46
`Claim 11: “The system of claim 1, wherein the controller
`causes the transfer of content on a periodic basis.” .................... 46
`7. Motivation to Combine ............................................................... 48
` Ground 2: Dusija, Sutardja, And Li In View Of The Knowledge
`Of A POSA Renders Obvious Claims 8-9 Of The 298 Patent ............. 50
`Ground 3: Moshayedi In View Of Dusija And The Knowledge Of
`A POSA Render Obvious Claims 1-5 and 11 Of The 298 Patent ........ 51
`1.
`Claim 1 ........................................................................................ 52
`a.
`[1.PRE] “A system for storing data comprising:” ...................... 52
`b.
`[1.A] “at least one MLC non-volatile memory module
`comprising a plurality of individually erasable blocks;” ............ 52
`
`h.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`
`
`-iii-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`[1.B] “at least one SLC non-volatile memory module
`comprising a plurality of individually erasable blocks; and” ..... 54
`[1.C] “a controller coupled to the at least one MLC non-
`volatile memory module and the at least one SLC non-
`volatile memory module wherein the controller is adapted
`to:” ............................................................................................... 55
`[1.D] “maintain an address map of at least one of the MLC
`and SLC non-volatile memory modules, the address map
`comprising a list of logical address ranges accessible by a
`computer system, the list of logical address ranges having a
`minimum quanta of addresses, wherein each entry in the list
`of logical address ranges maps to a similar range of
`physical addresses within either the at least one SLC non-
`volatile memory module or within the at least one MLC
`non-volatile memory module;” ................................................... 58
`[1.E] “determine if a range of addresses listed by an entry
`and mapped to a similar range of physical addresses within
`the at least one MLC non-volatile memory module, fails a
`data integrity test, and, in the event of such a failure, the
`controller remaps the entry to the next available equivalent
`range of physical addresses within the at least one SLC
`non-volatile memory module;” ................................................... 60
`[1.F] “determine which of the blocks of the plurality of the
`blocks in the MLC and SLC non-volatile memory modules
`are accessed most frequently by maintaining a count of the
`number of times each one of the blocks is accessed” ................. 60
`[1.G] “allocate those blocks that receive the most frequent
`writes by transferring the respective contents of those
`blocks to the at least one SLC non-volatile memory
`module;” ...................................................................................... 62
`Claim 2: “The system of claim 1, wherein the minimum
`quanta of addresses is equal to one block.” ................................ 65
`Claim 3: “The system of claim 1, wherein the minimum
`quanta of addresses is equal to one page.”.................................. 65
`Claim 4: “The system of claim 1, wherein the MLC non-
`volatile memory module is NAND flash memory.” ................... 66
`
`c.
`
`d.
`
`e.
`
`f.
`
`g.
`
`h.
`
`2.
`
`3.
`
`4.
`
`-iv-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`6.
`
`
`
`5.
`
`Claim 5: “The system of claim 1, wherein the SLC non-
`volatile memory module is NAND flash memory.” ................... 66
`Claim 11: “The system of claim 1, wherein the controller
`causes the transfer of content on a periodic basis.” .................... 66
`7. Motivation to Combine ............................................................... 67
`Ground 4: Moshayedi In View Of Dusija, Sutardja And The
`Knowledge Of A POSA Renders Obvious Claim 11 Of The 298
`Patent ..................................................................................................... 70
`1.
`Claim 11: “The system of claim 1, wherein the controller
`causes the transfer of content on a periodic basis.” .................... 70
`2. Motivation to Combine ............................................................... 71
` Ground 5: Moshayedi, Dusija, And Li In View Of The
`Knowledge Of A POSA Renders Obvious Claims 8-9 Of The 298
`Patent ..................................................................................................... 72
`VIII. CONCLUSION ................................................................................................ 74
`
`-v-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) ............................... 8, 9, 10, 12
`Apple Inc. v. Maxell, Ltd.,
`IPR2020-00204, Paper 11, 15-17 (PTAB June 19, 2020) .................................. 11
`Juniper Networks, Inc. v. WSOU Investments LLC,
`IPR2021-00538, Paper 9, 13 (PTAB Aug. 18, 2021) ................................... 10, 12
`Nvidia Corp. v. Invensas Corp.,
`IPR2020-00603, Paper 11, 23 (PTAB Sept. 3, 2020)......................................... 11
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 21
`Sand Revolution II, LLC v. Continental Intermodal Grp. – Trucking
`LLC,
`IPR2019-01393, Paper 24, 11-12 (PTAB June 16, 2020) ............................ 11, 12
`Vervain, LLC v. Micron Technology, Inc.,
`Case No. 6:21-cv-00487 (W.D. Tex., filed May 10, 2021) ........................ 4, 8, 10
`Vervain, LLC v. Western Digital Corporation,
`Case No. 6:21-cv-00488 (W.D. Tex., filed May 10, 2021) .................................. 4
`Statutes
`35 U.S.C §§ 102(a), (b), and (e) ................................................................................ 6
`35 U.S.C. § 314(a) ..................................................................................................... 7
`35 U.S.C. § 314(a) and 325(d) ................................................................................... 5
`Other Authorities
`37 C.F.R. § 42.10(b) .................................................................................................. 4
`
`-vi-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`37 C.F.R. § 42.15(a) ................................................................................................... 5
`37 C.F.R. § 42.104(a) ................................................................................................. 2
`37 C.F.R. § 42.104(B) ................................................................................................ 5
`37 C.F.R. § 42.108(a) ................................................................................................. 5
`157 Cong. Rec. S5429 (Sept. 8, 2011) (statement of Sen. Kyl) ................................ 9
`
`-vii-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`LISTING OF EXHIBITS
`
`Exhibit
`
`Description
`
`1001
`
`1002
`
`U.S. Patent No. 8,891,298 to Rao (“298 patent”)
`
`File History of U.S. Patent No. 8,891,298
`
`1003-1008
`
`Intentionally omitted
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`Declaration of Dr. David Liu (“Liu Decl.”) - IPR2021-01547
`
`U.S. Patent Application Publication No. 2011/0099460
`(“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`U.S. Patent Application Publication No. 2009/0327591
`(“Moshayedi”)
`
`U.S. Patent No. 7,254,059 (“Li”)
`
`Betty Prince, Semiconductor Memories – A Handbook of
`Design, Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617
`(“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
`
`U.S. Patent Application Publication No. 2011/0115192 (“Y.
`Lee”)
`
`-viii-
`
`

`

`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601
`(“Gavens”)
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition,
`2006, definition of periodic
`
`New Oxford American Dictionary, 3rd Edition, 2010, definition
`of module
`
`U.S. Patent Application Publication No. 2010/0172180
`(“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650
`(“Chin”)
`
`European Patent Specification No. EP 2.291.746 B1 (“Radke”)
`
`U.S. Patent Application Publication No. 2015/0214476
`(“Matsui”)
`
`U.S. Patent Application Publication No. 2006/0053246
`(“S. Lee”)
`
`Complaint for Patent Infringement, Dkt. No. 1, Vervain, LLC v.
`Micron Technology, Inc., Micron Semiconductor Products,
`Inc., and Micron Technology Texas, LLC, Case No. 6:21-cv-
`00487-ADA (May 10, 2021 W.D. Tex.)
`
`-ix-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`Agreed Scheduling Order, Dkt. No. 24, dated September 16,
`2021, in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas,
`LLC, Case No. 6:21-cv-00487-ADA
`
`Vervain’s Preliminary Infringement Contentions, dated August
`6, 2021, in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas,
`LLC, Case No. 6:21-cv-00487-ADA
`
`Judge Albright, Order Governing Proceedings - Patent Cases
`(OGP 3.4), dated June 24, 2021
`
`Scott McKeown, “WDTX ‘Implausible Schedule’ & Cursory
`Markman Order Highlighted,” Ropes & Gray, Patents Post-
`Grant, Inside Views & News Pertaining to the Nation’s Busiest
`Patent Court, June 2, 2021
`
`Dani Kass, Judge Albright Now Oversees 20% of New U.S.
`Patent Cases, Law360, March 10, 2021
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`U.S. Patent Application Publication No. 2012/0311244
`(“Huang”)
`
`U.S. Patent Application Publication No. 2008/0082736
`(“Chow”)
`
`U.S. Patent No. 8,656,256 (“Weathers”)
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`1035
`
`1036
`
`1037
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`1044
`
`1045
`
`1046
`
`1047
`
`1048-1054
`
`Intentionally omitted
`
`-x-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`I.
`
`INTRODUCTION
`Petitioner Micron Technology, Inc. (“Micron” or “Petitioner”) respectfully
`
`requests inter partes review of claims 1-5, 8-9, and 11 (the “Challenged Claims”) of
`
`U.S. Patent No. 8,891,298 (Ex. 1001, “298 patent”) which, according to USPTO
`
`records, is assigned to Vervain, LLC (“Vervain” or “Patent Owner”). There is more
`
`than a reasonable likelihood that Petitioner will prevail with respect to at least one
`
`Challenged Claim.
`
`The 298 patent relates to flash memory devices that include both multi-level
`
`cell (MLC) and single-level cell (SLC) memory modules. Flash memory devices
`
`with both MLC and SLC were well known and understood long before the 298 patent
`
`was filed, and the 298 patent does not contend otherwise. Instead, the 298 patent
`
`purports to improve such known devices by moving data from MLC to SLC in two
`
`specified circumstances: (1) if the data fails a “data integrity test” (the “data integrity
`
`test limitation”); and (2) if the data in a block is one of the most frequently accessed
`
`blocks in the system (the “hot blocks limitation”). The 298 patent’s claims as
`
`initially filed, which recited just the data integrity test limitation (and other well-
`
`known limitations), were rejected as anticipated. The claims were allowed only after
`
`the hot blocks limitation was added.
`
`The Applicant did not disclose to the Examiner, nor did the Examiner cite,
`
`any of the asserted references, which, in combination, disclose both the data integrity
`
`-1-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`and hot blocks limitations. Specifically, Dusija teaches a “post-write” read operation
`
`in which, if too many errors are detected, data is “remapped” from MLC to SLC
`
`(data integrity limitation), while Sutardja and Moshayedi each disclose a flash
`
`memory device that maintains a write count to determine which blocks are most
`
`frequently accessed and transfers the most frequently accessed MLC blocks to SLC
`
`blocks (hot blocks limitation). Nor is any other claim limitation novel (as the
`
`Examiner correctly found).
`
`The 298 patent’s claims thus represent nothing more than the expected result
`
`of combining known techniques, with a reasonable expectation of success, for
`
`improving flash memory reliability. As such, Petitioner respectfully requests that
`
`the Board enter a final written decision finding that the Challenged Claims of the
`
`298 patent are not patentable.
`
`II.
`
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW
`Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioner certifies that the 298 patent is available for IPR and that Petitioner
`
`is not barred or estopped from requesting IPR of the Challenged Claims of the 298
`
`patent on the grounds identified herein.
`
`Notice of Lead and Backup Counsel and Service Information
`(37 C.F.R. §§ 42.8(b)(3-4), 42.10(a))
`Pursuant to 37 C.F.R. §§ 42.8(b)(3-4) and 42.10(a), Petitioner provides the
`
`following designation of Lead and Back-Up counsel:
`
`-2-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`Lead Counsel
`Jeremy Jason Lang
`Registration No. 73,604
`(jlang@orrick.com)
`
`Back-Up Counsel
`Jared Bobrow
`Pro Hac Vice to be submitted
`(jbobrow@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`T: 650-614-7400; F: 650-614-7401
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`T: 650-614-7400; F: 650-614-7401
`
`Parth Sagdeo
`Registration No. 71,275
`(psagdeo@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`222 Berkeley St.
`Suite 2000
`Boston, MA 02116
`T: 617-880-1800; F: 617-880-1801
`
`Christopher Childers
`Registration No. 75,237
`(cchilders@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1152 15th St. NW
`Washington, DC 20005
`T: 202-339-8441; F: 202-339-8500
`
`Petitioner consents to service by electronic mail at the following addresses:
`
`PTABDocketJ3B3@orrick.com, PTABDocketJJL2@orrick.com,
`
`PTABDocketP2S7@orrick.com, PTABDocketC4C8@orrick.com, and Micron-
`
`Vervain_OHS@orrick.com.
`
`-3-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`Pursuant to 37 C.F.R. § 42.10(b), Petitioner’s Power of Attorney is attached.
`
`Notice of Real Party-in-Interest (37 C.F.R. § 42.8(b)(1))
`Petitioner Micron Technology, Inc.—along with its subsidiaries—is the real
`
`party-in-interest.
`
`Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`According to USPTO assignment records, the 298 patent is currently assigned
`
`to Vervain. Vervain has asserted the 298 patent and U.S. Patent Nos. 9,196,385,
`
`9,997,240, and 10,950,300 against Petitioner in a co-pending litigation, Vervain,
`
`LLC v. Micron Technology, Inc., Case No. 6:21-cv-00487 (W.D. Tex., filed May 10,
`
`2021) (“Co-Pending Litigation”). Vervain also has asserted the 298 patent and U.S.
`
`Patent Nos. 9,196,385, 9,997,240, and 10,950,300 against Western Digital
`
`Corporation, Western Digital Technologies, Inc., and HGST, Inc. in Vervain, LLC
`
`v. Western Digital Corporation, Case No. 6:21-cv-00488 (W.D. Tex., filed May 10,
`
`2021) (“Western Digital Litigation”).
`
`In addition to this Petition, Petitioner is filing petitions for inter partes review
`
`of the three other asserted patents in the Co-Pending Litigation: Petition for Inter
`
`Partes Review of U.S. Patent No. 9,196,385, IPR2021-01548, Petition for Inter
`
`Partes Review of U.S. Patent No. 9,997,240, IPR2021-01549, and Petition for Inter
`
`Partes Review of U.S. Patent No. 10,950,300, IPR2021-01550.
`
`-4-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
`
`The Director and the Board should allow this Petition under 35 U.S.C.
`
`§ 314(a) and 325(d) and/or 37 C.F.R. § 42.108(a). See Section IV.
`
`Fee for Inter Partes Review
`The Director is authorized to charge the fee specified by 37 C.F.R. § 42.15(a),
`
`and any other required fees, to Deposit Account No. 15-0665.
`
`Proof of Service
`Proof of service of this Petition on the Patent Owner at the correspondence
`
`addresses of record for the 298 patent is attached.
`
`III.
`
`IDENTIFICATION OF CLAIMS BEING CHALLENGED (37 C.F.R.
`§ 42.104(B))
`Petitioner requests IPR of claims 1-5, 8-9, and 11.
`
`The 298 patent was filed on April 25, 2012. The patent also makes a facial
`
`claim of priority to a July 19, 2011 Provisional Application No. 61/509,257. 298
`
`patent, Cover. For purposes of this Petition only, it is assumed that the 298 patent’s
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`claims are entitled to the benefit of this July 19, 2011 date.
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`Petitioner’s grounds rely on the following references:
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`(1) U.S. Patent Application Publication No. 2011/0099460 (Ex. 1010,
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`“Dusija”): Dusija was filed on December 18, 2009. Dusija is prior art to the 298
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`patent under at least §§ 102(a) and (e).
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`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
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`(2) U.S. Patent Application Publication No. 2008/0140918 (Ex. 1011,
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`“Sutardja”): Sutardja was filed on December 7, 2007, and published on June 12,
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`2008. Sutardja is prior art to the 298 patent under at least §§ 102(a), (b), and (e).
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`(3) U.S. Patent Application Publication No. 2009/0327591 (Ex. 1012,
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`“Moshayedi”): Moshayedi was filed on June 25, 2009 and published on December
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`31, 2009. Moshayedi is prior art to the 298 patent under at least §§ 102(a), (b), and
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`(e).
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`(4) U.S. Patent No. 7,254,059 (Ex. 1013, “Li”): Li was filed on July 18, 2005,
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`and issued on August 7, 2007 and is therefore prior art under at least 35 U.S.C
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`§§ 102(a), (b), and (e).
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`Petitioner challenges the claims on the following grounds:
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`Ground 1: Claims 1-5 and 11 are obvious over Dusija and Sutardja in view
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`of the knowledge of a person of ordinary skill in the art (a “POSA”);
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`Ground 2: Claims 8-9 are obvious over Dusija, Sutardja, and Li in view of
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`the knowledge of a POSA;
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`Ground 3: Claims 1-5 and 11 are obvious over Moshayedi and Dusija in view
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`of the knowledge of a POSA;
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`Ground 4: Claim 11 is obvious over Moshayedi, Dusija, and Sutardja in view
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`of the knowledge of a POSA.
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`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
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`Ground 5: Claims 8-9 are obvious over Moshayedi, Dusija, and Li in view
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`of the knowledge of a POSA.
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`None of the references on which these grounds are based was cited or
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`discussed by the Examiner during prosecution of the 298 patent.
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`These grounds are supported by the declaration of Dr. David Liu (Ex. 1009,
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`“Liu Decl.”).
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`IV. THE BOARD SHOULD NOT EXERCISE ITS DISCRETION TO
`DENY INSTITUTION
`The Parallel District Court Litigation Does Not Weigh Against
`Institution
`Petitioner respectfully requests that the Board not exercise its discretion to
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`deny institution pursuant to 35 U.S.C. § 314(a). On May 10, 2021, Vervain sued
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`Micron, Micron Semiconductor Products, Inc., and Micron Technology Texas, LLC
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`in the Western District of Texas, asserting the 298 patent and three other patents.
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`Ex. 1034. Micron had no pre-suit notice of the 298 patent. Nevertheless,
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`approximately four and a half months later, Micron filed this Petition as well as
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`petitions on the three other asserted patents. At the time of filing this Petition, no
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`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
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`substantial litigation activity has occurred.1 On August 6, 2021, Vervain served its
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`preliminary infringement contentions, which identify the claims it is asserting.
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`Given that the Co-Pending Litigation is still in its very early stages, and discovery
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`has not commenced, Petitioner’s diligence weighs heavily in favor of institution.
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`Should Patent Owner argue that the Board should deny institution in its
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`discretion under the factors set forth in Apple Inc. v. Fintiv, Inc., IPR2020-00019,
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`Paper 11 (PTAB Mar. 20, 2020) (“the Fintiv factors”), and if the Board were to
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`entertain such an argument, Petitioner respectfully requests that it be afforded an
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`opportunity to submit a reply brief. In any event, the Board should not exercise its
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`discretion to deny this Petition.
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`First, doing so would unfairly close the Board’s doors to Petitioner. Micron
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`was extraordinarily diligent in analyzing the prior art and preparing this Petition
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`(along with three others) to file as early as it did.
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`Second, the Fintiv factors weigh in favor of institution. Under Fintiv factor three
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`(investment in the parallel proceeding), Fintiv notes: “[i]f the evidence shows that
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`the petitioner filed the petition expeditiously, such as promptly after becoming aware
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`1 On July 9, 2021, Micron filed a Rule 12(b)(6) Motion to Dismiss the Complaint
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`because the Complaint is devoid of any factual allegations that plausibly allege
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`infringement. The Court has not ruled on this motion.
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`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
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`of the claims being asserted, this fact has weighed against exercising the authority
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`to deny institution under NHK.” Apple v. Fintiv, IPR2020-00019, Paper 11, 11.
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`Here, Petitioner filed approximately four and a half months after receipt of the
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`complaint and approximately six weeks after infringement contentions were served
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`(which identified the asserted claims for the first time).2 Moreover, to date, no court
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`resources have been devoted to analyzing prior art, invalidity, or any other
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`substantive issue in this proceeding. No claim construction has occurred, a motion
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`to dismiss is pending, and there has been no meaningful fact or expert discovery.
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`When the Board issues its institution decision on this Petition, fact discovery will be
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`in its infancy. See Ex. 1035 (fact discovery to begin January 21, 2022 and close
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`August 12, 2022). Further, expert discovery is not to be completed until October 7,
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`2022. Id. And any district court claim construction proceedings that occur before
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`institution would add to the efficiency of this IPR proceeding because the parties
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`will submit any district court claim construction materials to the Board. On facts
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`nearly identical to these, the Board found this factor to weigh substantially against
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`exercising discretion to deny institution because “while the scheduled date for a
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`2 Denying institution would negate Congressional intent to “afford defendants a
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`reasonable opportunity to identify and understand the patent claims that are relevant
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`to the litigation.” 157 Cong. Rec. S5429 (Sept. 8, 2011) (statement of Sen. Kyl).
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`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
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`Markman hearing ha[d] passed, much of the invested effort [wa]s unconnected to
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`the patentability challenges.” Juniper Networks, Inc. v. WSOU Investments LLC,
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`IPR2021-00538, Paper 9, 13 (PTAB Aug. 18, 2021) (granting institution and stating
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`that “the substantial work that remains on invalidity issues in the parallel district
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`court litigation and Petitioner’s expeditious filing of its Petition substantially
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`outweighs the minimal investment so far”).
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`Under Fintiv factor six (other considerations), Fintiv notes that if the merits
`
`of the Petition are strong, which is the case here, institution of a trial may “serve the
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`interest of overall system efficiency and integrity because it allows the proceeding
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`to continue in the event that the parallel proceeding settles or fails to resolve the
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`patentability question presented in the PTAB proceeding.” Apple v. Fintiv,
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`IPR2020-00019, Paper 11, 15. Vervain has already brought two patent infringement
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`lawsuits against two memory manufacturers, and others are likely in line. What’s
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`more, Micron’s petition challenges more claims than Vervain is asserting in district
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`court, so an IPR trial will resolve issues that the parallel proceeding will not reach.
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`The fourth Fintiv factor (overlap of issues between the district court and IPR)
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`heavily favors institution. In the Co-Pending Litigation, Patent Owner asserts fewer
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`claims than this Petition challenges: Vervain does not assert claims 2, 8, or 9, though
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`this Petition challenges these claims. Compare Ex. 1036, 2, with Section III.
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`Moreover, should the Board institute an IPR proceeding on the 298 patent, Micron
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`Petition for Inter Partes Review of U.S. Patent No. 8,891,298
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`further stipulates that it will not pursue any instituted grounds as invalidity defenses
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`in the District Court, eliminating any overlap in issues. The Board has found that
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`such stipulations weigh in favor of institution. See Sand Revolution II, LLC v.
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`Continental Intermodal Grp. – Trucking LLC, IPR2019-01393