US007254059B2
`
`(12) United States Patent
`Li et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7.254,059 B2
`Aug. 7, 2007
`
`(54) MULTILEVEL PHASE-CHANGE MEMORY
`ELEMENT AND OPERATING METHOD
`
`(75) Inventors: Chien-Ming Li, Hsinchu (TW);
`Wen-Han Wang, Hsinchu (TW);
`Kuei-Hung Shen, Hsinchu (TW)
`
`(73) Assignee: Industrial Technology Research
`Institut, Hsinchu (TW)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`(21) Appl. No.: 11/182,783
`(22) Filed:
`Jul. 18, 2005
`(65)
`Prior Publication Data
`US 2006/007770.6 A1
`Apr. 13, 2006
`Foreign Application Priority Data
`(30)
`Oct. 8, 2004
`(TW) .............................. 931306OO A
`
`(51) Int. Cl.
`(2006.01)
`GIC II/34
`(52) U.S. Cl. .................................. 365/185.03:365/163
`(58) Field of Classification Search ................ 365/161,
`365/163, 185.03, 46, 148: 257/1, 2
`See application file for complete search history.
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`6,141.241 A * 10/2000 Ovshinsky et al. ......... 365,163
`
`6,339,544 B1* 1/2002 Chiang et al. .............. 365,163
`6,635,914 B2 10/2003 Kozicki et al. ...
`... 257,296
`7,106,623 B2 * 9/2006 Hung et al. ................. 365,163
`2005/0191804 A1* 9, 2005 Lai et al. .................... 438.238
`2006/0077741 A1* 4/2006 Wang et al. ......
`... 365.222
`2006/009 1374, A1
`5/2006 Yoon et al. .................... 257/2
`2006/0097239 A1* 5/2006 Hsiung .......................... 257/4
`2006,0166455 A1* 7, 2006 Gordon et al. .
`... 438,385
`2006/0226411 A1* 10/2006 Lee ............................... 257/2
`
`OTHER PUBLICATIONS
`
`Ed Spall, Ovonyx, "Ovonic Unified Memory.” Presentation to IEEE
`Electron Device Society, May 22, 2001.
`* cited by examiner
`Primary Examiner Anh Phung
`Assistant Examiner—Alexander Sofocleous
`(74) Attorney, Agent, or Firm—Rabin & Berdo, P.C.
`(57)
`ABSTRACT
`
`A multilevel phase change memory element and operating
`method and electrodes, which are configured in a parallel
`structure to form a memory cell. A Voltage-drive mode is
`employed to control and drive the memory element Such that
`multilevel memory states may be achieved by imposing
`different voltage levels. The provided multilevel phase
`change memory element has more bits and higher capacity
`than that of a memory element with a single phase-change
`layer.
`
`23 Claims, 13 Drawing Sheets
`
`
`
`10
`
`XXX.
`SSSSS
`
`S&S S&
`
`50 mm.
`
`20
`
`30
`
`60
`
`61
`
`Micron Ex. 1013, p. 1
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`U.S. Patent
`
`Aug. 7, 2007
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`Sheet 1 of 13
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`US 7.254,059 B2
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`
`
`42
`N
`41 Š
`
`2O
`
`1O
`
`50 U
`2
`2S2 60
`61
`
`S
`
`3O
`
`FIG. 1
`
`Micron Ex. 1013, p. 2
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 2 of 13
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`US 7.254,059 B2
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`70
`
`
`
`
`
`S
`VY&
`V X. NX
`XOS
`C
`S&S
`XXXXXXX
`
`&S:
`
`sex
`RX
`C
`X
`&S
`XXXXXXX
`
`2O
`
`30
`
`50
`
`61
`
`FIG. 2
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`Micron Ex. 1013, p. 3
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 3 of 13
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`US 7.254,059 B2
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`FIG. 3A ZNZ 1OO
`
`101
`
`ONOTE
`FIG. 3B 2N2-100
`S2
`
`FIG. 3C
`
`
`
`
`
`101
`
`s
`
`
`
`103
`102
`100
`
`103
`
`Š
`2s2 102
`ZNz1 100
`N2
`
`103A
`
`Š
`
`2 2 1OO 2N2
`
`101
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 4 of 13
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`US 7.254,059 B2
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`103B
`103A
`FIG. 3F N1 102
`Š
`ZNZ-1 100
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to
`FIG. 3G
`
`FIG. 3H
`
`
`
`104
`
`104
`
`104
`
`103A
`1O2
`100
`
`104
`
`105
`
`103A
`1 O2
`1OO
`
`104
`
`105
`
`
`
`101
`
`103A
`
`NN 102
`2N21 100
`
`101
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet S of 13
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`US 7.254,059 B2
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`FIG. 4A ZNZ
`
`Š
`2O2
`FIG. 4B zSz? 200
`
`2O3
`
`FIG. 4C
`
`204
`
`N TE
`Š
`Sz-- 200
`2N2
`
`201
`
`
`
`2O3
`
`204
`
`FIG. 4D Y-12
`ŽNZ1 200
`2
`
`201
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 6 of 13
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`US 7.254,059 B2
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`
`
`
`
`
`
`
`
`
`
`2O3
`FIG. 4E
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`2O3
`
`FIG.4F
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`208
`
`205
`
`205
`
`205
`
`:::::::::::::::
`
`
`
`204
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`Y ZNZ1 100
`
`101
`
`205
`
`2O7
`
`- 20
`ZN21 200
`
`204
`
`2O5
`% 2O7
`
`2O3
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`FIG, 4G
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`A-20?
`2N21 200
`
`2O4
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 7 of 13
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`US 7.254,059 B2
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`70
`
`10
`
`N
`k k 2O
`N
`
`30
`
`
`
`61
`
`FIG. 5A
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`70
`
`N
`
`2O
`
`30
`
`-
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`61
`
`FIG. 5B
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 8 of 13
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`US 7.254,059 B2
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`10
`
`50
`
`
`
`
`
`Y
`N
`
`y
`
`N
`2
`2
`
`2O
`
`30
`
`61
`
`FIG. 5C
`
`
`Y Y Y
`Y Y 2O
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`60
`
`61
`
`FIG. 5D
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`Micron Ex. 1013, p. 9
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 9 of 13
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`US 7.254,059 B2
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`3O
`S 25
`d
`cu
`20
`9.
`15
`H g 1O
`5
`
`O
`1
`
`
`
`3O
`
`25
`
`2O
`15
`
`1O
`
`
`
`1
`
`d
`
`g
`
`O
`D
`
`amorphization
`
`- - - - First material
`- Second material
`Crystallization
`
`1 OOOO
`1OOO
`100
`1O
`PULSE DURATION (ns)
`
`amorphization
`
`
`
`- - - - First material
`
`H Second material
`crystallization
`
`- - - - - -
`
`10
`
`100
`
`1OOO
`
`10OOO
`
`PULSE DURATION (ns)
`
`FIG. 6B
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 10 of 13
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`US 7.254,059 B2
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`
`
`3 O
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`2 5
`
`2 O
`
`
`
`
`
`amorphization
`
`
`
`
`
`ablation
`
`- - - - First material
`
`
`
`- Second material
`crystallization
`5
`O- - - -
`1
`1O
`1OO
`1000
`
`1 OOOO
`
`PULSE DURATION (ns)
`FIG. 6C
`
`amorphization
`
`
`
`- - - - First material
`
`-
`
`Second material
`
`s
`
`a a
`
`-s
`
`a
`
`1O
`1OO
`1OOO
`10OOO
`PULSE DURATION (ns)
`FIG. 6D
`
`
`
`
`
`2 O
`
`15
`
`1 O
`
`1
`
`Micron Ex. 1013, p. 11
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 11 of 13
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`US 7.254,059 B2
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`First state
`
`Second state
`
`- - - - - - - - - -
`88:
`
`- - - -
`
`--------------------- Third State
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`
`
`ReadOut Current
`
`
`
`Fourth state
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`
`
`Impose first control signal
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`Impose fourth control signal
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`Impose fourth control signal
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`Impose third control signal
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`
`
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`Impose third control signal
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`
`
`Impose first control signal
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`
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`
`
`Impose second control signal
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`
`
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`
`
`
`Impose first control signal
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`
`
`Impose second control signal
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`
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`
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`FIG. 7
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 12 of 13
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`US 7.254,059 B2
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`
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`Impose second control signal
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`Impose third control signal
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`Impose fourth control signal
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`Impose first control signal
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`Impose third control signal
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`Impose fourth control signal
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`ReadOut Current
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`Third
`State
`Fourth
`State
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`
`
`Impose first control signal
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`Impose first control signal
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`Impose fourth control signal
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`Impose second control signal
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`Impose third control signal
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`Impose second control signal
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`FIG. 8
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`U.S. Patent
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`Aug. 7, 2007
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`Sheet 13 of 13
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`US 7,254,059 B2
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`
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`FIG 10
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`US 7,254,059 B2
`
`1.
`MULTILEVEL PHASE-CHANGE MEMORY
`ELEMENT AND OPERATING METHOD
`
`This application claims the benefit of Taiwan Patent
`Application No. 93130600, filed on Oct. 8, 2004, which is
`hereby incorporated by reference for all purposes as if fully
`set forth herein.
`
`BACKGROUND OF THE INVENTION
`
`2
`of DRAM and SRAM), large capacity, high integrity, high
`environment endurance, long storage time, etc. Furthermore,
`operation Voltage is decreasing gradually. These memories
`may substitute Flash memory in the near future. Therefore,
`there is an urgent need for a new phase change memory
`element structure.
`
`SUMMARY OF THE INVENTION
`
`Accordingly, the invention relates to a multilevel phase
`change memory element, its manufacture method and its
`operating method that substantially solves the problems of
`the related art.
`An object of the invention is to provide a multilevel
`phase-change memory element, its manufacture method and
`its operating method having four memory states through one
`single memory cell.
`Another object of the invention is to provide a multilevel
`phase-change memory element, its manufacture method and
`its operating method, in which the memory cell is configured
`by two independent phase change units formed in parallel in
`order to obtain a memory cell with high density. The
`materials of the phase change units may be the same or
`different.
`Additional features and advantages of the invention will
`be set forth in the following description, and in part will be
`apparent from the description, or may be learned by practice
`of the invention. The objectives and other advantages of the
`invention will be realized and attained by the structure
`explained in the written description and claims hereof as
`well as the appended drawings.
`To achieve these and other advantages and in accordance
`with the purpose of the invention, as embodied and broadly
`described herein, a phase change memory element includes
`a first phase change layer having a crystalline state or an
`amorphous state; a second phase change layer having a
`crystalline state or an amorphous state; a first top electrode
`and a second top electrode formed on one surface of the first
`phase change layer and the second phase change layer
`respectively for delivering electrical signals to change the
`states of the first phase change layer and the second phase
`change layer, and at least one bottom electrode formed on
`another Surface of the first phase change layer and the
`second phase change layer.
`According to the object of the invention, the phase change
`memory element has the advantage of multilevel memory
`states in one single cell.
`According to the object of the invention, the phase change
`memory element has the advantage of definite reading
`separation for the multilevel memory states.
`According to the object of the invention, the phase change
`memory element has the advantage of transferring the
`memory state thorough one or two operation steps.
`Further scope of applicability of the invention will
`become apparent from the detailed description given here
`inafter. However, it should be understood that the detailed
`description and specific examples, while indicating embodi
`ments of the invention, are given by way of illustration only
`and are intended to provide further explanation of the
`invention as claimed, since various changes and modifica
`tions within the spirit and scope of the invention will become
`apparent to those skilled in the art from this detailed descrip
`tion.
`
`1. Field of Invention
`The invention relates to a semiconductor memory device,
`and more particularly to a semiconductor memory element
`with a multi-level memory state.
`2. Related Art
`Memory is widely used in general electric devices. Most
`are DRAM, SRAM, or Flash memory. Application and
`architecture of electric devices determine the usage of the
`memory and the required capacity. Development of memory
`technology, such as FeRAM, MRAM and phase change
`memory technology, is ongoing.
`A phase change semiconductor memory element stores
`data through resistance variation caused by phase change of
`materials. Regarding the phase materials, in the 1960s, S. R.
`Ovshinsky of the U.S. company ECD discovered that crys
`tallization and amorphization of chalcogenide has a distinct
`difference in optics and electrical conductivity. It is capable
`of fast reversible transformation and has Switching/memory
`application.
`A phase change memory element is called a semiconduc
`tor memory because chalcogenide belongs to the VIA group
`in the Periodic Table Of Elements, and is a semiconductive
`material between metals and nonmetals. Adding some ele
`ments is required for specific purposes in practical use, for
`example, increasing amorphization/crystallization speed, or
`crystallization characteristics.
`Phase change memories meet the need for large and fast
`storage operations and long storage time. It has the advan
`tages of Small volume, more storage data, and fast operation
`speed, and may store data more than ten years under 130°C.
`Therefore, a phase change memory element is a non-volatile
`memory element with great potential, having high read/write
`speed, high integrity, long endurance, low power consump
`tion, and radiation hardness. Main technology trends focuses
`on higher record density and low power consumption
`through reducing memory cells.
`However, besides increasing the memory density by
`reducing the area, multi-level/multi-state memory is another
`consideration. Thus, a single memory cell may have more
`than two memory states in the condition of not changing the
`component size.
`In the related art, Tyler Lowrey (Ovonyx Inc.) provides a
`multi-state structure in a published company technology
`document. A memory cell with a single phase change layer
`is employed to obtain multi levels with different resistant
`values by controlling the reset current. However, the solu
`tion may have the problem of Small current separation Such
`that writing error occurs due to the current offset.
`Also, U.S. Pat. No. 6,635,914 discloses a four level
`memory cell that belongs to the category of Programmable
`Metallization Cell Memory (PMCm). The cell is composed
`of a solid electrolyte layer and two electrodes. The conduc
`tivity of the solid electrolyte layer is changed by delivering
`an electrical field by the electrodes.
`Phase change memory, MRAM, and FRAM are the main
`memory technology trends, which have the advantages of
`being non-volatile, high speed (close to the operation speed
`
`10
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`15
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`US 7,254,059 B2
`
`3
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The accompanying drawings, which are included to pro
`vide a further understanding of the invention and are incor
`porated in and constitute a part of this specification, illustrate
`embodiments of the invention and together with the descrip
`tion serve to explain the principles of the invention. In the
`drawings:
`FIG. 1 is a structure diagram of the phase change memory
`element according to the invention;
`FIG. 2 is another structure diagram of the phase change
`memory element according to the invention;
`FIG. 3A-FIG. 3I illustrate the fabricating process of the
`phase change memory element according to the invention;
`FIG. 4A-FIG. 4G illustrate the fabricating process of the
`phase change memory element according to the invention;
`FIG. 5A-FIG.5D are the illustrative diagrams of the four
`memory states of the phase change memory element accord
`ing to the invention;
`FIG. 6A-FIG. 6D are the characteristic diagrams of the
`four memory states of the phase change memory element
`according to the invention;
`FIG. 7 illustrates the operation for memory state trans
`ferring of the phase change memory element according to
`the invention;
`FIG. 8 illustrates the operation for memory state trans
`ferring of the phase change memory element according to
`the invention; and
`FIGS. 9 and 10 show selecting elements connected to the
`phase change memory element according to the invention.
`
`10
`
`15
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`25
`
`30
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`4
`electrode 42 for delivering Voltage or current signals such
`that the first phase change layer 10 and the second phase
`change layer 20 are heated to change the State through the
`electrical signals; thereby controlling the operation of the
`phase change memory element in accordance with the
`invention.
`According to the principle of the invention, two phase
`change layers are employed and connected in parallel to
`form one single memory cell. Each phase change layer has
`a crystalline state and an amorphous state, which may be
`changed by heating. The first phase change layer 10 has a
`crystalline State and an amorphous state, while the second
`phase change layer 20 has a crystalline State and an amor
`phous state. Thus four states are formed when the two phase
`change layers are connected in parallel. The four states are
`referred as the first state, second state, third state and fourth
`state hereinafter. The conditions for the four states will be
`described in the following.
`The first phase change layer 10 and the second phase
`change layer 20 are different materials for phase change,
`which have distinct characteristics and preferably resistant
`differences. The crystallization and amorphization speed of
`the first phase change layer 10 and the second phase change
`layer 20 are also preferably different. For example, one of
`the two layers may employ a material with the characteris
`tics of low resistance, high crystallization temperature and
`fast crystallization speed, while the other may employ a
`material with the characteristics of high resistance, low
`crystallization temperature and slower crystallization speed.
`In one embodiment, the materials of the first phase change
`layer 10 and the second phase change layer 20 are different.
`In another embodiment, the two layers may adopt the same
`phase change material. The technological effect of the four
`memory states may be achieved by forming the two single
`phase change cells in parallel through an optimized struc
`tural design.
`For example, the first phase change layer 10 may employ
`doped eutectic SbTe, AgInSbTe or GenSbTe. The second
`phase change layer 20 may employ GeSbTe compounds
`such as GeSbTes. The aforementioned materials are for
`illustration only, and are not intended to limit the composi
`tion of the invention. Two phase change layers with different
`resistant variations and crystallization/amorphization speeds
`may be obtained by changing the composition of the phase
`change layers, adjusting the thickness of the phase change
`layers, changing the top electrodes types and contact areas,
`or forming functional layers between the phase change
`layers and the top electrodes.
`The bottom electrode 30 not only connects the first phase
`change layer 10 and the second phase change layer 20 for
`conducting, but also helps heat sink. The material with stable
`chemical characteristics (not reacting with the phase change
`layers) and high heat conductivity may be employed, for
`example, TiN.
`The materials of the first top electrode 41 and the second
`top electrode 42 may be the same as that of the bottom
`electrode 30. In one embodiment, for simplifying the fab
`ricating process, the materials of the first top electrode 41
`and the second top electrode 42 may be the same as that of
`the bottom electrode 30. In another embodiment, the size of
`the first top electrode 41 and the second top electrode 42
`may be the same. In yet another embodiment, the size of the
`first top electrode 41 and the second top electrode 42 may be
`different. The size of the electrodes is adjusted to control the
`heating efficiency.
`According the principle of the invention, in one embodi
`ment, a functional layer 80 is optionally formed between the
`
`35
`
`45
`
`Reference will now be made in detail to an embodiment
`of the invention, examples of which are illustrated in the
`accompanying drawings. Reference in the specification to
`“one embodiment' or “an embodiment’ means that a par
`ticular feature, structure, or characteristic described in con
`nection with the embodiment is included in at least one
`40
`embodiment of the invention. The appearances of the phrase
`“in one embodiment” in various places in the specification
`are not necessarily all referring to the same embodiment.
`Refer to FIG. 1, which illustrates the structure of the phase
`change memory element of the invention. In the embodi
`ment, the phase change memory element includes a first
`phase change layer 10, a second phase change layer 20, a
`bottom electrode 30, a first top electrode 41 and a second top
`electrode 42. The first phase change layer 10 and the second
`phase change layer 20 are formed on the bottom electrode 30
`by a semiconductor process. The first top electrode 41 is
`formed on the first phase change layer 10 by a semiconduc
`tor process. The second top electrode 42 is formed on the
`second phase change layer 20 by a semiconductor process.
`In another embodiment, a protection layer 50 is formed
`from dielectric material by a semiconductor process to cover
`and protect the first phase change layer 10, the second phase
`change layer 20, the bottom electrode 30, the first top
`electrode 41 and the second top electrode 42. In another
`embodiment, the bottom electrode 30 is formed on a sub
`strate 60, in which a metal contact 61 is formed for con
`necting to a selecting element. which may be a MOSFET
`110 or a diode 120 (see FIGS. 9 and 10) needed for
`operation. The substrate 60 is formed in the former process
`for COMS or Bipolar transistors. In another embodiment, a
`metal line 70 is formed on the protection layer 50 and makes
`contact with the first top electrode 41 and the second top
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`US 7,254,059 B2
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`first top electrode 41 and the first phase change layer 10 or
`the second top electrode 42 and the second phase change
`layer 20. As illustrated in FIG. 2, the functional layer 80 may
`be arranged with one or both layers. In one embodiment, the
`functional layer 80 may be a heating layer for increasing
`heating efficiency. In another embodiment, the functional
`layer 80 may be a nucleation accelerating layer for accel
`erating crystallization speed of the first phase change layer.
`In yet another embodiment, the functional layer 80 may be
`a diffusion stop layer for preventing diffusion between the
`first phase change layer and the first top electrode. The
`material of the functional layer 80 may employ refractory
`metal, conductible metallic carbide, intermetallic carbide,
`metallic nitride, intermetallic nitride, metallic carbonitrid, or
`intermetallic carbonitride. The functional layer 80 may have
`one, two or all functions listed above according the charac
`teristics of the materials.
`In one embodiment, the provided phase change memory
`element selects the cell to be written in or read out through
`a selecting element, which may be, for example, MOSFET
`110, or diode 120, or BJT, The transistor connects with the
`bottom electrode 30 through the metal contact 61. Sufficient
`heat for phase change of the first phase change layer 10 and
`the second phase change layer 20 is generated by imposing
`voltages on the heater, or the first top electrode 61 and the
`second top electrode 30. Then the signals are delivered to the
`receiving ends and sensing amplifier through the top and
`bottom electrodes. According to the principle of the inven
`tion, the operation of the multilevel phase change memory
`element is controlled by imposing Voltages and imposing
`time.
`Refer to FIGS. 3A-3I, which illustrate the fabricating
`process of the phase change memory element according to
`the invention. In the embodiment, the phase change layers
`employ the same material. Composition of one of the phase
`change layers is converted by ion implantation.
`A substrate 100, in which a metal contact 101 is formed,
`is provided in the former manufacturing process for CMOS
`or bipolar. Abottom electrode 102 is formed on the substrate
`40
`100. Then the phase change layer 103 is deposited and the
`bottom electrode 102 and the phase change layer 103 is
`etched, as shown in FIGS. 3A-FIG. 3B. The phase change
`layer 103, for example, may employ eutectic SbTehaving 16
`at. 96-37 at. '% composition of Te.
`Then, one portion of the phase change layer 103 is ion
`implanted to change the chemical composition. The
`implanted elements include III A group, IVA group, VA
`group, VIA group and rare-earth transition metals. After
`implanting, a first phase layer 103A and a second phase
`change layer 103B are formed, which are connected with
`each other, as illustrated in FIG. 3E.
`The phase change layer 103 (first phase change layer
`103A and second phase change layer 103B which are
`connected with each other) is etched to separate the first
`phase change layer 103A and the second phase change layer
`103B, as illustrated in FIG. 3F.
`Adielectric layer 104 is then deposited for protection. The
`first top electrode 105 and the second top electrode 106 are
`deposited through masking and etching processes, as illus
`trated in FIGS. 3G-FIG. 3H. The Surface of the dielectric
`layer 104 is polished and then deposited with a metal line
`107, as illustrated in FIG. 31. In one embodiment, the size
`of the first top electrode 105 and the second top electrode
`106 is the same. In another embodiment, the size of the first
`top electrode 105 and the second top electrode 106 is
`different.
`
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`6
`In another embodiment, a functional layer (referred to as
`the functional layer 80 in FIG. 2) may be formed between
`the first top electrode 105 and the first phase change layer
`103A. The functional layer may be a heating layer for
`increasing heating efficiency, a nucleation accelerating layer
`for accelerating crystallization speed of the first phase
`change layer, a diffusion stop layer for preventing diffusion
`between the first phase change layer and the first top
`electrode or any combination of these layers. This functional
`layer is also optionally formed between the second top
`electrode 106 and the second phase change layer 103B. It is
`noted that one or two functional layers may be adopted.
`Refer to FIG. 4, which illustrates the fabricating process
`of the phase change memory element according to the
`invention. In the embodiment, the phase change layers
`employ different materials.
`A substrate 200, in which a metal contact 201 is formed,
`is provided in the former manufacturing process for CMOS
`or bipolar. Abottom electrode 202 is formed on the substrate
`200. The first phase change layer 203 and the second phase
`change layer 204 are then deposited, as shown in FIGS. 4A
`and FIG. 4D. The materials of the phase change layers may
`employ doped eutectic SbTe or GeSbTe compounds. In one
`embodiment, the thickness of the first phase change layer
`203 and the second phase change layer 204 may be the same.
`In another embodiment, the thickness of the first phase
`change layer 203 and the second phase change layer 204
`may be different.
`A dielectric layer 205 is then deposited for protection. The
`first top electrode 206 and the second top electrode 207 are
`deposited through masking and etching processes, as illus
`trated in FIG. 4E-FIG. 4F. The surface of the dielectric layer
`205 is polished and then deposited with a metal line 208, as
`illustrated in FIG. 4G. In one embodiment, the size of the
`first top electrode 206 and the second top electrode 207 is the
`same. In another embodiment, the size of the first top
`electrode 206 and the second top electrode 207 is different.
`In another embodiment, a functional layer (referred to as
`the functional layer 80 in FIG. 2) may be formed between
`the first top electrode 206 and the first phase change layer
`203. The functional layer may be a heating layer, a nucle
`ation accelerating layer for accelerating crystallization speed
`of the first phase change layer, a diffusion stop layer for
`preventing diffusion between the first phase change layer
`and the first top electrode or any combination of these layers.
`This functional layer is also optionally formed between the
`second top electrode 207 and the second phase change layer
`204. It is noted that one or two functional layers may be
`adopted.
`The operation of the phase change memory element in
`accordance with the invention is illustrated as follows. Refer
`to FIGSA to FIG.SD.
`The phase change memory element in accordance with
`the invention employs a Voltage-drive mode in operation.
`The first phase change layer 10 and the second phase change
`layer 20 are heated by imposing different voltages on the
`first top electrode 41 and the second top electrode 42. Then
`the first phase change layer 10 and the second phase change
`layer 20 generate Zero, one, or two amorphous Volumes
`because of the material characteristics. In the invention, two
`amorphous Volumes are referred as the fourth State; an
`amorphous Volume is referred as the second State and third
`state; no amorphous volume is referred as the first state. The
`schematic diagram of all the states is illustrated in FIG.
`5A-FIG. 5D. The phase change layer with amorphous
`volumes has the highest resistance. Therefore, the parallel
`resistance of the fourth state is the highest; the second
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`7
`highest is the third state, the third highest is the second state
`and the first state's resistance is lowest. Four resistance
`levels correspond to four memory states, thereby achieving
`four memory states.
`According to the principle of the invention, the physical
`parameters of the materials of the first phase change layer 10
`and the second phase change layer 20 are provided in
`TABLE I, in which the first material is applied for the first
`phase change layer 10, while the second material is applied
`for the second phase layer 20, or vice versa.
`The materials listed hereinafter are exemplary and
`explanatory and are not intended to limit the materials for
`the phase change memory element of the invention. There
`fore, people skilled in the related art may obtain a phase
`change memory element with four memory states through
`selecting proper materials.
`
`TABLE I
`
`SECOND
`FIRST
`MATERIAL MATERIAL
`
`Crystallization resistance (S.2-cm)
`Amorphization resistance (S2-cm)
`Crystallization Temperature (C.)
`Melting point (C.)
`Specific heat (J/cmK)
`Thermo-conductivity coefficient (W/cmK)
`
`5 x 10
`50
`190
`570
`~1.0
`O.17
`
`1 x 102
`100
`150
`610
`~1.0
`O.14
`
`The amorphous volumes of the first material and the
`second material are supposed to be the same. The ratio of the
`thickness and the crystallized area is 1:9. The size of the
`heating electrodes is the same. The total resistance for each
`state is estimated as follows.
`FIRST STATE
`The first phase change layer and the second phase change
`layer crystallize.
`1/R 1=1/(5x10-3)x10+1/(1x10-2)x1O-30,
`R1 =O.O3
`
`SECOND STATE
`The first phase change layer crystallizes, and the second
`phase change layer amorphizes.
`1/R2=1/(5x10-3)x10+1/100x1+(1x10-2)x9-20,
`R2=O.OS
`THIRD STATE
`The first phase change layer amorphizes, and the second
`phase change layer crystallizes.
`1/R3=1/50x1+(5x10-3)x9+1/(1x10-2)x10-10,
`R3=0.1
`FOURTH STATE
`The first phase change layer and the second phase change
`layer amorphize.
`
`From the estimation, the total resistance is determined by
`the resistance of the amorphized area. The total current is
`I4=0.03V. I3=10V. I2=20V, and I1=30V, respectively, when
`imposing Voltage V. Therefore, the memory state may be
`determined by reading out the current of the memory.
`Refer to FIGS. 6A to 6D for the characteristic curves of
`the supposed conditions listed above. Areas I, II, III, and IV
`in the figures may be obtained by selecting proper materials
`or adjusting sizes of the structures.
`A Voltage pulse test of single phase change cell is con
`ducted for the first material and the second material. The
`conditions for amorphization and crystallization may be
`
`US 7,254,059 B2
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`8
`obtained by modulating Voltage (V) and time (t). A crystal
`lized cell is employed for an amorphization test, while a
`written cell is employed for a crystallization test. The test
`results are shown in the V-t diagram, which has an amor
`phization area, a crystallization area, and an ablation area.
`The amorphization area and the crystallization area of each
`phase change material may be adjusted to not totally overlap
`by adjusting the structural parameters of the memory cell.
`Thus, there are multiple correspondent relationships accord
`ing to different phase change materials. For example, a
`higher crystallization temperature has a higher bottom edge
`of the crystallization area; a higher melting point has a
`higher bottom edge of the amorphization area; a faster
`crystallization speed has a front edge of the crystallization
`area and the amorphization area.
`When two memories are connected in parallel and the
`Voltage pulse (V, t) falls in the overlapped amorphization
`area (AREA IV), each phase change layer has an amorphous
`volume. When the voltage pulse (V, t) falls in the amor
`phization area of the first material and does not overlap with
`the amorphization area of the second material (AREA III),
`the first phase change layer has an amorphous Volume while
`the second phase change layer does not act. When the
`voltage pul