`
`
`
`Declaration of Dr. David Liu
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`VERVAIN,LLC,
`Patent Owner
`
`
`
`
`Case No.: IPR2021-01547
`U.S. Patent No. 8,891,298
`Original Issue Date: November 18, 2014
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`
`
`
`
`DECLARATION OF DR. DAVID LIU
`
`
`1
`
`Micron Ex. 1009, p. 1
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`
`Declaration of Dr. David Liu
`
`I.
`II.
`
`Page
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 6 
`EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS ............................................................... 6 
`III. ASSIGNMENT AND MATERIALS CONSIDERED .................................. 9 
`IV. UNDERSTANDING OF THE LAW ........................................................... 12 
`V.
`LEVEL OF SKILL IN THE ART ................................................................ 16 
`VI. THE 298 PATENT’S EFFECTIVE FILING DATE ................................... 17 
`VII. THE 298 PATENT ....................................................................................... 17 
`A.
`Technological Background ................................................................ 17 
`1.
`Volatile, Non-volatile, and Flash Memory .............................. 17 
`2.
`SLC and MLC Flash Memory Cells ........................................ 20 
`3.
`Flash Architecture .................................................................... 21 
`4.
`Logical Addresses, Physical Addresses, Bad Block
`Replacement, and Wear Leveling ............................................ 24 
`Caching .................................................................................... 32 
`Speed and Durability Considerations for MLC and SLC
`Cells.......................................................................................... 33 
`Data Integrity Tests .................................................................. 34 
`7.
`Summary of the 298 Patent’s Disclosure ........................................... 35 
`B.
`The 298 Patent’s Prosecution History ................................................ 37 
`C.
`VIII. CLAIM CONSTRUCTION ......................................................................... 37 
`A.
`“data integrity test” (claim 1) ............................................................. 39 
`B.
`“on a periodic basis” (claim 11) ......................................................... 40 
`C. Other Terms ........................................................................................ 40 
`IX. HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE .............. 41 
`A.
`Prior Art Overview ............................................................................. 41 
`1.
`Dusija ....................................................................................... 41 
`2.
`Sutardja .................................................................................... 44 
`
`5.
`6.
`
`2
`
`Micron Ex. 1009, p. 2
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Declaration of Dr. David Liu
`
`3.
`
`4.
`
`5.
`
`6.
`
`3. Moshayedi ................................................................................ 45 
`4.
`Li .............................................................................................. 46 
`B. Ground 1: Dusija And Sutardja In View Of The Knowledge Of
`A POSA Renders Obvious Claims 1-5 And 11 Of The 298
`Patent .................................................................................................. 46 
`2.
`Claim 2: “The system of claim 1, wherein the minimum
`quanta of addresses is equal to one block.” ............................. 72 
`Claim 3: “The system of claim 1, wherein the minimum
`quanta of addresses is equal to one page.” ............................... 72 
`Claim 4: “The system of claim 1, wherein the MLC non-
`volatile memory module is NAND flash memory.” ................ 73 
`Claim 5: “The system of claim 1, wherein the SLC non-
`volatile memory module is NAND flash memory.” ................ 74 
`Claim 11: “The system of claim 1, wherein the controller
`causes the transfer of content on a periodic basis.” ................. 74 
`7. Motivation to Combine ............................................................ 76 
`C. Ground 2: Dusija, Sutardja, And Li In View Of The Knowledge
`Of A POSA Renders Obvious Claims 8-9 Of The 298 Patent .......... 80 
`D. Ground 3: Moshayedi In View Of Dusija And The Knowledge
`Of A POSA Render Obvious Claims 1-5 And 11 Of The 298
`Patent .................................................................................................. 82 
`1.
`Claim 1 ..................................................................................... 82 
`a.
`[1.PRE] “A system for storing data comprising:” ......... 82 
`b.
`[1.A] “at least one MLC non-volatile memory
`module comprising a plurality of individually
`erasable blocks;” ............................................................ 83 
`[1.B] “at least one SLC non-volatile memory
`module comprising a plurality of individually
`erasable blocks; and” ..................................................... 85 
`[1.C] “a controller coupled to the at least one MLC
`non-volatile memory module and the at least one
`SLC non-volatile memory module wherein the
`controller is adapted to:” ................................................ 87 
`
`c.
`
`d.
`
`3
`
`Micron Ex. 1009, p. 3
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Declaration of Dr. David Liu
`
`e.
`
`f.
`
`[1.D] “maintain an address map of at least one of
`the MLC and SLC non-volatile memory modules,
`the address map comprising a list of logical
`address ranges accessible by a computer system,
`the list of logical address ranges having a
`minimum quanta of addresses, wherein each entry
`in the list of logical address ranges maps to a
`similar range of physical addresses within either
`the at least one SLC non-volatile memory module
`or within the at least one MLC non-volatile
`memory module;” .......................................................... 89 
`[1.E] “determine if a range of addresses listed by
`an entry and mapped to a similar range of physical
`addresses within the at least one MLC non-volatile
`memory module, fails a data integrity test, and, in
`the event of such a failure, the controller remaps
`the entry to the next available equivalent range of
`physical addresses within the at least one SLC
`non-volatile memory module;” ...................................... 93 
`[1.F] “determine which of the blocks of the
`plurality of the blocks in the MLC and SLC non-
`volatile memory modules are accessed most
`frequently by maintaining a count of the number of
`times each one of the blocks is accessed” ..................... 93 
`[1.G] “allocate those blocks that receive the most
`frequent writes by transferring the respective
`contents of those blocks to the at least one SLC
`non-volatile memory module;” ...................................... 96 
`Claim 2: “The system of claim 1, wherein the minimum
`quanta of addresses is equal to one block.” ........................... 101 
`Claim 3: “The system of claim 1, wherein the minimum
`quanta of addresses is equal to one page.” ............................. 101 
`Claim 4: “The system of claim 1, wherein the MLC non-
`volatile memory module is NAND flash memory.” .............. 103 
`Claim 5: “The system of claim 1, wherein the SLC non-
`volatile memory module is NAND flash memory.” .............. 103 
`
`g.
`
`h.
`
`2.
`
`3.
`
`4.
`
`5.
`
`4
`
`Micron Ex. 1009, p. 4
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Declaration of Dr. David Liu
`
`6.
`
`Claim 11: “The system of claim 1, wherein the controller
`causes the transfer of content on a periodic basis.” ............... 103 
`7. Motivation to Combine .......................................................... 105 
`Ground 4: Moshayedi In View Of Dusija, Sutardja And The
`Knowledge Of A POSA Renders Obvious Claim 11 Of The 298
`Patent ................................................................................................ 108 
`1.
`Claim 11: “The system of claim 1, wherein the controller
`causes the transfer of content on a periodic basis.” ............... 109 
`2. Motivation to Combine .......................................................... 110 
`Ground 5: Moshayedi, Dusija, And Li In View Of The
`Knowledge Of A POSA Renders Obvious Claims 8-9 Of The
`298 Patent ......................................................................................... 112 
`X. OBJECTIVE INDICIA OF NON-OBVIOUSNESS .................................. 114 
`XI. DECLARATION ........................................................................................ 115 
`
`
`
`E.
`
`F.
`
`
`
`5
`
`Micron Ex. 1009, p. 5
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`I.
`
`Declaration of Dr. David Liu
`
`I, Dr. David Liu, hereby declare as follows:
`
`INTRODUCTION
`1.
`I have been retained by Micron Technology, Inc. (“Micron”) as an
`
`independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office (“PTO”). I am not an employee of Micron or any affiliate
`
`or subsidiary of Micron.
`
`2.
`
`I have been asked to consider whether certain references teach or
`
`suggest the features recited in certain claims of U.S. Patent No. 8,891,298, which I
`
`refer to herein as the 298 patent, and whether certain claims of the 298 patent are
`
`unpatentable as obvious.
`
`3. My opinions and the bases for my opinions are set forth below.
`
`4.
`
`I am being compensated at $550 per hour for my work, plus
`
`reimbursement for any reasonable expenses. My compensation is based solely on
`
`the amount of time that I devote to activity related to this case and is in no way
`
`contingent on the nature of my findings, the presentation of my findings in
`
`testimony, or the outcome of this or any other proceeding. I have no other
`
`financial interest in this proceeding.
`
`II. EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS
`5. My curriculum vitae (“CV”) is attached hereto as Attachment A and
`
`provides an accurate identification of my background and experience. Among
`
`6
`
`Micron Ex. 1009, p. 6
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`other things, my CV includes a list of my issued patents and publications for at
`
`Declaration of Dr. David Liu
`
`least the last 30 years. My curriculum vitae also includes information about my
`
`expert witness experience, with case numbers where available.
`
`6.
`
`I received a Bachelor of Science in Electrical Engineering from the
`
`University of California, Berkeley, in 1983. I received a Master of Science and
`
`Ph.D. degrees in Electrical Engineering from Stanford University in 1985 and
`
`1989, respectively.
`
`7.
`
`From 1989 to 1992, I was a member of technical staff at Texas
`
`Instruments, Inc. At Texas Instruments, my job responsibilities included process
`
`integration, device modeling, high-voltage CMOS process integration, and
`
`investigating novel source-side injection mechanisms for Flash EPROM channel
`
`hot-electron programming.
`
`8.
`
`From 1992 to 1995, I was a member of the technical staff at Advanced
`
`Micro Devices, Inc. (AMD) where I was a key contributor in optimizing Flash cell
`
`and periphery devices in AMD’s CMOS-based 0.5um and 0.35um Flash EPROM
`
`technology. My job responsibilities at AMD also included process integration,
`
`device modeling, and development of triple-well process technology for
`
`accommodate x-decoder transistors and high voltage transistors for negative gate
`
`erase operation. While at AMD, I was awarded a Spotlight Award for developing
`
`7
`
`Micron Ex. 1009, p. 7
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`a method of manufacturing a self-aligned source (SAS) etch for a NOR flash
`
`Declaration of Dr. David Liu
`
`memory.
`
`9.
`
`I spent the next five years of my career in managerial and director
`
`roles at several California-based semiconductor companies. I was responsible for
`
`increasing yield and for leading teams of engineers working to develop next-
`
`generation memory devices.
`
`10.
`
`In 2000, I co-founded Progressant Technologies in Fremont,
`
`California. Progressant Technologies developed IP for negative differential
`
`resistance transistor technology and was eventually acquired by Synopsys, Inc.
`
`11. From 2000 to 2004, I was a Senior Manager at Xilinx, Incorporated,
`
`where I was responsible for developing nonvolatile memory process technology
`
`for flash and CPLD product applications, as well as advanced CMOS process
`
`technology (specifically 75nm CMOS technology node, a half node version
`
`between 90nm and 65nm).
`
`12. From 2004 to 2007, I was a Senior Scientist at Maxim Integrated
`
`Products where I was responsible for developing Embedded Non-volatile Memory
`
`process technology for Power Management product applications.
`
`13. Since 2007, I have served as a technical consultant where I have
`
`provided expert advice regarding Flash memory technology, CMOS process
`
`technology, and semiconductor device physics.
`
`8
`
`Micron Ex. 1009, p. 8
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Declaration of Dr. David Liu
`
`14.
`
`I am not now and have never been an employee of the Petitioner.
`
`III. ASSIGNMENT AND MATERIALS CONSIDERED
`15.
`I have been asked to provide analysis and explain the subject matter of
`
`the 298 patent, including the state of the art when the 298 patent application was
`
`filed. I have also been asked to consider, analyze, and explain certain prior art to
`
`the 298 patent including how that art relates to the challenged claims of the 298
`
`patent and to provide my opinions regarding whether that art invalidates the
`
`claimed subject matter.
`
`16. The opinions expressed in this declaration are not exhaustive of my
`
`opinions regarding the unpatentability of the claims of the 298 patent. Therefore,
`
`the fact that I do not address a particular point should not be understood to indicate
`
`an agreement on my part that any claim complies with the requirements of any
`
`applicable patent or other rule.
`
`17.
`
`I reserve the right to amend and supplement this declaration in light of
`
`additional evidence, arguments, or testimony presented during this IPR or related
`
`proceedings on the 298 patent.
`
`18.
`
`In forming the opinions set forth in this declaration, I have considered
`
`and relied upon my education, knowledge of the relevant field, knowledge of
`
`scientific and engineering principles, and my experience. I have also reviewed and
`
`9
`
`Micron Ex. 1009, p. 9
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`considered the 298 patent (Exhibit 1001), its prosecution history (Exhibit 1002),
`
`Declaration of Dr. David Liu
`
`and the following additional materials:
`
`Exhibit
`
`Description
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`U.S. Patent Application Publication No. 2011/0099460
`(“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`U.S. Patent Application Publication No. 2009/0327591
`(“Moshayedi”)
`
`U.S. Patent No. 7,254,059 (“Li”)
`
`Betty Prince, Semiconductor Memories – A Handbook of
`Design, Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617
`(“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
`
`U.S. Patent Application Publication No. 2011/0115192 (“Y.
`Lee”)
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601
`(“Gavens”)
`
`1023
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`10
`
`Micron Ex. 1009, p. 10
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Exhibit
`
`Description
`
`Declaration of Dr. David Liu
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1040
`
`1041
`
`1042
`
`1043
`
`1044
`
`1045
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition,
`2006, definition of periodic
`
`New Oxford American Dictionary, 3rd Edition, 2010, definition
`of module
`
`U.S. Patent Application Publication No. 2010/0172180
`(“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650
`(“Chin”)
`
`European Patent Specification No. EP 2.291.746 B1 (“Radke”)
`
`U.S. Patent Application Publication No. 2015/0214476
`(“Matsui”)
`
`U.S. Patent Application Publication No. 2006/0053246
`(“S. Lee”)
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`U.S. Patent Application Publication No. 2012/0311244
`(“Huang”)
`
`U.S. Patent Application Publication No. 2008/0082736
`(“Chow”)
`
`11
`
`Micron Ex. 1009, p. 11
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Exhibit
`
`Description
`
`Declaration of Dr. David Liu
`
`1046
`
`1047
`
`U.S. Patent No. 8,656,256 (“Weathers”)
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`IV. UNDERSTANDING OF THE LAW
`19.
`I am not an attorney, but I have been instructed in and applied the law
`
`as described in this section.
`
`20.
`
`I understand that the first step in comparing an asserted claim to the
`
`prior art is for the claim to be properly construed. I address how a person of
`
`ordinary skill in the art would have understood the claims of the alleged invention
`
`in Section IX below.
`
`21.
`
`I have been further instructed and understand that a patent claim is
`
`unpatentable and invalid as obvious if the subject matter of the claim as a whole
`
`would have been obvious to a person of ordinary skill in the art of the claimed
`
`subject matter as of the time of the invention at issue. I understand that when
`
`assessing the obviousness of claimed subject matter, the following factors are
`
`evaluated: (1) the scope and content of the prior art; (2) the difference or
`
`differences between each claim of the patent and the prior art; and (3) the level of
`
`ordinary skill in the art at the time the patent was filed.
`
`22.
`
`I understand that claimed subject matter may be obvious in view of
`
`more than one item of prior art. I understand, however, that it is not enough to
`
`12
`
`Micron Ex. 1009, p. 12
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`show simply that all the limitations of the claimed subject matter are spread
`
`Declaration of Dr. David Liu
`
`throughout the prior art. Instead, for claimed subject matter to be obvious over
`
`multiple references, there must be some reason or motivation for one of ordinary
`
`skill in the art to combine the prior art references to arrive at the claimed subject
`
`matter.
`
`23.
`
`I have been informed that, in seeking to determine whether an
`
`invention that is a combination of known elements would have been obvious to a
`
`person of ordinary skill in the art at the time of the invention, one must consider
`
`the references in their entirety to ascertain whether the disclosures in those
`
`references render the combination obvious to such a person.
`
`24.
`
`I have been informed and understand that, while not required, the
`
`prior art references themselves may provide a teaching, suggestion, motivation, or
`
`reason to combine, but other times the motivation linking two or more prior art
`
`references is common sense to a person of ordinary skill in the art at the time of the
`
`invention.
`
`25.
`
`I understand that a particular combination may be proven obvious
`
`merely by showing that it was obvious to try the combination. I have been
`
`informed that, if a technique has been used to improve one device, and a person of
`
`ordinary skill in the art would recognize that it would improve similar devices in
`
`13
`
`Micron Ex. 1009, p. 13
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`the same way, using the technique is obvious unless its actual application is
`
`Declaration of Dr. David Liu
`
`beyond his or her skill.
`
`26.
`
`I further understand that an obviousness analysis recognizes that
`
`market demand, rather than scientific literature, often drives innovation, and that a
`
`motivation to combine references also may be supplied by the direction of the
`
`marketplace. For example, when there is a design need or market pressure to solve
`
`a problem and there are a finite number of identified, predictable solutions, a
`
`person of ordinary skill has good reason to pursue the known options within his or
`
`her technical grasp because the result is likely the product not of innovation but of
`
`ordinary skill and common sense.
`
`27.
`
`I have been informed that the combination of familiar elements
`
`according to known methods is likely to be obvious when it does no more than
`
`yield predictable results. Thus, where all of the elements of a claim are used in
`
`substantially the same manner, in devices in the same field of endeavor, the claim
`
`is likely obvious.
`
`28. Additionally, I understand that a patent is likely to be invalid for
`
`obviousness if a person of ordinary skill can implement a predictable variation or if
`
`there existed at the time of the invention a known problem for which there was an
`
`obvious solution encompassed by the patent’s claims. Therefore, when a work is
`
`14
`
`Micron Ex. 1009, p. 14
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`available in one field of endeavor, design incentives and other market forces can
`
`Declaration of Dr. David Liu
`
`prompt variations of it, either in the same field or a different one.
`
`29.
`
`I further understand that combining embodiments related to each other
`
`in a single prior art reference would not ordinarily require a leap of inventiveness.
`
`30.
`
`I also understand that one of ordinary skill in the art must have had a
`
`reasonable expectation of success when combining references for claimed subject
`
`matter to be obvious.
`
`31.
`
`I have been informed and I understand that factors referred to as
`
`“objective indicia of non-obviousness” or “secondary considerations” are also to
`
`be considered when assessing obviousness when such evidence is available. I
`
`understand that these factors can include: (1) commercial success; (2) long-felt but
`
`unresolved needs; (3) copying of the invention by others in the field; (4) initial
`
`expressions of disbelief by experts in the field; (5) failure of others to solve the
`
`problem the claimed subject matter solved; and (6) unexpected results.
`
`32.
`
`I also understand that evidence of objective indicia of non-
`
`obviousness must be commensurate in scope with the claimed subject matter. I
`
`further understand that there must be a relationship, sometimes referred to as a
`
`“nexus,” between any such secondary indicia and the claimed invention.
`
`33. Finally, I have been informed that one cannot use hindsight to
`
`determine that an invention was obvious.
`
`15
`
`Micron Ex. 1009, p. 15
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`34.
`
`I provide my opinions in this declaration based on the guidelines set
`
`Declaration of Dr. David Liu
`
`forth above.
`
`V. LEVEL OF SKILL IN THE ART
`35.
`I have been informed and understand that the level of ordinary skill in
`
`the relevant art at the time of the invention is relevant to inquiries such as the
`
`meaning of claim terms, the meaning of disclosures found in the prior art, and the
`
`reasons one of ordinary skill in the art may have for combining references.
`
`36.
`
`I have been informed and understand that factors that may be
`
`considered in determining the level of ordinary skill include: (1) the education of
`
`the inventor; (2) the type of problems encountered in the art; (3) prior art solutions
`
`to those problems; (4) rapidity with which innovations are made; (5) sophistication
`
`of the technology; and (6) education level of active workers in the relevant field. I
`
`have been further informed and understand that a person of ordinary skill in the art
`
`is also a person of ordinary creativity.
`
`37. A person of ordinary skill in the art (“POSA”) at the time of the
`
`alleged invention would have had at least a Bachelor of Science degree in electrical
`
`engineering, computer engineering, or a closely related field, along with at least 3-
`
`5 years of experience in the design of non-volatile memory devices. An individual
`
`with an advanced degree in a relevant field would require less experience in the
`
`design of non-volatile memory devices.
`
`16
`
`Micron Ex. 1009, p. 16
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Declaration of Dr. David Liu
`
`38.
`
`In view of my educational background (e.g., a Ph.D. in Electrical
`
`Engineering obtained in 1989) and decades of experience in the design of non-
`
`volatile memories, as discussed in Section II, I was a person of more than the
`
`ordinary level of skill in the art as of July 2011. My opinions herein, however,
`
`were formed considering the perspective of an ordinarily skilled artisan.
`
`VI. THE 298 PATENT’S EFFECTIVE FILING DATE
`39.
`I understand that the application leading to the 298 patent was filed on
`
`April 25, 2012.
`
`40. Based on my review of the 298 patent, I note that it also refers to a
`
`July 19, 2011 provisional application.
`
`41. For purposes of this declaration, I have been instructed to use July 19,
`
`2011 as the effective filing date of the 298 patent. My opinions in this declaration
`
`were formed from the perspective of a person of ordinary skill in the art as of July
`
`19, 2011, including both the knowledge of a person of ordinary skill in the art at
`
`that time as well as how a person of ordinary skill in the art would have understood
`
`the prior art.
`
`VII. THE 298 PATENT
`A. Technological Background
`1.
`Volatile, Non-volatile, and Flash Memory
`42. Computer system memory comes in several varieties. Generally,
`
`computer memories store data (e.g., programs and user data) in what is known as
`
`17
`
`Micron Ex. 1009, p. 17
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`“binary” code, i.e., zeros and ones. In one of the simplest forms of memory, a
`
`Declaration of Dr. David Liu
`
`certain number of electrons may be stored on a capacitor to represent a binary 0
`
`while a different number represents a binary 1. The number of electrons will
`
`manifest themselves either as a distinct voltage level or current level that can be
`
`obtained from the capacitor.
`
`43. Memory may either be “volatile” or “non-volatile.” Volatile memory,
`
`such as dynamic random access memory (DRAM), needs continuous power to
`
`preserve stored data. That is, volatile memory loses its contents when the
`
`computer’s power is turned off. Non-volatile memory (sometimes called NVM or
`
`NV memory), such as Flash memory and disk drive storage, maintains its contents
`
`when power is turned off. Unlike volatile memory, non-volatile storage does not
`
`require a continuous availability of power in order to retain its data. See Ex. 1040,
`
`Dipert & Levy at p. 21.
`
`44. Flash memory has been a known memory type for several decades. It
`
`is often found in USB flash drives, MP3 players, digital cameras, digital phones,
`
`and more recently, in personal computers and servers. See Ex. 1018, Axelson at
`
`17-18, 22-23. One early type of flash memory was known as electrically erasable
`
`programmable read only memory (“EEPROM”). Flash has the advantage of being
`
`a non-volatile memory, while also being able to be made smaller than traditional
`
`non-volatile storage, e.g., disk drives. In addition, unlike disk drives, flash
`
`18
`
`Micron Ex. 1009, p. 18
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`memories do not have mechanical moving parts and thus are more able to
`
`Declaration of Dr. David Liu
`
`withstand sudden movement, making them better suited for portable devices.
`
`45. As shown below, many flash memory cells use floating gate
`
`transistors to store information.
`
`
`
`See also, Ex. 1014, Prince at pp. 54-55.
`
`46. Other flash memory cells use what is known as “charge trap”
`
`technology, which is a distinct but similar technology for storing charge in a flash
`
`memory cell. Ex. 1019, Micheloni at 115. In both floating gate and charge trap
`
`flash memory cells, the amount of charge stored in the cell represents information.
`
`For example, a large amount of charge may represent a value of “0,” whereas a
`
`small amount of charge may represent a value of “1.” Id. at 20.
`
`19
`
`Micron Ex. 1009, p. 19
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Declaration of Dr. David Liu
`
`2.
`SLC and MLC Flash Memory Cells
`47. The charge on the floating gate indicates the value that the cell stores
`
`by affecting the threshold voltage of the memory cell. The threshold voltage of the
`
`memory cell refers to the voltage at which the transistor will begin to conduct
`
`substantial current across the channel. As described below, the threshold voltage
`
`can be set such that the cell stores two values, i.e., either a 0 or 1 (single-level cell,
`
`“SLC”) or such that the cell stores more than two values (multi-level cell, “MLC”).
`
`For example, a multi-level cell may stores two bits, representing four values, i.e.,
`
`00, 01, 10, or 11.
`
`48. A typical way to program a Flash cell is to apply a voltage pulse to the
`
`control gate, and to place the source and drain at ground. Then, electrons will be
`
`injected onto the floating gate. This adds charge to the floating gate and, therefore,
`
`changes the threshold voltage of the memory cell. Ex. 1019, Micheloni at 24.
`
`49. During programming, the device will periodically perform a verify
`
`operation on the cells being programmed. Ex. 1019, Micheloni at 62. After the
`
`floating gate has been programmed for a period of time, the device will read the
`
`state of the memory cell and attempt to verify that it has been programmed to the
`
`proper threshold voltage. If the memory cell is read at the proper state, then
`
`programming is complete. If the memory cell does not verify to the proper state,
`
`then the programming process is repeated.
`
`20
`
`Micron Ex. 1009, p. 20
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`
`Declaration of Dr. David Liu
`
`50. Different threshold voltages can correspond to different memory
`
`states or digital values. For example, if the memory cell has a threshold voltage of
`
`0 volts, this may correspond to a logical high value, whereas a threshold voltage of
`
`1 volt may correspond to a logical low value. The threshold voltage is
`
`programmable to various threshold values and these memory states can be
`
`associated with different logical values. SLC refers to Flash cells that have two
`
`states, whereas MLC refers to Flash cells that have more than two states. Ex.
`
`1019, Micheloni at 5-6; Ex. 1015, Varkony at 3:4-7, 7:24-35.
`
`51. Flash memory cells, however, “wear out,” i.e., after a certain number
`
`of erase and program (write) operations, they become defective and, e.g., remain
`
`“stuck” at a 0 or 1 value. E.g., Ex. 1019, Micheloni at 41; Ex. 1016, Friedman at
`
`1:19-37. While in other memories, such as DRAM, memory cells also become
`
`defective, the problem is a much bigger issue in flash memories and techniques to
`
`deal with this wear have been around, in effect, since the creation of flash
`
`memories.
`
`3.
`Flash Architecture
`52. Flash memory is organized into “blocks,” “pages,” and/or “sectors.”
`
`Ex. 1019, Micheloni at 27. A block is the smallest erasable unit; an erase
`
`operation must occur, at minimum, on an entire block, not a subset of the block. A
`
`block is made up of multiple pages. A page is the smallest programmable or
`
`21
`
`Micron Ex. 1009, p. 21
`Micron v. Vervain
`IPR2021-01547
`
`

`

`
`writable unit; in a read or write operation, an entire page, not a subset of the page,
`
`Declaration of Dr. David Liu
`
`must be read or written. A page may be made up of one or more sectors. The host
`
`(not the flash device) defines the size of the sector. Ex. 1041, Gorobets, 2:57-66.
`
`53. The size of a block and of a page are often influenced by constraints
`
`in the physical design of the memory. For example, blocks in flash memory tend
`
`to be bigger than pages because the hardware required to erase a cell tends to be
`
`bigger than the hardware required to write some number of cells. Thus, 2,000 cells
`
`might share the same write hardware (and therefore be in the same page), whereas
`
`128 pages might share the same erase hardware (and therefore be in the same
`
`block). In the context of flash memories, a sector is often the same size as a page.
`
`Ex. 1019, Micheloni at 40.
`
`54. Flash memories typically comprise many blocks