UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`
`____________________________
`
`Case No.: IPR2021-01547
`U.S. Patent No. 8,891,298
`Original Issue Date: November 18, 2014
`
`Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
`_________________________________________________________________
`
`PETITIONER’S REPLY
`_________________________________________________________________
`
`

`

`TABLE OF CONTENTS
`
`I.
`II.
`
`III.
`
`IV.
`
`V.
`
`3.
`
`B.
`
`Introduction ..................................................................................................... 1
`The Board Should Again Reject PO’s Attempt to Construe “Blocks”
`to Mean “Physical Blocks” ............................................................................. 2
`The Moshayedi in View of Dusija Grounds Discloses and Renders
`Obvious Limitations [1.F]-[1.G] .................................................................... 6
`A.
`Moshayedi’s “Erase Count” Disclosures Render Obvious
`Limitations [1.F]-[1.G] ................................................................................... 7
`1.
`PO Relies on an Incorrect Construction of “Transferring” .......... 8
`2.
`Moshayedi Discloses the “Transferring” Limitation Under
`PO’s Incorrect Construction ........................................................... 10
`Moshayedi Renders Obvious the “Transferring” Limitation
`Under PO’s Incorrect Construction ............................................... 13
`Moshayedi’s “Write Count” Disclosures Render Obvious
`Limitations [1.F]-[1.G] ................................................................................. 15
`The Dusija in View of Sutardja Grounds Renders Obvious Limitations
`[1.F] and [1.G] .............................................................................................. 16
`The “Second Showing” Renders Obvious Limitations [1.F]-
`[1.G] ............................................................................................................... 17
`1.
`Limitation [1.F].................................................................................. 17
`2.
`Limitation [1.G] ................................................................................. 18
`The “First Way” Teachings Render Obvious Limitation [1.F]-
`[1.G] ............................................................................................................... 21
`1.
`Limitation [1.F].................................................................................. 21
`2.
`Limitation [1.G] ................................................................................. 23
`Conclusion .................................................................................................... 24
`
`-i-
`
`

`

`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Acceleration Bay, LLC v. Activision Blizzard Inc.,
`908 F.3d 765 (Fed. Cir. 2018) .............................................................................. 6
`Evolusion Concepts, Inc. v. HOC Events, Inc.,
`22 F.4th 1361 (Fed. Cir. 2022) ............................................................................. 3
`In re Fulton,
`391 F.3d 1195 (Fed. Cir. 2004) .......................................................................... 15
`Kingston Tech. Co., Inc. v. SPEX Techs., Inc.,
`798 F. App'x 629 (Fed. Cir. 2020) ................................................................ 18, 22
`Microprocessor Enhancement Corp. v. Texas Instruments Inc.,
`520 F.3d 1367 (Fed. Cir. 2008) ............................................................................ 6
`Microsoft Corp. v. FG SRC, LLC,
`860 Fed. Appx. 708 (Fed. Cir. 2021) ............................................................ 17, 21
`Novo Nordisk A/S v. Eli Lilly & Co.,
`1999 WL 1094213 (D. Del. Nov. 18, 1999) ......................................................... 3
`
`-ii-
`
`

`

`LISTING OF EXHIBITS
`
`Exhibit
`
`Description
`
`1001
`
`1002
`
`U.S. Patent No. 8,891,298 to Rao (“298 patent”)
`
`File History of U.S. Patent No. 8,891,298
`
`1003-1008
`
`Intentionally omitted
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`Declaration of Dr. David Liu (“Liu Decl.”) - IPR2021-01547
`
`U.S. Patent Application Publication No. 2011/0099460
`(“Dusija”)
`
`U.S. Patent Application Publication No. 2008/0140918
`(“Sutardja”)
`
`U.S. Patent Application Publication No. 2009/0327591
`(“Moshayedi”)
`
`U.S. Patent No. 7,254,059 (“Li”)
`
`Betty Prince, Semiconductor Memories – A Handbook of
`Design, Manufacture, and Application (2d ed. 1991) (“Prince”)
`
`U.S. Patent No. 8,120,960 (“Varkony”)
`
`U.S. Patent No. 7,000,063 (“Friedman”)
`
`U.S. Patent Application Publication No. 2005/0251617
`(“Sinclair”)
`
`Jan Axelson, USB Mass Storage: Designing and Programming
`Devices and Embedded Hosts (2006) (“Axelson”)
`
`Rino Micheloni et al., Inside NAND Flash Memories (1st ed.
`2010) (“Micheloni”)
`
`U.S. Patent Application Publication No. 2011/0115192 (“Y.
`Lee”)
`
`-iii-
`
`

`

`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`U.S. Patent No. 7,453,712 (“Kim”)
`
`U.S. Patent Application Publication No. 2011/0096601
`(“Gavens”)
`
`U.S. Patent No. 8,078,794 (“C. Lee”)
`
`U.S. Patent No. 7,733,729 (“Boeve”)
`
`Microsoft Computer Dictionary, Fifth Edition, 2002, definition
`of read-after-write
`
`Merriam-Webster’s Collegiate Dictionary, Eleventh Edition,
`2006, definition of periodic
`
`New Oxford American Dictionary, 3rd Edition, 2010, definition
`of module
`
`U.S. Patent Application Publication No. 2010/0172180
`(“Paley”)
`
`U.S. Patent No. 7,853,749 (“Kolokowsky”)
`
`U.S. Patent Application Publication No. 2010/0017650
`(“Chin”)
`
`European Patent Specification No. EP 2.291.746 B1 (“Radke”)
`
`U.S. Patent Application Publication No. 2015/0214476
`(“Matsui”)
`
`U.S. Patent Application Publication No. 2006/0053246
`(“S. Lee”)
`
`Complaint for Patent Infringement, Dkt. No. 1, Vervain, LLC v.
`Micron Technology, Inc., Micron Semiconductor Products,
`Inc., and Micron Technology Texas, LLC, Case No. 6:21-cv-
`00487-ADA (May 10, 2021 W.D. Tex.)
`
`-iv-
`
`

`

`1035
`
`1036
`
`1037
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`1044
`
`1045
`
`1046
`
`1047
`
`Agreed Scheduling Order, Dkt. No. 24, dated September 16,
`2021, in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas,
`LLC, Case No. 6:21-cv-00487-ADA
`
`Vervain’s Preliminary Infringement Contentions, dated August
`6, 2021, in Vervain, LLC v. Micron Technology, Inc., Micron
`Semiconductor Products, Inc., and Micron Technology Texas,
`LLC, Case No. 6:21-cv-00487-ADA
`
`Judge Albright, Order Governing Proceedings - Patent Cases
`(OGP 3.4), dated June 24, 2021
`
`Scott McKeown, “WDTX ‘Implausible Schedule’ & Cursory
`Markman Order Highlighted,” Ropes & Gray, Patents Post-
`Grant, Inside Views & News Pertaining to the Nation’s Busiest
`Patent Court, June 2, 2021
`
`Dani Kass, Judge Albright Now Oversees 20% of New U.S.
`Patent Cases, Law360, March 10, 2021
`
`Brian Dipert and Markus Levy, Designing with Flash Memory
`(1994) (“Dipert & Levy”)
`
`U.S. Patent No. 7,366,826 (“Gorobets”)
`
`U.S. Patent No. 6,901,498 (“Conley”)
`
`U.S. Patent No. 8,356,152 (“You”)
`
`U.S. Patent Application Publication No. 2012/0311244
`(“Huang”)
`
`U.S. Patent Application Publication No. 2008/0082736
`(“Chow”)
`
`U.S. Patent No. 8,656,256 (“Weathers”)
`
`Ashok Sharma, Advanced Semiconductor Memories,
`Architectures, Designs, and Applications (2003) (“Sharma”)
`
`1048-1055
`
`Intentionally omitted
`
`-v-
`
`

`

`1056
`
`1057
`
`1058
`
`1059
`
`1060
`
`1061
`
`1062
`
`1063
`
`1064
`
`1065
`
`1066
`
`Pro Hac Vice Motion of Jared Bobrow
`
`Reply Declaration of Dr. David Liu (“Liu Reply”) - IPR2021-
`01547
`
`Curriculum Vitae of Dr. David Liu
`
`Deposition Transcript of Sunil Khatri (September 1, 2022)
`[IPR2021-01547, -01548 and -01549]
`
`Intentionally omitted
`
`U.S. Patent No. 8,130,554 (“Linnell”)
`
`U.S. Patent No. 7,917,709 (“Gorobets III”)
`
`Excerpt from Exhibit 1 (eMMC) to Vervain’s Final
`Infringement Contentions, dated August 31, 2022, in Vervain,
`LLC v. Micron Technology, Inc., Micron Semiconductor
`Products, Inc., and Micron Technology Texas, LLC, Case No.
`6:21-cv-00487-ADA – FILED UNDER SEAL
`
`Byung-Woo Nam, Gap-Joo Na, and Sang-Won Lee, “A Hybrid
`Flash Memory SSD Scheme for Enterprise Database
`Applications”
`
`Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, “Improving
`Flash Wear-Leveling by Proactively Moving Static Data”
`
`Muthukumar Murugan, “Rejuvinator: A Static Wear Leveling
`Algorithm for NAND Flash Memory with Minimized
`Overhead”
`
`1067-1068
`
`Intentionally omitted
`
`-vi-
`
`

`

`I.
`
`Introduction
`Against the Moshayedi set of grounds, PO’s sole argument relies on two
`
`steps: (1) rewriting limitation [1.G] to read “by transferring the respective contents
`
`of [in] those [physical] blocks [before the allocation],” and (2) misreading
`
`Moshayedi as only disclosing writing new data into SLC (and as not disclosing
`
`copying data in a physical MLC block into an SLC block). As to the first step,
`
`PO’s expert admitted that PO’s basis for rewriting this limitation—that logical
`
`blocks cannot be erased—is incorrect. The record shows that it was well known in
`
`the art that logical blocks can be erased. But even if this rewrite were permissible
`
`(it’s not), Moshayedi plainly discloses limitation [1.G]: “the MLC block data (for a
`
`MLC block with erase count=500) can be copied to a free block of SLC.” Ex.
`
`1012 (“Moshayedi”), [0049]. PO cannot rewrite this sentence, too. Finally, even
`
`ignoring all of this, PO utterly fails to challenge the Petition’s alternative showing
`
`that the limitation, even as rewritten by PO, would have been obvious.
`
`With no legitimate argument against the Sutardja set of grounds, PO resorts
`
`to misrepresentation and speculation. Although the Petition clearly sets forth
`
`alternative showings (the “first way” and “second showing”) that render the claims
`
`obvious, PO pretends as if the Petition does not present two sets of claim
`
`mappings. PO then makes arguments which all assume that the claimed “block”
`
`actually means “physical block,” thereby ignoring the context of the claims and
`
`-1-
`
`

`

`specification. Next, PO goes so far as to argue that Sutardja’s second NVS
`
`memory in its “hybrid” flash memory system—which has a greater write cycle
`
`lifetime, is more expensive, and is faster than the first NVS memory—may not be
`
`SLC. PO does not deny that these characteristics of Sutardja’s second NVS are
`
`hallmarks of SLC. Rather, PO’s argument relies on its expert’s speculation that
`
`perhaps Sutardja was built with used parts, and thus one cannot tell if these
`
`hallmarks apply.
`
`None of these arguments raise a serious challenge to the Petition’s showings.
`
`II.
`
`The Board Should Again Reject PO’s Attempt to Construe “Blocks” to
`Mean “Physical Blocks”1
`PO’s proposed construction of “blocks,” i.e., “in a non-volatile memory, a
`
`physical group of memory cells that must be erased together,” is just another way
`
`of saying “physical blocks.” POR, 23-24 (characterizing dispute as “blocks” must
`
`“be physical as opposed to logical blocks”). For good reason, the Board already
`
`rejected PO’s attempt to limit “blocks” to “physical blocks.” ID, 17; Ex. 1057
`
`(“Liu Reply”), ¶¶ 11-17.
`
`1 Petitioner agrees with PO that no constructions of “data integrity test” and “on a
`
`periodic basis” are necessary to resolve this proceeding. POR, 27-30.
`
`-2-
`
`

`

`As to the claim language, first, because patentee chose the broader claim
`
`term, “block,” as opposed to the narrower term, “physical block,” the claim scope
`
`must reflect this “choice of words.” Novo Nordisk A/S v. Eli Lilly & Co., No.
`
`CIV.A.: 98-643 MMS, 1999 WL 1094213, at *17 (D. Del. Nov. 18, 1999) (“[I]f
`
`Lilly had desired to limit the claims to ‘human patients,’ it could have used that
`
`language instead of ‘patient.’ Since Lilly chose to use the broader term[ ] . . .
`
`‘patient,’ the scope of the claims should reflect its choice of words.”); see also
`
`Evolusion Concepts, Inc. v. HOC Events, Inc., 22 F.4th 1361, 1366-67 (Fed. Cir.
`
`2022) (applying same reasoning not to limit “magazine catch bar” to a “new,”
`
`“different,” or “remov[able]” “magazine catch bar”). Here, the specification
`
`references “logical block,” “physical block,” and “block” (Ex. 1001, 2:10-27, 2:59-
`
`3:13, 6:24-35), and patentee deliberately chose to use the broad claim term
`
`“block.” Thus, the claim scope of “block” must “reflect [patentee’s] choice of
`
`words” and include within its scope both logical and physical blocks. Novo
`
`Nordisk A/S, 1999 WL 1094213, at *17.
`
`Second, the surrounding claim language confirms that the claim term
`
`“blocks” includes logical blocks within its scope. Claim 1 starts with “one MLC
`
`non-volatile memory module comprising a plurality of individually erasable
`
`blocks.” The claim then recites “maintain[ing] an address map of … the MLC …
`
`non-volatile memory module[].” That map includes (1) “logical address ranges
`
`-3-
`
`

`

`having a minimum quanta of addresses” that (2) each “maps” to (3) “a similar
`
`range of physical addresses.” This claim language, as PO’s expert confirms,
`
`“map[s] logical blocks to physical blocks.”2 Ex. 2014, ¶ 33. Thus, this “map[]”
`
`limitation expressly requires that the claimed “blocks” exist as both logical and
`
`physical blocks. Indeed, dependent claim 2 specifies that “the minimum quanta of
`
`[logical] addresses is equal to one block,” expressly incorporating in the claim
`
`language logical and physical blocks.
`
`Third, the claim language would be nonsensical if “block” meant only a
`
`“physical block.” Claim 1 recites “allocate those blocks … to the at least one SLC
`
`non-volatile memory module.” But physical blocks cannot be allocated from MLC
`
`to SLC, e.g., there are no microscopic tools to physically move a physical block to
`
`a different module. Rather, and as Dr. Khatri admits, the allocation is of a logical
`
`block, i.e., allocating refers to reassigning the logical block address from the MLC
`
`module to the SLC module. Ex. 1059, 102:21-105:16; Liu Reply, ¶ 15.
`
`In the face of all this, PO argues that “the blocks” must mean “physical
`
`blocks” because the claim recites “a plurality of individually erasable blocks,” and
`
`2 A “block” in flash memory may exist in two corresponding forms: the physical
`
`form (“physical block”) and a corresponding logical form (“logical block”). Ex.
`
`1001, 2:59-3:13; Liu Reply, ¶ 13.
`
`-4-
`
`

`

`“only physical (and not logical) blocks can be erased.” POR, 24-25. This
`
`argument fails for three independent reasons.
`
`First, it is wrong. As Dr. Khatri conceded in his deposition, logical blocks
`
`were (and are) erasable. Dr. Khatri, for example, admits that Moshayedi discloses
`
`“the erase count of a logical block.” Ex. 1059, 168:19-169:8.3 It was well known
`
`in the art that logical blocks are erasable. E.g., Ex. 1061, 3:54-4:2 (“delet[ing]” a
`
`“logical block”), 6:63-7:5 (“logical block level erasure”); Ex. 1062, 2:10-34 (“The
`
`host can issue a sector erase command to erase the logical sector in the memory.”).
`
`Indeed, in the context of hot blocks and MLC-SLC data movement, Moshayedi
`
`discloses using the “erase count of a logical block address (LBA)” to trigger data
`
`movement. Moshayedi, Claim 1-2; Liu Reply, ¶¶ 16-17.
`
`3 Although Dr. Khatri now admits that logical blocks are erasable by the host, he
`
`suggests that the 298 patent defines “erasable” as physical erasure, contrary to its
`
`plain and ordinary meaning. Ex. 1059, 48:6-21. As discussed below, there is no
`
`lexicography or disclaimer here. Also, it makes little sense to argue that the 298
`
`patent would define “erase” to exclude host erases because the 298 specification
`
`and claims refer to host accesses. Ex. 1001, 2:17-28, 2:49-3:1, 5:1-4, Claim 1
`
`(“maps” limitation).
`
`-5-
`
`

`

`Second, even if this erase language references the physical block form of a
`
`“block” (it doesn’t), Claim 1 later confirms that the “block” also has a logical
`
`block form with the “map[]” limitation. This shows that “block” includes both
`
`forms.
`
`Third, even if this erase language specifies a physical block (it doesn’t),
`
`“the patentee’s mere use of a term with an antecedent does not require that both
`
`terms have the same meaning” where a uniform reading is “nonsensical.”
`
`Microprocessor Enhancement Corp. v. Texas Instruments Inc., 520 F.3d 1367,
`
`1375 (Fed. Cir. 2008). Both parties’ experts agree that it would be nonsensical to
`
`actually “allocate” physical blocks. Ex. 1059, 102:21-105:16.
`
`As to the specification and file history, there is no disclaimer or
`
`lexicography that limits “blocks” to “physical blocks.” Acceleration Bay, LLC v.
`
`Activision Blizzard Inc., 908 F.3d 765, 770-71 (Fed. Cir. 2018) (requiring “precise
`
`and clear language” to read in limitation). To the contrary, the only relevant
`
`embodiment (describing “blocks” that are “accessed” and “allocate[d]”) uses the
`
`generic term “blocks” in describing these actions. Ex. 1001, 6:24-35. And as
`
`noted above, both parties’ experts agree that logical blocks are being allocated.
`
`III. The Moshayedi in View of Dusija Grounds Discloses and Renders
`Obvious Limitations [1.F]-[1.G]
`The Petition demonstrated that Moshayedi discloses and renders obvious
`
`limitations [1.F]-[1.G] with two alternative sets of disclosures: (1) using an erase
`
`-6-
`
`

`

`count to swap frequently-erased MLC blocks to SLC (Moshayedi, [0032], [0049]),
`
`and (2) using a write count to perform the same swap for frequently-written MLC
`
`blocks (Moshayedi, [0024]). Petition, 60-65.
`
`A. Moshayedi’s “Erase Count” Disclosures Render Obvious Limitations
`[1.F]-[1.G]
`PO does not argue that Moshayedi’s “erase count” disclosures fail to satisfy
`
`limitation [1.F], e.g., under its erroneous “block” construction.4 POR, 66. Thus,
`
`despite the POR’s headings, PO challenges Moshayedi’s “erase count disclosures”
`
`only with respect to the “transferring” portion of limitation [1.G]. POR, 57-66.
`
`The Petition demonstrated that for (1) a frequently-erased MLC block and
`
`(2) a frequently-written MLC block, the next incoming write will trigger a “swap”
`
`that satisfies “transferring the respective contents of those blocks to the at least one
`
`SLC non-volatile memory module.” Petition, 62-65. In particular, Moshayedi
`
`4 Nor could it. Moshayedi’s claim 1 recites “a list of one or more metrics
`
`associated with the erasing data blocks,” and claim 2 recites “wherein the one or
`
`more metrics … comprise an erase count of a logical block address (LBA).”
`
`Moshayedi, Claims 1-2. Thus, given that the dependent claim narrows “erase” to
`
`“logical block” erasure, Claim 1’s generic “erasing data blocks” recitation must
`
`include erasures of both physical and logical blocks.
`
`-7-
`
`

`

`discloses that if one of the “counts” is above a threshold, a write operation directed
`
`to that block will instead be written to an SLC block. Id. PO argues that because
`
`the new data (associated with the incoming write) was not previously in the
`
`physical MLC block, this cannot satisfy the transferring limitation. POR, 57-63.
`
`PO’s argument fails for three independent reasons.
`
`1. PO Relies on an Incorrect Construction of “Transferring”
`PO characterizes the “swap” operation as only writing “a single block of
`
`data” received with the write operation to SLC. POR, 57. Even if this were
`
`correct (it’s not), it satisfies the claims under the correct claim interpretation. Note
`
`that for this write operation, the “newly received data [is] associated with a
`
`particular LBA.” Moshayedi, ¶24.5 Thus, upon receiving the write operation with
`
`new “data,” that “data” are “the respective contents of those blocks,” because the
`
`are “associated with a particular LBA” (i.e., the LBA for the MLC block). Id. The
`
`act of writing that data to SLC “transfer[s] the respective contents of those blocks
`
`to the at least one SLC non-volatile memory module.” Liu Reply, ¶ 18. The
`
`limitation requires nothing more.
`
`5 Moshayedi at paragraphs [0024] and [0032] describes the same “swap” and write
`
`redirection but using different counts. Petition, 62-63.
`
`-8-
`
`

`

`In response, PO argues that Moshayedi does not disclose the transferring
`
`limitation because the transfer must be of the data “that is already in MLC flash
`
`memory.” POR, 59. This interpretation attempts to rewrite the claim language as
`
`follows: “by transferring the respective contents of [in] those [physical] blocks
`
`[before the allocation].” This interpretation fails at multiple levels.
`
`First, for the reasons set forth in Section II, there is no basis to limit
`
`“blocks” to “physical blocks.” Section II. Thus, the “contents” that are transferred
`
`need not be in the physical blocks.
`
`Second, PO identifies no lexicography or disclaimer that justifies
`
`interjecting a limitation that the “contents” must be from before the allocation
`
`occurs. POR, 48-50. In fact, the only relevant portion of the specification
`
`contradicts any such limitation. Ex. 1001, 6:24-35. The specification notes that
`
`the controller can perform this transfer “for example, every 1000 writes, or every
`
`10,000 writes.” Id., 6:30-35. This only embodiment suggests that the “transfer[]”
`
`may occur by transferring the data associated with a write command (not the data
`
`from before the allocation) to SLC, e.g., as part of the 1000th write operation. Liu
`
`Reply, ¶ 20.
`
`Third, PO’s implicit construction is disingenuous. In a related district court
`
`proceeding, PO has accused “dynamic wear leveling” (i.e., the directing of
`
`incoming writes based on write count) of satisfying limitation [1.G]. Ex. 1063, 18-
`
`-9-
`
`

`

`21 (“Dynamic [wear leveling]: policy used to choose a new NAND block to use
`
`during Host write.”). PO’s district court position contradicts its position before the
`
`Board. PO’s failure to disclose its inconsistent position violates its duty of candor
`
`to the PTAB.
`
`2. Moshayedi Discloses the “Transferring” Limitation Under
`PO’s Incorrect Construction
`In instituting trial, the Board made a critical observation: nothing about
`
`Moshayedi says that only “new” data (the data associated with the write operation)
`
`are transferred to SLC. ID, 30-31. This is correct. As explained below,
`
`Moshayedi’s “swap” operation involves redirecting an incoming write from a
`
`block of MLC to a block in SLC and also transferring the remaining valid data in
`
`the original MLC physical block to the newly chosen SLC physical block so that
`
`the original MLC block can be erased. This satisfies limitation [1.G] under PO’s
`
`erroneous interpretation.
`
`For context, a block in NAND flash is the smallest erasable unit and
`
`comprises multiple pages. A page is the smallest writable unit. Ex. 1009 (“Liu
`
`Decl.”), ¶¶52-54. Thus, if a host writes only a single page, it will not change the
`
`data (or lack thereof) in the remaining pages in that block. Id. In the case of
`
`Moshayedi’s write redirection, this means the “new” data, originally intended for a
`
`“selected” block in MLC, may be redirected and written to a “free block” of SLC
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`instead. Moshayedi, [0047]-[0048] (transferring), Figs. 7A, 7B, [0049] (copying),
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`[0060]. If the other pages of the “selected” MLC block include valid data,
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`Moshayedi will transfer those pages to SLC in order to transfer the entire MLC
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`block to SLC, which allows the selected block to be erased. Moshayedi, [0048],
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`[0060], Fig. 7B (steps 720, 724). This copying or transferring of the existing pages
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`to another block was well-known in the art as part of “garbage collection” and
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`“block reclamation” wherein existing pages in a block would be moved to a new
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`block so that the original block could be marked invalid, erased during garbage
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`collection, and “reclaimed” for subsequent writes. Ex. 1064, 39, 42 (describing
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`“valid pages in the original data block” may exist and transferring to a new block);
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`Ex. 1065, 55 (“before a block is erased, data of any valid pages in the block must
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`be copied to the other free pages”); Ex. 1066, 2-3 (describing “cop[ying]” “valid
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`pages” to a new block before reclaiming a block); Ex. 1046, 7:54-66 (describing
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`the remapping and moving of data to a new block so that the old block can be
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`“reclaimed”); Liu Reply, ¶¶ 21-26. This is why Moshayedi discloses that the write
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`“triggers a swap where the data from the MLC flash block is written to a block in
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`SLC flash.” Moshayedi, [0032]; Liu Reply, ¶¶ 27-30.
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`Vervain erroneously assumes that Moshayedi’s “swap” only refers to the
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`redirection of the incoming write to SLC when it portrays Moshayedi’s disclosure
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`that “data from the MLC flash block is written to a block in SLC flash” is a
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`“misnomer” because no data is actually “swapped” (i.e., transferred) as part of this
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`process. Moshayedi, [0032]; POR, 57-58; see also POR, 20. Far from a
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`misnomer, Moshayedi details the transfer of data from the physical MLC block to
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`SLC as its own step. Moshayedi, [0048], Fig. 7B (step 720). Specifically, during a
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`write operation, incoming data is buffered and, if the erase count of the MLC block
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`is above a threshold, the “swap” process is initiated. Id., [0047]. Moshayedi then
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`finds a “free block” in SLC and transfers the existing data from the “selected
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`block” (i.e., MLC) to the “free block” (i.e., SLC) before copying the buffered data
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`into SLC. Id., [0048], Fig. 7B (steps 720 and 722); Liu Reply, ¶¶ 28-30. Thus,
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`Vervain’s contention that Moshayedi’s “swap” is merely the redirection of an
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`incoming write is incorrect.
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`This “swap” is further detailed in paragraph [0049] of Moshayedi, which
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`teaches the copying of data already in MLC to SLC. Moshayedi discloses that “the
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`next written data can be moved to a SLC area.” Moshayedi, [0049]. After this, it
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`discloses “[f]or example, the MLC block data (for a MLC block with erase
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`count=500) can be copied to a free block of SLC” and “[t]he MLC block can then
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`be erased.” Id. The old block can be marked invalid and, subsequently, erased
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`through a process such as garbage collection because all pages were transferred to
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`the new SLC block (between the write operation and the copying of other pages).
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`It was well known that a block cannot be erased until all existing valid pages are
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`copied into a new block, here, the SLC block. Ex. 1064, 39, 42; Ex. 1065, 55; Ex.
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`1046, 7:54-66; Ex. 1066, 2-3. Confirming this, Moshayedi discloses: “The
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`fundamental write flow is that a free block is selected as a new target block. The
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`original data plus changed data is copied to the new target block.” Moshayedi,
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`[0059]. The “original data” is the data in the physical block (any valid pages), and
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`the “changed data” is the incoming write data. Liu Reply, ¶¶ 30-31. In summary,
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`Moshayedi discloses the ability to transfer any remaining valid pages in the
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`physical MLC block to the SLC block, enabling erasure of the physical MLC
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`block.
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`What’s more, Moshayedi discloses that “[i]t is not possible to operate the
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`SLC at one logical block size and the MLC at a different logical block size. The
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`reason for this being that it would make it extremely difficult to copy data between
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`the two and keep track of the data.” Moshayedi, [0068]. Here, Moshayedi is
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`referring to the need to keep the pages of the block together, i.e., when necessary,
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`copy all the block pages from MLC to SLC to move the block to SLC. Liu Reply,
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`¶ 32.
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`3. Moshayedi Renders Obvious the “Transferring” Limitation
`Under PO’s Incorrect Construction
`The Petition also demonstrated that it would have been obvious to perform
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`the entire transfer outside the context of a write operation, i.e., merely copy the
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`entire MLC physical block content to SLC. Petition, 64; Liu Decl., ¶ 227. Dr. Liu
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`cited Moshayedi ([0049]) and five references establishing that it was well known
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`to do such operations during “idle” time, when the controller is free to do such
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`operations. Id. Indeed, PO does not contest the benefits of doing such operations
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`as background operations during “idle time.” Nor could it. Such background
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`operations “prepare for future write commands to improve [system] performance.”
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`Ex. 1044, [0163]; Liu Decl., ¶ 227. PO’s expert, Dr. Khatri, says such background
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`operations “save time and resources.” Ex. 1059, 195:16-196:18. In Moshayedi,
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`transferring the frequently-written MLC blocks to SLC during idle time would
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`prepare for the next write operation to that block, obviating the need to perform the
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`write redirection because the transfer would have already been done. Liu Reply, ¶¶
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`33-34.
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`In response, PO first argues that Moshayedi ([0049]) does not disclose
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`background operations. POR, 61. This is wrong. Even PO concedes that
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`Moshayedi describes SLC-to-MLC background operations. Id., 62 (citing
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`Moshayedi, [0073]); Moshayedi, [0049] (“SLC block data can be copied to the free
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`block of MLC”).
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`Next, PO argues that Moshayedi teaches away from MLC-to-SLC
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`background operations because Moshayedi discloses that they are unnecessary.
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`POR, 62. But this ignores Moshayedi’s teaching that such MLC-to-SLC
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`background operations are only unnecessary because of the write redirection.
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`Moshayedi, [0073]; Ex. 1059, 195:16-196:18. In other words, Moshayedi teaches
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`that an alternative to write redirection is MLC-to-SLC background operations, just
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`like Moshayedi’s SLC-to-MLC background operations. Liu Reply, ¶ 35. And
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`“[t]he prior art’s mere disclosure of more than one alternative does not constitute a
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`teaching away…[where] such disclosure does not criticize, discredit, or otherwise
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`discourage the solution claimed.” In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir.
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`2004).
`
`B. Moshayedi’s “Write Count” Disclosures Render Obvious Limitations
`[1.F]-[1.G]
`PO raises two arguments against the write count disclosures.
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`First, PO raises the same “transferring” argument addressed above (POR,
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`57-63), which fails for the same reasons. Section III.A.1-3.
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`Second, PO argues that Moshayedi’s “write count” disclosures do not
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`disclose limitation [1.F] because Moshayedi counts writes to logical blocks, not
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`physical blocks. POR, 63-66. This argument relies entirely on the legally
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`erroneous “physical blocks” construction and fails for that reason. See Section II.
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`Thus, Moshayedi’s write count disclosures also at least render obvious
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`limitations [1.F]-[1.G].
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`IV. The Dusija in View of Sutardja Grounds Renders Obvious Limitations
`[1.F] and [1.G]
`PO challenges the Dusija in view of Sutardja grounds only with respect to
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`limitations [1.F]-[1.G]. POR, 30-56. The Petition demonstrated that Dusija in
`
`view of Sutardja renders obvious limitations [1.F]-[1.G] with two independent,
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`alternative sets of disclosures.
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`First, Sutardja determines write counts of logical blocks and transfers the
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`most frequently written logical blocks to SLC by redirecting writes to SLC blocks,
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`i.e., by writing the logical block data into SLC and assigning the logical block
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`address to SLC. Petition, 42-44; Ex. 1011 (“Sutardja”), [0112]-[0113], [0146]-
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`[0147]. The ID and POR refer to this “logical block” mapping as the Petition’s
`
`“second showing” or “second way.” ID, 18; POR, 43-44, 48-49. PO largely
`
`focuses on this set of disclosures.
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`Second, Sutardja also satisfies these limitations by maintaining write counts
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`of physical blocks and transferring the data in the most frequently written physical
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`blocks to SLC using a “data shift” procedure. Petition, 42-44; Sutardja, [0111],
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`[0121], [0148]-[0149]. The ID and POR refer to this “physical block” mapping as
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`Petitioner’s “first showing.” ID, 20; POR, 43.
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`The below addresses each of PO’s scattershot arguments against each
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`limitation.
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`The “Second Showing” Renders Obvious Limitations [1.F]-[1.G]
`1. Limitation [1.F]
`First, PO argues that limitation [1.F] requires counting physical writes,
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`whereas the second showing uses a logical block write count. POR, 32-36. This
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`argument fails because it relies entirely on PO’s erroneous construction of “block.”
`
`Section II. If “blocks” are construed to include both logical and physical blocks,
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`there is no dispute that this limitation is met, because Sutardja determines which
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`logical blocks are most frequently written. Ex. 1059, 135:17-21. That is,
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`maintaining counts of writes to each logical address range, i.e.,