Trials@uspto.gov
`571-272-7822
`
`Paper 13
`Date: April 8, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`v.
`VERVAIN, LLC,
`Patent Owner.
`
`IPR2021-01547
`Patent 8,891,298 B2
`
`
`
`
`
`
`
`
`
`Before SALLY C. MEDLEY, STACEY G. WHITE, and
`ROBERT J. WEINSCHENK, Administrative Patent Judges.
`MEDLEY, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`
`571-272-7822
`
`Paper 13
`Date: April 8, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`v.
`VERVAIN, LLC,
`Patent Owner.
`
`IPR2021-01547
`Patent 8,891,298 B2
`
`
`
`
`
`
`
`
`
`Before SALLY C. MEDLEY, STACEY G. WHITE, and
`ROBERT J. WEINSCHENK, Administrative Patent Judges.
`MEDLEY, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`
`
`IPR2021-01547
`Patent 8,891,298 B2
`
`I. INTRODUCTION
`Micron Technology, Inc. (“Petitioner”) filed a Petition for inter partes
`review of claims 1–5, 8, 9, and 11 of U.S. Patent No. 8,891,298 B2 (Ex.
`1001, “the ’298 patent”). Paper 1 (“Pet.”). Vervain, LLC (“Patent Owner”)
`filed a Preliminary Response. Paper 10 (“Prelim. Resp.”). Institution of an
`inter partes review is authorized by statute when “the information presented
`in the petition . . . and any response . . . shows that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of the
`claims challenged in the petition.” 35 U.S.C. § 314(a). Upon consideration
`of the Petition, the Preliminary Response, and the evidence of record, we
`determine that Petitioner has established a reasonable likelihood of
`prevailing with respect to the unpatentability of at least one claim of the ’298
`patent. Accordingly, for the reasons that follow, we institute an inter partes
`review of claims 1–5, 8, 9, and 11 of the ’298 patent.
`
`A. Real Parties in Interest
`Petitioner lists “Micron Technology, Inc.—along with its
`subsidiaries” as the real parties-in-interest. Pet. 4.
`Patent Owner lists Vervain, LLC as the real party-in-interest. Paper 4,
`
`2.
`
`B. Related Matters
`The parties identify a related district court litigation, Vervain, LLC v.
`Micron Technology, Inc., No. 6:21-cv-00487 (W.D. Tex.) (“underlying
`litigation”). Pet. 4; Paper 4, 2. The parties further identify a district court
`litigation in which Patent Owner asserted the ’298 patent against third
`parties, Vervain, LLC v. Western Digital Corp. et al., No. 6:21-cv-00488
`(W.D. Tex.). Id. The parties also identify the following inter partes review
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`Patent 8,891,298 B2
`petitions for other patents asserted in the underlying litigation: IPR2021-
`01548, involving U.S. Patent No. 9,196,385; IPR2021-01549, involving
`U.S. Patent No. 9,997,240; and IPR2021-01550, involving U.S. Patent No.
`10,950,300. Pet. 4; Paper 4, 2–3.
`
`C. The ’298 Patent
`The ’298 patent relates to “reliable storage through the use of non-
`volatile memories.” Ex. 1001, 1:25–26. In particular, the ’298 patent
`describes “a system and method of increasing the reliability and lifetime of a
`NAND flash storage system, module, or chip through the use of a
`combination of single-level cell (SLC) and multi-level cell (MLC) NAND
`flash storage.” Id. at 1:27–31. The ’298 patent observes that “MLC NAND
`flash enjoys greater density than SLC NAND flash, at the cost of a decrease
`in access speed and lifetime (endurance),” and so the patent describes using
`one bank of “economical MLC NAND flash” and another bank of “high
`endurance SLC NAND flash.” See id. at 3:19–21; 4:51–55.
`Figure 1 illustrates a computer system for implementing an
`embodiment of the ’298 patent, and is reproduced below.
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`Figure 1 shows computer system 10 as including device controller 14 for
`controlling access to MLC NAND flash memory module 26 and SLC
`NAND flash memory module 28. Id. at 4:64–5:15. Device controller 14
`maintains a translation table for mapping logical addresses to physical
`addresses in each of flash memory modules 26 and 28. Id. at 5:20–23.
`Initially, the translation table maps all logical addresses to MLC NAND
`flash memory module 26, because “MLC flash memory is less expensive
`than SLC flash memory, on a cost per bit basis.” Id. at 5:24–27. For data
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`integrity purposes, device controller 14 may read data from an address range
`after each write to an address within that range. Id. at 5:34–37. “If a data
`integrity test fails, the address range is remapped from the MLC NAND
`flash memory module 26 to the next available address range in the SLC
`NAND flash memory module 28.” Id. at 5:37–40.
`Figures 2a and 2b illustrate a failed data integrity test, and are
`reproduced below.
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`Patent 8,891,298 B2
`As Figure 2a shows, “a list of logical address ranges (R0–RN) is translated
`to physical address ranges” of blocks on MLC NAND flash memory module
`26. Id. at 5:42–46. In the example shown in Figures 2a and 2b, “address
`range R2 corresponds to failed quanta of data stored in block 2 of the MLC
`NAND flash memory module 26.” Id. at 5:48–50. Accordingly, as shown
`in Figure 2b, the failed quanta is “remapped to the next available range of
`physical addresses within the SLC NAND flash memory module 28, in this
`example, SLC/block 0.” Id. at 5:50–54.
`Although not shown in the Figures, the ’298 patent describes another
`application of a computer system that combines SLC and MLC NAND flash
`storage. Specifically, the system may “allocate ‘hot’ blocks; i.e., those
`blocks that receive frequent writes, into the SLC NAND flash memory
`module 28, while allocating ‘cold’ blocks; i.e., those blocks that only receive
`infrequent writes, into the MLC NAND flash memory module 26.” Id. at
`6:24–29. Device controller 14 “could simply maintain a count of those
`blocks that are accessed (written to) most frequently, and, on a periodic
`basis, such as, for example, every 1000 writes, or every 10,000 writes,
`transfer the contents of those blocks into the SLC NAND flash memory
`module 28.” Id. at 6:30–35.
`
`D. Illustrative Claim
`Petitioner challenges claims 1–5, 8, 9, and 11 of the ’298 patent.
`Claim 1 is independent and is reproduced below.
`1. A system for storing data comprising:
`at least one MLC non-volatile memory module comprising
`a plurality of individually erasable blocks;
`at least one SLC non-volatile memory module comprising
`a plurality of individually erasable blocks; and
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`Patent 8,891,298 B2
`a controller coupled to the at least one MLC non-volatile
`memory module and the at least one SLC non-volatile memory
`module wherein the controller is adapted to:
`a) maintain an address map of at least one of the
`MLC and SLC non-volatile memory modules, the address
`map comprising a list of logical address ranges accessible
`by a computer system, the list of logical address ranges
`having a minimum quanta of addresses, wherein each
`entry in the list of logical address ranges maps to a similar
`range of physical addresses within either the at least one
`SLC non-volatile memory module or within the at least
`one MLC non-volatile memory module;
`b) determine if a range of addresses listed by an
`entry and mapped to a similar range of physical addresses
`within the at least one MLC non-volatile memory module,
`fails a data integrity test, and, in the event of such a failure,
`the controller remaps the entry to the next available
`equivalent range of physical addresses within the at least
`one SLC non-volatile memory module;
`c) determine which of the blocks of the plurality of
`the blocks in the MLC and SLC non-volatile memory
`modules are accessed most frequently by maintaining a
`count of the number of times each one of the blocks is
`accessed; and
`d) allocate those blocks that receive the most
`frequent writes by transferring the respective contents of
`those blocks to the at least one SLC non-volatile memory
`module.
`Ex. 1001, 7:8–8:9.
`
`E. Asserted Grounds of Unpatentability
`Petitioner asserts that claims 1–5, 8, 9, and 11 would have been
`unpatentable on the following grounds (Pet. 6–7):
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`Patent 8,891,298 B2
`Claim(s) Challenged
`1–5, 11
`8, 9
`1–5, 11
`11
`8, 9
`
`35 U.S.C. §
`103(a)1
`103(a)
`103(a)
`103(a)
`103(a)
`
`Reference(s)
`Dusija,2 Sutardja3
`Dusija, Sutardja, Li4
`Moshayedi,5 Dusija
`Moshayedi, Dusija, Sutardja
`Moshayedi, Dusija, Li
`
`II. DISCUSSION
`A. Principles of Law
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time of the invention to a
`person having ordinary skill in the art. KSR Int’l Co. v. Teleflex, Inc., 550
`U.S. 398, 406 (2007). The question of obviousness is resolved on the basis
`of underlying factual determinations including (1) the scope and content of
`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of ordinary skill in the art; and (4) objective evidence
`of nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`
`1 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. § 103. The ’298 patent issued from
`U.S. Patent Appl. No. 13/455,267, which was filed on April 25, 2012. Ex.
`1001, code (22). Because the filing date is before the effective date of the
`applicable AIA amendment, we refer to the pre-AIA versions of 35 U.S.C.
`§ 103.
`2 U.S. Pat. Appl. Pub. No. US 2011/0099460 A1, published Apr. 28, 2011
`(Ex. 1010, “Dusija”).
`3 U.S. Pat. Appl. Pub. No. US 2008/0140918 A1, published June 12, 2008
`(Ex. 1011, “Sutardja”).
`4 U.S. Pat. No. US 7,254,059 B2, issued Aug. 7, 2007 (Ex. 1013, “Li”).
`5 U.S. Pat. Appl. Pub. No. US 2009/0327591 A1, published Dec. 31, 2009
`(Ex. 1012, “Moshayedi”).
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`B. Level of Ordinary Skill in the Art
`Relying on the testimony of Dr. David Liu, Petitioner offers an
`assessment as to the level of ordinary skill in the art and the general
`knowledge of a person of ordinary skill at the time of the ’298 patent. See
`Pet. 27 (citing Ex. 1009 ¶ 37). Dr. Liu states that a person having ordinary
`skill in the art “would have had at least a Bachelor of Science degree in
`electrical engineering, computer engineering, or a closely related field, along
`with at least 3–5 years of experience in the design of non-volatile memory
`devices.” Ex. 1009 ¶ 37. Patent Owner does not propose an alternative
`assessment, but rather notes that “[f]or purposes of this preliminary response
`only, Patent Owner has used Petitioner’s definition of a POSA.” Prelim.
`Resp. 12 n.2. We adopt Petitioner’s definition of the level of skill for
`purposes of this Decision, except that we delete the phrase “at least” to avoid
`including ambiguity in the definition of the level of skill.
`
`C. Claim Construction
`In inter partes review, we construe claims using the same claim
`construction standard that would be used to construe the claims in a civil
`action under 35 U.S.C. § 282(b), including construing the claim in
`accordance with the ordinary and customary meaning of such claim as
`understood by one of ordinary skill in the art and the prosecution history
`pertaining to the patent. 37 C.F.R. § 42.100(b) (2020).
`For purposes of this Decision, we need not expressly construe any
`claim term. See Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795,
`803 (Fed. Cir. 1999) (holding that “only those terms need be construed that
`are in controversy, and only to the extent necessary to resolve the
`controversy”); see also Nidec Motor Corp. v. Zhongshan Broad Ocean
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`Motor Co. Matal, 868 F.3d 1013, 1017 (Fed. Cir. 2017) (citing Vivid Techs.
`in the context of an inter partes review).
`
`D. Asserted Obviousness of Claims 1–5 and 11 over Dusija and Sutardja
`Petitioner contends claims 1–5 and 11 are unpatentable under 35
`U.S.C. § 103(a) as obvious over Dusija and Sutardja. Pet. 27–50. In support
`of its showing, Petitioner relies on the declaration of Dr. David Liu. Id.
`(citing Ex. 1009).
`
`1. Dusija
`Dusija relates to error management for flash memory. Ex. 1010 ¶ 18.
`In particular, Dusija describes a flash memory with two different portions,
`where the second portion stores data at a higher density but with a smaller
`margin of error than the first portion. Id. In operation, “[d]ata is written to
`the second portion for efficient storage,” but if a post-write read reveals
`excessive error bits, “the data is rewritten or kept at the less error-prone first
`portion.” Id.
`In an embodiment, Dusija describes a memory array partitioned into
`two portions where “[t]he first portion 410 has the memory cells configured
`as lower density storage” and “[t]he second portion 420 has the memory
`cells configured as high density storage with each cell storing multiple bits
`of data.” Id. ¶ 109. Preferably, a first copy of a page of incoming data is
`written to “the high density second portion for the sake of efficiency and
`high capacity.” Id. ¶ 111. “Later, the first copy of the data page is read back
`in a ‘post write read’ to determine if there are any errors.” Id. ¶ 112. “If the
`number of error bits does not exceed the predetermined amount, the first
`copy . . . is deemed valid.” Id. ¶ 113.
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`Figure 14B illustrates a rewrite of a second copy of a data page and is
`reproduced below.
`
`
`Figure 14B shows the scenario where a post-write read of a first copy of a
`data page in a second portion of a flash memory detects a number of error
`bits in excess of a predetermined amount. See id. ¶¶ 116–117. In this case,
`a second copy of the data page is rewritten to the first portion of the flash
`memory and replaces the first copy as the valid copy. Id. ¶ 117. “[T]he first
`portion has each memory cell storing one bit of data and the second portion
`has each memory cell storing more than one bit of data.” Id. ¶ 118. Dusija
`notes that “the first portion will operate with a much wider margin of error
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`compared to that of the second portion” and “memory operations in the first
`portion will have less error than that in the second portion.” Id. ¶ 109.
`
`2. Sutardja
`Sutardja relates to a solid state memory system including two different
`non-volatile semiconductor memories that have different write cycle
`lifetimes. See Ex. 1011 ¶ 11. In Sutardja, a wear leveling module generates
`wear levels for the memories based on the respective write cycle lifetimes,
`and maps logical addresses to physical addresses of one of the memories
`based on the wear levels. Id. In an embodiment, Sutardja describes that
`“first solid-state nonvolatile memory 204 may include single-level cell
`(SLC) flash memory or multi-level cell (MLC) flash memory” and that
`“second solid-state nonvolatile memory 206” similarly may include SLC or
`MLC flash memory. Id. ¶ 108.
`Figure 7C, reproduced below, illustrates an aspect of the operation of
`“a hybrid nonvolatile solid-state (NVS) memory system using first and
`second NVS memories having different write cycle lifetimes and storage
`capacities.” Id. ¶ 145.
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`Prior to the operation shown in the flowchart of Figure 7C, logical addresses
`with low write frequencies are mapped to the first memory, and logical
`addresses with high write frequencies are mapped to the second memory,
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`and data is written according to the mappings. Id. ¶¶ 146–147. If a data
`shift analysis is called for, then, in step 520 in Figure 7C, it is determined
`whether the number of writes to a first block of the first memory during a
`predetermined time is greater than or equal to a threshold. Id. ¶ 149. If true,
`then the logical addresses corresponding to the first block are mapped to a
`second block in the second memory, in step 522. Id. Subsequently, in step
`524, it is determined whether the available memory in the second memory is
`less than a threshold, and if so, a least used block in the second memory is
`identified and the logical addresses corresponding to the least used block are
`mapped to a block in the first memory, in steps 526 and 528. Id. ¶ 150.
`
`3. Discussion
`Claim 1 recites “[a] system for storing data.” Petitioner contends, to
`the extent the preamble is limiting, that Dusija teaches the preamble by
`describing flash memory device 90 that includes memory array 200. Pet.
`28–29 (citing Ex. 1010, Fig. 1, ¶ 59; Ex. 1009 ¶ 112).
`Petitioner contends that Dusija teaches the claim 1 limitation “at least
`one MLC non-volatile memory module comprising a plurality of
`individually erasable blocks.” Pet. 29–31 (citing Ex. 1010, Figs. 6, 14A,
`¶¶ 77–79, 109; Ex. 1009 ¶¶ 113–115). For example, Petitioner argues that
`Dusija’s second portion 420 of memory array 200 is an MLC non-volatile
`memory module comprising a plurality of individually erasable blocks. Id.
`at 29.
`
`Petitioner contends that Dusija teaches the claim 1 limitation “at least
`one SLC non-volatile memory module comprising a plurality of individually
`erasable blocks.” Pet. 31–33 (citing Ex. 1010, Figs. 6, 14A, ¶¶ 77–79, 109;
`Ex. 1009 ¶¶ 116–117). For example, Petitioner argues that Dusija’s first
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`portion 410 of memory array 200 is a SLC non-volatile memory module
`comprising a plurality of individually erasable blocks. Id. at 31–32.
`Claim 1 further recites “a controller coupled to the at least one MLC
`non-volatile memory module and the at least one SLC non-volatile memory
`module.” Petitioner contends that Dusija discloses a controller 102 coupled
`to memory chip 100, which comprises a memory array 200, including the
`MLC and SLC modules. Pet. 33–35 (citing Ex. 1010, Fig. 1, ¶¶ 60, 117; Ex.
`1009 ¶¶ 119–121).
`Petitioner contends that Dusija’s controller is “adapted to” perform
`each of the remaining claim 1 limitations based on Dusija or Dusija in view
`of Sutardja. Pet. 35. For the claim 1 limitation “maintain an address map of
`at least one of the MLC and SLC non-volatile memory modules, the address
`map comprising a list of logical address ranges . . . ” that “maps to a similar
`range of physical addresses,” Petitioner contends that Dusija’s controller
`includes a directory that is a logical-to-physical address map that meets this
`limitation. Pet. 35–38 (citing Ex. 1010 ¶¶ 60–61, 111, 117, 129, 138, 164–
`168; Ex. 1028 ¶¶ 20, 34, 141, 154–155, 159, 163, 171; Ex. 1009 ¶¶ 123–
`138).
`
`Petitioner contends Dusija’s “post-write read” and “post-write read
`and adaptive rewrite” each separately teaches, or at least renders obvious,
`the claim 1 limitation “determine if a range of addresses listed by an entry
`and mapped to a similar range of physical addresses within the at least one
`MLC non-volatile memory module, fails a data integrity test, and, in the
`event of such a failure, the controller remaps the entry to the next available
`equivalent range of physical addresses within the at least one SLC non-
`volatile memory module.” Pet. 38–41 (citing Ex. 1010 ¶¶ 60, 87–88, 111–
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`117, 119–125, 153–154, 203; Ex. 1011 ¶¶ 105, 108, 111, 118, 123; Ex. 1028
`¶¶ 201–202; Ex. 1029, 2:53–3:14; Ex. 1009 ¶¶ 140–148).
`At this juncture of the proceeding, Patent Owner does not dispute
`Petitioner’s showing with respect to the above claim 1 limitations. See
`generally Prelim. Resp.
`Claim 1 recites “determine which of the blocks of the plurality of the
`blocks in the MLC and SLC non-volatile memory modules are accessed
`most frequently by maintaining a count of the number of times each one of
`the blocks is accessed.” Petitioner contends that Sutardja describes a wear
`leveling module as part of its controller that manages a memory that
`includes MLC and SLC blocks of memory. Pet. 42 (citing Ex. 1011 ¶¶ 106,
`108, 118, Claim 37). Petitioner further contends that the wear leveling
`module may track the number of times that each block has been erased or
`written that meets the limitation of “maintaining a count of the number of
`times each one of the blocks is accessed.” Id. (citing Ex. 1001, 6:30–33;
`Ex. 1009 ¶ 150; Ex. 1011 ¶¶ 111, 121, 147). Petitioner argues that
`Sutardja’s wear leveling module determines how frequently data is written
`to each of the logical addresses and that Sutardja uses the count to determine
`the most frequently written blocks to transfer to SLC memory (“determine
`which of the blocks of the plurality of the blocks in the MLC and SLC non-
`volatile memory modules are accessed most frequently by maintaining a
`count”). Id. (citing Ex. 1011 ¶¶ 112, 113, 149; Ex. 1009 ¶ 151).
`Patent Owner argues that “[t]here is no mention in Sutardja of
`determining how frequently data is written to each of the physical blocks.”
`Prelim. Resp. 38. Patent Owner further argues that determining “how
`frequently data is written to each of the logical addresses will not necessarily
`determine which of the physical blocks are accessed most frequently.” Id. at
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`38–39 (citing Ex. 2001 ¶¶ 46–48). Patent Owner also argues that Sutardja’s
`“data shift analysis” analyzes a single block for a predetermined time against
`a predetermined threshold with no mention of determining write frequencies
`of the physical blocks. Id. at 39–42 (citing Ex. 1011 ¶¶ 146–149; Ex. 2001
`¶¶ 49–52). Patent Owner recognizes that Sutardja describes that the wear
`leveling may track the number of times that each block has been erased or
`written, but contends that Sutardja does not mention determining those
`blocks that are accessed most frequently. Id. at 43 (citing Ex. 1011 ¶ 111).
`At this juncture of the proceeding, we are not persuaded by Patent
`Owner’s arguments that we should construe “blocks” to mean physical
`blocks. Id. at 38 (arguing that Sutardja fails to describe determining how
`frequently data is written to each of the physical blocks). Claim 1 does not
`recite “physical blocks” and Patent Owner has not directed us to sufficient
`evidence to support its implied construction. Dr. Khatri’s testimony also is
`based on an unsupported assumption that claim 1 requires “physical blocks,”
`and, therefore, is not particularly helpful. Ex. 2001 ¶¶ 46–49. At this
`juncture of the proceeding, we also are not persuaded by Patent Owner’s
`conclusory argument that there is no mention in Sutardja of determining
`blocks that are accessed most frequently, because Sutardja describes a wear
`leveling module that may “track the number of times that each block has
`been erased or written,” e.g., accessed and also describes determining
`whether the number of write operations to a block during a predetermined
`time is greater than a predetermined threshold.6 Ex. 1011 ¶¶ 111, 149.
`
`
`6 The ’298 patent describes blocks that are accessed to at least include blocks
`that are written to. Ex. 1001, 6:30–33; Ex. 1009 ¶ 150.
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`Claim 1 recites that the controller is adapted to “allocate those blocks
`that receive the most frequent writes by transferring the respective contents
`of those blocks to the at least one SLC non-volatile memory module.”
`Petitioner contends that Sutardja describes a data shift analysis that
`determines if “a number of write operations to a first block of the first NVS
`memory [i.e., MLC] during a predetermined time is greater than or equal to
`a predetermined threshold” then the “control maps the logical addresses that
`correspond to the first block to a second block of the second NVS memory
`[i.e., SLC memory module] in step 522.” Pet. 43–44 (citing Ex. 1011
`¶¶ 148–149, Fig. 7C, claim 37 (first memory is MLC and second memory is
`SLC); Ex. 1009 ¶¶ 154–156). Petitioner further contends that Sutardja’s
`data shift involves transferring the contents of MLC blocks to SLC blocks
`and updating the mapping table without the data changing. Id. at 43.
`Petitioner asserts that Sutardja discloses a second way to use the
`frequency count to transfer data from MLC memory to SLC memory.
`Specifically, Petitioner contends that upon receiving a host write to an MLC
`block, if the frequency count to that logical address is high, “it may direct
`the write to a physical SLC block, thereby transferring the data from MLC
`memory modules to SLC memory modules.” Id. at 44 (citing Ex. 1011
`¶¶ 146–147; Ex. 1009 ¶ 157).
`Patent Owner argues that Sutardja does not describe transferring data
`to SLC memory. Prelim. Resp. 44. Specifically, Patent Owner argues that
`Sutardja claim 37, which Petitioner relies on for the SLC memory, “does not
`limit the second memory to only SLC” because it recites that the second
`memory “includes” SLC. Id. Patent Owner further argues that Sutardja
`teaches that the first or second NVS can both comprise SLC and MLC flash
`memory. Id. 44–45 (citing Ex. 1011, claims 35–37). At this juncture of the
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`Patent 8,891,298 B2
`proceeding, Patent Owner’s arguments do not undermine Petitioner’s
`showing. Sutardja claim 1 recites that the second write cycle lifetime of the
`second NVS “is different than said first write cycle lifetime.” Ex. 1011,
`claim 1. Sutardja claim 37 depends from claim 1 and further recites
`“wherein said second NVS memory includes single-level cell (SLC) flash
`memory and said first NVS memory include multi-level cell (MLC) flash
`memory.” Patent Owner does not address Sutardja claim 1 in making the
`argument that claim 37 could mean that the second NVS memory could
`include both SLC and MLC. Lastly, and based on the current record, Patent
`Owner does not consider Dr. Liu’s testimony, which we determine is
`reasonable, that it would have been obvious to a person having ordinary skill
`in the art “to move frequently written blocks from a less durable storage
`medium (i.e., MLC) to a more durable storage medium (i.e., SLC).” Ex.
`1009 ¶ 150 (citing Ex. 1019, 511).
`Patent Owner also argues that Sutardja’s “data shift analysis” “merely
`analyzes a single block for a ‘predetermined time’ against a ‘predetermined
`threshold’” and that “Sutardja never explains when, if ever, the data shift
`analysis is performed . . . [o]r what the ‘predetermined time’ and
`‘predetermined threshold’ are.” Prelim. Resp. 39–40. Patent Owner’s
`arguments regarding when the data shift analysis is performed or what the
`predetermined time and predetermined threshold consist of are not
`commensurate in scope with apparatus claim 1 that does not recite any
`temporal requirements or a specific threshold.7 Moreover, Patent Owner’s
`
`
`7 For claim 11, which recites “the controller causes the transfer of content on
`a periodic basis,” Petitioner’s contentions that it would have been obvious
`that Sutardja’s data shift analysis is performed periodically is reasonable and
`
`19
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`IPR2021-01547
`Patent 8,891,298 B2
`argument that Sutardja performs its data shift analysis on a single block at a
`time also is not commensurate in scope with the claim language. Claim 1
`does not require that the controller is adapted to determine which blocks of
`the plurality of blocks are accessed most frequently all at once as Patent
`Owner seems to assert. Rather, the claim language may include determining
`the frequency of accesses one block at a time. Indeed, claim 1 explains that
`the determination is performed “by maintaining a count of the number of
`times each one of the blocks is accessed,” such that the determination may
`be performed one block at a time. Lastly, Patent Owner’s single block
`arguments (Prelim. Resp. 39–40) are directed only to Petitioner’s first
`showing with respect to the disputed limitation. Patent Owner does not
`address Petitioner’s assertions regarding the second showing with respect to
`this limitation, which we determine is reasonable. Pet. 44 (citing Ex. 1011
`¶¶ 146–147; Ex.1009 ¶ 157).
`Petitioner provides reasons to combine Dusija and Sutardja. Pet. 48–
`50. For example, Petitioner argues that Sutardja’s rationale for periodically
`remapping hot blocks to SLC to optimize cost and memory lifetime applies
`equally to Dusija’s system that also seeks to maximize memory lifetime. Id.
`at 48 (citing Ex. 1011 ¶ 102; Ex. 1010 ¶ 18; Ex. 1009 ¶ 175). Petitioner
`further argues that a person having ordinary skill in the art would have
`understood that mapping higher-usage logical addresses to SLC would
`improve access time, because access time to SLC cells was faster than MLC
`cells and that integrating those features into Dusija would further improve
`the speed of Dusija’s system. Id. at 48–49 (citing Ex. 1012 ¶¶ 7–8, 22; Ex.
`
`
`Patent Owner does not dispute Petitioner’s showing at this juncture of the
`proceeding. Pet. 46–47.
`
`20
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`IPR2021-01547
`Patent 8,891,298 B2
`1021, 3:45–58; Ex. 1010 ¶ 18; Ex. 1022 ¶ 18; Ex. 1019, 511; Ex. 1009
`¶¶ 176–177). Petitioner further provides reasons why a person having
`ordinary skill in the art would have had a reasonable expectation of success
`in adapting Dusija to include Sutardja’s hot blocks teaching. Id. at 49–50
`(citing Ex. 1010 ¶¶ 151, 154–160; Ex. 1009 ¶¶ 178–179).
`Patent Owner argues that Petitioner has not established a proper
`motivation to combine Dusija and Sutardja, and that there would have been
`no reasonable expectation of success for the combination. Prelim. Resp. 45–
`53. At this juncture of the proceeding, we determine that Patent Owner’s
`arguments do not undermine Petitioner’s reasons for combining Dusija and
`Sutardja.
`In particular, Patent Owner’s arguments are based on a rigid view of
`Dusija or Sutardja alone without considering what the combined teachings
`of Dusija and Sutardja would have suggested to a person having ordinary
`skill in the art. For example, Patent Owner argues that Dusija discloses a
`heterogeneous flash memory device directed to limited, infrequent use of
`SLC and post-write read checks in order to reduce error correction control
`(ECC) complexity and reduce performance degradation. Id. at 45–48 (citing
`Ex. 1010 ¶¶ 16–18, 24, 106), 50–53. Patent Owner argues that in contrast,
`Sutardja is directed to a homogeneous memory architecture including first
`and second NVS memory with dynamic wear leveling and remapping
`performed to ensure a consistent wear level across the first and second NVS
`memories. Id. at 46–48 (citing Ex. 1011 ¶ 111), 50–53. As such, and
`because “Dusija doesn’t state that it seeks to maximize memory lifetime,”
`Patent Owner argues that there is no shared goal of maximizing memory
`lifetime between Sutardja and Dusija that justifies a combination of the two
`references. Id. at 48–49.
`
`21
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`IPR2021-01547
`Patent 8,891,298 B2
`Patent Owner’s attorney arguments do not undermine Petitioner’s
`supported assertions that a person having ordinary skill in the art at the time
`of the invention would have understood that Dusija shares the goal of
`maximizing memory lifetime with Sutardja and that Sutardja and Dusija
`each disclose different and complementary improvements to the reliability of
`flash memory devices. Ex. 1009 ¶ 175 (citing Ex. 1010 ¶ 18). Based on the
`current record, a person having ordinary skill in the art at the time of the
`invention knew that a flash memory controller could implement multiple
`techniques that each improve the performance or reliability of the flash
`memory device. Ex. 1009 ¶ 175 (citing Ex. 1019, 39, Fig. 2.33). Based on
`the current record, we determine that it would have been reasonable to
`implement Sutardja’s hot block teachings in Dusija to create a system with
`multiple techniques to improve performance (memory lifetime).
`We have reviewed Petitioner’s showing for dependent claims 2–5 and
`11, and find such showing sufficiently persuasive at this stage of the
`proceeding. Pet. 45–47. At this juncture of the proceeding, Patent Owner
`does not make separate arguments for these claims. See generally Prelim.
`Resp. Based on the current record, we determine the information presented
`shows a reasonable likelihood that Petitioner would prevail in establishing
`that at least one of the challenged claims 1–5 and 11 would have been
`obvious over Dusija and Sutardja.
`
`E. Asserted Obviousness of Claims 8 and 9 over Dusija, Sutardja, and Li
`Petitioner contends claims 8 and 9 are unpatentable under 35 U.S.C.
`§ 103(a) as obvious over Dusija, Sutardja, and Li. Pet. 50–51. In support of
`its show
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