`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`APPLE INC.
`Petitioner
`
`v.
`
`FUTURE LINK SYSTEMS, LLC
`Patent Owner
`____________
`
`
`Case No. IPR2021-01488
`U.S. Patent No. 6,807,505
`____________
`
`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,807,505
`
`
`
`IPR2021-01488
`U.S. Patent No. 6,807,505
`
`TABLE OF CONTENTS
`
`
`INTRODUCTION ............................................................................... 1
`I.
`SUMMARY OF THE ’505 PATENT .................................................. 1
`II.
`THE ’505 PATENT’S ALLEGED INVENTION ..................................................... 1
`A.
`THE ’505 PATENT’S PROSECUTION ................................................................ 8
`B.
`C. OVERVIEW OF PROPOSED GROUNDS .............................................................. 9
`D. A PERSON HAVING ORDINARY SKILL IN THE ART .........................................10
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ................ 10
`A.
`STANDING UNDER 37 C.F.R. § 42.104(A) ....................................................10
`B.
`CHALLENGE UNDER 37 C.F.R. § 42.104(B) AND RELIEF REQUESTED ............11
`C.
`CLAIM CONSTRUCTION UNDER 37 C.F.R. § 42.104(B)(3) .............................12
`IV. THE CHALLENGED CLAIMS ARE UNPATENTABLE ................ 14
`A. GROUND 1: CLAIMS 1, 6, AND 8 WOULD HAVE BEEN OBVIOUS UNDER PRE-AIA
`35 U.S.C. § 103 OVER HONG IN VIEW OF THE KNOWLEDGE OF A POSITA ....14
`V. DISCRETIONARY CONSIDERATIONS ......................................... 44
`THE FINTIV FACTORS FAVOR INSTITUTION....................................................44
`A.
`VI. CONCLUSION ................................................................................... 54
`VII. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1) .............. 55
`A.
`REAL PARTY-IN-INTEREST ...........................................................................55
`B.
`RELATED MATTERS .....................................................................................55
`C.
`LEAD AND BACK-UP COUNSEL ....................................................................55
`APPENDIX OF EXHIBITS ......................................................................... 56
`
`
`
`i
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`
`
`I.
`
`INTRODUCTION
`
`IPR2021-01488
`U.S. Patent No. 6,807,505
`
`Petitioner Apple Inc. (“Petitioner”) requests an Inter Partes Review (“IPR”)
`
`of claims 1, 6, and 8 (the “Challenged Claims”) of U.S. Patent No. 6,807,505 (“the
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`’505 Patent”).
`
`II.
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`SUMMARY OF THE ’505 PATENT
`
`A.
`
`The ’505 Patent’s Alleged Invention
`
`The ’505 Patent describes an alleged improvement to existing boundary scan
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`circuit testing. ’505 Patent (Ex. 1001), 2:17-24. Boundary scan circuit testing was
`
`developed in the 1980s by a group of manufacturers called the “Joint Test Action
`
`Group,” or JTAG, who in 1990 codified a testing technique in Institute of Electrical
`
`and Electronics Engineers (“IEEE”) Standard 1149.1 that has since evolved into a
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`family of related standards published as recently as 2013. See JTAG boundary-scan,
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`firmly based on IEEE standards,” JTAG Technologies, (last visited Sep. 1, 2021),
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`https://www.jtag.com/jtag-boundary-scan-firmly-based-on-ieee-standards/
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`(explaining the history and evolution of the original IEEE 1149.1 standard) (Ex.
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`1002). The ’505 Patent describes the standard by citing to an article co-authored by
`
`inventor Franciscus G. M. De Jong (“De Jong Article”). ’505 Patent (Ex. 1001),
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`1:24-28. Figure 1-19 of that article depicts the IEEE standard for boundary scan
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`circuitry on an integrated circuit (“IC”):
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`1
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`IPR2021-01488
`U.S. Patent No. 6,807,505
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`
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`De Jong Article (Ex. 1003), 13 (annotated). As depicted in the figure, the typical
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`boundary scan circuity is designed to test interconnects (i.e., buses)1 that feed
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`information to and from a circuit using four dedicated testing pins collectively
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`referred to as the Test Access Port to the circuit and a test controller (also called a
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`
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`1 A POSITA would have considered buses to be interconnects. Liu Dec. (Ex. 1004),
`
`¶ 33 (explaining that the ’505 Patent at 1:7-15 and 2:25-49 describes its object as
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`testing interconnects between electronic circuits, which the patent specifies as the
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`address and data buses between them at 6:18-7:25 and 7:26-54).
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`
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`2
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`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`state machine) that controls the serial shift of test data through boundary-scan cells
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`connected to the input and output (“I/O”) nodes of a circuit. ’505 Patent (Ex. 1001),
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`1:28-61.
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`According to the ’505 Patent, synchronous dynamic random access memory
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`(“SDRAM”) devices had “highly standardised pin lay-out[s]” incompatible with the
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`dedicated TDI, TDO, TMS, and TCK test pins required in a conventional boundary
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`scan architecture. Id. at 5:56-6:1 (describing the structured pin layout2 of an SDRAM
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`device obstructed by typical boundary scan test pins); see also id. at 4:19-24
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`(describing pin count and compatibility constraints). To avoid the need for these
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`additional test pins, the ’505 Patent proposes an “alternative” to the traditional
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`boundary scan testing standard that replaces its state machine and dedicated test pins
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`for a “low complexity memory” that can be used to accomplish much of the same
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`interconnect testing. Id. at 2:25-44 (describing interacting with such low-complexity
`
`
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`2 A POSITA would have recognized circuit pins as circuit input and output nodes.
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`Liu Dec. (Ex. 1004), ¶ 34 (explaining that the ’505 Patent at Fig. 1 and 5:46-59
`
`discloses an SDRAM device “pin lay-out” that also “schematically shows which I/O
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`nodes are generally present on an SDRAM device” and concluding the ’505 Patent
`
`refers to pins and I/O nodes interchangeably).
`
`3
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`memory to test address and data interconnects), 6:5-9 (describing the low-
`
`complexity memory as an alternative to an “ordinary boundary-scan test unit”). In
`
`one example, interconnects are tested by sending a unique combination of address
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`bits over an address bus to a location in the low-complexity memory, writing known
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`test data bits previously stored at that address to a data bus, such that both the address
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`and data bus operations are tested when the test pattern written to the data bus match
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`the expected response. Id. at 6:18-7:25 (describing address bus testing), 7:26-54
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`(describing data bus testing), 8:31-55 (describing the configuration of circuitry in
`
`the testing embodiment of Figure 2). According to the ’505 Patent, low-complexity
`
`memories avoid complicated access protocols, lengthy initialization procedures, and
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`dynamic restrictions of high complexity memories such as SDRAM. Id. at 3:56-
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`4:18. Such low complexity memories can be traditional memory structures such as
`
`SRAM or ROM, but may also be even simpler structures such as data registers. Id.
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`at 4:57-63 (describing SRAM and ROM low complexity memories), 12:51-52
`
`(claiming a test unit that “comprises a read/write register”).
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`Figure 1 depicts one layout of address, data, and control interconnects (nodes)
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`connected to a test unit 120 that is operable as a low-complexity memory, which
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`internally interfaces with the core logic unit 110 (e.g., an SDRAM circuit):
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`4
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`IPR2021-01488
`U.S. Patent No. 6,807,505
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`Id. at Fig. 1 (annotated), 5:56-6:9. The ’505 Patent describes mode-based node
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`
`
`connections:
`
`In a normal mode of the circuit 100, the test unit 120 is transparent, and
`signals can pass freely between the I/O nodes 130 and the main unit
`110. In a test mode of the circuit 100, the main unit 110 is logically
`disconnected from the I/O nodes 130 and the test unit 120 is in control.
`
`Id. at 5:46-50.
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`
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`
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`5
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`Fig. 2 below illustrates how such a device may interact with an external testing
`
`device in the “test mode”:
`
`Id. at Fig. 2 (annotated).
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`6
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`As an alternative to memory structures, the test unit may instead comprise a simple
`
`combinatorial logic circuit with “Exclusive-OR” (or “XOR”) gates like the ones
`
`depicted by Fig. 6:
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`
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`Id. at Fig. 6 (annotated), 11:62-12:2. Because each known set of input bits will
`
`correspond to a known output from the logic gates, this combinatorial circuit
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`“implements the functionality of a ROM table,” allowing the system to input known
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`patterns of bits and confirm the outputs match the expected responses. Id. at 9:57-67
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`(describing the operation of the combinatorial implementation), 2:35-54 (“It is
`
`important that particular input data for the test unit, i.e., the address, result in output
`
`
`
`7
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`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`data from the test unit that are [sic] known a priori, i.e. the stored data.”). The
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`following table illustrates twelve patterns of five bits than can be used to confirm the
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`proper operation of five input and two outputs using combinatorial logic circuits:
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`Id. at 11:7-24. The Challenged Claims focus on this combinatorial embodiment in
`
`
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`which the test unit comprises XOR logic gates.
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`B.
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`The ’505 Patent’s Prosecution
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`The Application that resulted in the ’505 Patent is a divisional application of
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`parent application 09/402,154 filed on January 29, 1999, under the provisions of the
`
`Patent Cooperation Treaty. ’505 Patent (Ex. 1001). The Application claims earliest
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`foreign priority to European Patent application 98200288, filed February 22, 1998.
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`Id. For purposes of this petition and without waiving its right to challenge priority
`
`
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`8
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`in this or any other proceeding, Petitioner adopts February 22, 1998, as the invention
`
`date for the Challenged Claims.
`
`No prior art-based rejections were issued during prosecution. The Examiner
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`issued a notice of allowability on May 4, 2004 and cited European Patent (EP)
`
`publication 0,588,507 A2 of Williams, Great Britain Patent 2,278,689 of Thatcher,
`
`et al., U.S. Patent 5,103,450 of Whetsel, U.S. Patent 5,416,409 of Hunter, and U.S.
`
`Patent 5,781,559 of Muris, et al. ’505 File History (Ex. 1005) at 47. In the reasons
`
`for allowance, Examiner stated: “[t]he prior art of record neither discloses nor
`
`suggests normal and test interconnects wherein the test input unit includes at least
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`one combinatorial circuit with at least two inputs and a function output, thus testing
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`particular I/O nodes.” Id.
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`C. Overview of Proposed Grounds
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`The ’505 Patent purports to have simplified interconnect testing as a result of
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`the “highly standardized pin lay-out” of SDRAM units in the late 90s, which were
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`allegedly incompatible with the dedicated test pins required of traditional boundary
`
`scan test architectures. ’505 Patent (Ex. 1001), 5:56-6:5. But the claims are not so
`
`limited. Rather, the Challenged Claims are more broadly directed to test units
`
`implementing combinatorial circuit functionalities and are not limited to the
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`
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`9
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`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`SDRAM circuits that were the ostensible focus of the alleged invention. In fact, the
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`Challenged Claims are not even limited to structures that avoid dedicated test pins.
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`As a consequence of the stark divide between the narrow focus of the ’505
`
`Patent’s disclosure and its broad claims, the simple structures recited in the
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`Challenged Claims were well represented in the prior art long before the ’505 Patent.
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`Hong—filed nearly two decades before the ’505 Patent—demonstrates that XOR
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`gates have long been used as a very simple means of testing circuit interconnects.
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`Hong (Ex. 1006), 1:44-50 (describing a multi-input, single output Exclusive-OR
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`circuit used to test interconnections).
`
`D. A Person Having Ordinary Skill in the Art
`
`A person of ordinary skill in the art (“POSITA”) at the time of the ’505 Patent
`
`would have had at least a bachelor’s degree in electrical engineering or equivalent
`
`with at least one year of experience in the field of circuit design or circuit testing.
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`Additional education or experience might substitute for the above requirements. Liu
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`Dec. (Ex. 1004), ¶¶ 30-32.
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`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
`
`A.
`
`Standing Under 37 C.F.R. § 42.104(A)
`
`Petitioner certifies that the ’505 Patent is available for IPR and that Petitioner
`
`is not barred or estopped from requesting an IPR challenging the claims of the ’505
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`
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`10
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`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`Patent. Specifically, (1) Petitioner is not the owner of the ’505 Patent, (2) Petitioner
`
`has not filed a civil action challenging the validity of any claim of the ’505 Patent,
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`and (3) this Petition is filed less than one year after the Petitioner was served with a
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`complaint alleging infringement of the ’505 Patent.
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`B. Challenge Under 37 C.F.R. § 42.104(B) and Relief Requested
`
`In view of the prior art and evidence presented, claims 1, 6, and 8 of the ’505
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`Patent are unpatentable and should be cancelled. 37 C.F.R. § 42.104(b)(1). Further,
`
`based on the prior art references identified below, IPR of the Challenged Claims
`
`should be granted. 37 C.F.R. § 42.104(b)(2).
`
`Proposed Ground of Unpatentability
`Ground 1: Claims 1, 6, and 8 are obvious under pre-AIA 35
`U.S.C. § 103 over U.S. Patent 4,241,307 (“Hong”) in View of
`the Knowledge of a POSITA
`
`Section IV identifies where each element of the Challenged Claims is found
`
`Exhibits
`Ex. 1006
`
`in the prior art. 37 C.F.R. § 42.104(b)(4). The exhibit numbers of the evidence relied
`
`upon to support the challenges are provided above and the relevance of the evidence
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`to the challenges raised is provided in Section IV. 37 C.F.R. § 42.104(b)(5). Exhibits
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`1001-1011 are also attached.
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`
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`11
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`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`C. Claim Construction Under 37 C.F.R. § 42.104(B)(3)
`
`In this proceeding, claims are interpreted under the same standard applied by
`
`Article III courts (i.e., the Phillips standard). See 37 C.F.R § 42.100(b); see also 83
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`Fed. Reg. 197 (Oct. 11, 2018); Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed.
`
`Cir. 2005) (en banc). Under this standard, words in a claim are given their plain
`
`meaning which is the meaning understood by a person of ordinary skill in the art in
`
`view of the patent and file history. Phillips, 415 F.3d 1303, 1212–13.
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`a. “Testing the interconnects”
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`Claim 1 recites a test unit for “testing the interconnects” connecting the input
`
`and output nodes of one electronic circuit to a further electronic circuit. ’505 Patent
`
`(Ex. 1001), Claim 1. The ’505 Patent is a division of the application that issued as
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`U.S. Patent No. 6,622,108 (“the ’108 Patent”), which is the subject of a separate
`
`request for Inter Partes Review filed by Petitioner. The ’108 Patent was previously
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`the subject of a patent infringement lawsuit in the District of Delaware in which the
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`court issued a Markman Order construing the same “testing the interconnects”
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`language that appears on the ’505 Patent Challenged Claims. Memorandum Opinion
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`(Ex. 1007), 20-21. In that prior litigation, Patent Owner argued “testing the
`
`interconnects” should be construed as “applying test data to one end of an
`
`interconnect and observing response data at the other end.” Id. at 20. The court
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`12
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`accepted this definition because “Future Link’s construction is taken from a
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`paragraph of the specification that is discussing the claimed invention” rather than
`
`the boundary scan test standard itself. Id. at 21-22.
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`For the purposes of this proceeding, Petitioner proposes that the Board adopt
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`the construction that Patent Owner previously advanced in the D. Del. litigation and
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`construe “testing the interconnects” as “applying test data to one end of an
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`interconnect and observing response data at the other end,” without prejudice to
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`Petitioner’s right to propose an alternative construction in the co-pending W.D. Tex.
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`Litigation.3
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`
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`3 This approach is consistent with PTAB practice. See 10X Genomics, Inc. v. Bio-
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`Rad Labs., Inc., IPR2020-00088, Paper 8 at 14-18 (PTAB Apr. 27, 2020) (finding
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`petition based on constructions Patent Owner was expected to advance in parallel
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`litigation consistent with the pertinent statutes, rules, Trial Practice Guide, and prior
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`panel decisions); Western Digital Corp. v. Spex Techs., Inc., IPR2018-00084, Paper
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`14 at 12 (PTAB Apr. 25, 2018) (finding Petition based on claim constructions urged
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`by Patent Owner is proper and noting Petitioner is not required to express its
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`subjective agreement regarding correctness of the proffered claim construction or
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`13
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`IV. THE CHALLENGED CLAIMS ARE UNPATENTABLE
`
`A. Ground 1: Claims 1, 6, and 8 would have been obvious under pre-
`AIA 35 U.S.C. § 103 over Hong in View of the Knowledge of a
`POSITA
`Overview of Hong
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`U.S. Patent 4,241,307 to Se June Hong (“Hong”) (Ex. 1006) issued on
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`December 23, 1980, and is prior art to the ’505 Patent under at least 35 U.S.C. §§
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`102(b) (pre-AIA). Hong was not cited or considered during prosecution of the ’505
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`Patent. ’505 Patent (Ex. 1001).
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`Hong discloses a “module interconnection testing scheme.”4 Hong (Ex. 1006),
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`Title. This scheme “relates to the testing of connections between modules mounted
`
`
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`take ownership of the construction); Gen. Elec. Co. v. Vestas Wind Systems A/S,
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`IPR2018-00928, Paper 9 at 12-17 (PTAB Nov. 5, 2018). Petitioner takes no position
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`at this time as to whether Patent Owner’s construction is the correct one under
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`Phillips.
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`4 A POSITA would have recognized Hong’s “interconnection” as synonymous in
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`structure and operation to an “interconnect.” Liu Dec. (Ex. 1004), ¶ 40 (noting the
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`’505 Patent describes testing for short circuits and “stuck-at 1” and “stuck-at 0”
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`faults between “interconnects” at 6:66-7:20 in an address bus and at 7:26-41 in a
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`14
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`on cards and more particularly to circuitry in the modules to provide simple testing
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`of such connections.” Id. at 1:7-10. Hong explains that after module circuits are
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`assembled on a card, “what really needs to be tested . . . [are] the connections
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`between the modules and the card” because “generating tests for defective pin
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`connections becomes an enormous task.” Id. at 1:11-24. Hong’s modules mounted
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`on a card are depicted in Figs. 3 and 4 below:
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`Id. at Figs. 3-4 (annotated to show card-mounted modules).
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`data bus, and concluding the interconnect testing in the ’505 Patent is identical to
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`“testing for shorts between the different interconnection networks” and “testing for
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`simple stuck 1’s or 0’s in those networks” Hong describes at 3:15-21).
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`15
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`Hong describes two module embodiments: a first, “simple” embodiment that
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`allows interconnection testing for “simple stuck 1’s or 0’s,” and a second, “complex”
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`embodiment that tests for “shorts between the different interconnection networks on
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`the card in addition to testing for simple stuck 1’s or 0’s.” Id. at 3:15-19 (emphasis
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`added). The embodiments share most circuit components:
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`
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`Id. at Figs. 1, 3 (annotated to show similar structure), 2:25-46 (describing first
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`embodiment circuitry components), 3:22-34 (describing second embodiment
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`circuitry components). A POSITA would have recognized the module circuitry
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`replicated by both embodiments operates similarly. Liu Dec. (Ex. 1004), ¶¶ 40-41
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`(noting Hong describes the second embodiment as a “more complex embodiment”
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`following the first, “simple embodiment” that “test[s] for simple stuck 1’s or 0’s”
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`but adds the option of “testing for shorts” at 3:15-20 (emphases added), also noting
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`Hong applies consistent numerals and descriptions to the module input pins, output
`16
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`pins, logic circuits, and Exclusive-OR circuits of both the first and second
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`embodiments, and concluding these components operate identically in the
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`embodiments to preserve the testing functions of the first embodiment in the second
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`embodiment).
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`Hong’s modules operate in either (1) a normal mode with the input and output
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`pins connected to the logic circuits or (2) a test mode with the input and output pins
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`connected to the Exclusive-OR circuits:
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`During normal operation, that is, operation when the modules are not
`being tested, a binary 1 is applied to each of the terminals 12b. This
`connects the output lines [20]5 of the logic circuits to the output
`terminals 14 so the circuits 16 on the cards can perform in their intended
`manner. When the circuits are to be tested a binary 0 is applied to
`terminals 12b on all the modules. This ungates the connection between
`the output lines [20] of the original logic circuits and the terminals and
`instead connects all the terminals to line 26 so that test signals can be
`applied to the output terminals by their application to the card terminal
`connected to terminals 12a on all the modules.
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`
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`5 Hong’s Fig. 1 labels the output lines from the logic circuits with “20,” but the
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`description of these circuits uses the label, “21.” Liu Dec. (Ex. 1004), ¶ 42. For
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`clarity and to align the description with the figures, Petitioner has replaced “21” with
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`“20” in excerpts from the specification discussing these output lines both here and
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`in subsequent citations to the same.
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`17
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`Hong (Ex. 1006), 2:52-64 (emphases added). The normal mode signal flow through
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`the logic circuit is annotated in Fig. 1 below:
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`
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`Id. at Fig. 1 (annotated). As illustrated in Fig. 4, multiple modules are placed on a
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`single card such that the outputs of a first module are connected as the input to an
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`adjacent module. Id. at Fig. 4, 2:47-51 (noting the invention requires multiple
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`modules on a single card). To best illustrate the signal flow in test mode, two
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`modules (from Fig. 1) are placed side-by-side below and the signal flow during test
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`mode (blue) is depicted below:
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`18
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`
`
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`Id. at Fig. 1 (annotated to illustrate a test mode signal flow in which test data input
`
`through node 12a becomes the input to half-select circuits 24, the half-select circuits
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`24 output through output pins 14, which become inputs to input pins 12 in the
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`adjacent module, and where each such input flows through XOR gate 22, producing
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`the test output on output node 14a). In this test mode, Hong explains that the modules
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`can be tested to identify whether any pin is stuck at binary 0 or binary 1. Id. at 2:58-
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`3:5 (explaining that inputting a binary 0 on input pin 12a and obtaining a binary 1 at
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`output pin 14a indicates that some pin (e.g., output pins 14 or input pins 12) is stuck
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`at binary 1 and that inputting a binary 1 on input pin 12a and obtaining a binary 0 at
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`output pin 14a indicates that some pin (e.g., output pins 14 or input pins 12) is stuck
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`at binary 0).
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`19
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`Hong’s second embodiment adds complexity to the module’s test circuitry by
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`incorporating a shift register that works in tandem with the Exclusive-OR circuit,
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`which allows the test unit to identify “shorts between the different interconnection
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`networks on the card in addition to testing for simple stuck 1’s or 0’s.” Id. at 3:15-
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`21. This more complex embodiment is illustrated in annotated Fig. 3 below:
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`
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`Id. at Fig. 3 (annotated), 3:22-56 (describing the same).
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`Hong depicts the flow of the binary patterns among the interconnections
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`between modules in Figure 4, which is a “schematic view of a card containing the
`
`embodiment of Fig. 3 with test signals superimposed on the terminals and pins of
`
`the card”:
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`
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`20
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`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`
`
`
` Id. at Fig. 4 (annotated), 2:20-22.
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`Because Hong, like the ’505 Patent, discloses an electronic circuit that
`
`facilitates interconnect testing by connecting the I/O nodes to a test unit in a test
`
`mode and by connecting the I/O nodes to a main unit in a normal mode, Hong is in
`
`the same field of endeavor as the ’505 Patent. Compare Hong (Ex. 1006), 3:15-27
`
`(describing “testing” where “each module includes an Exclusive-OR circuit . . . with
`
`an input coupled to each of the module input pins” and its “output connected to a
`
`stage . . . in a shift register” where the module’s output pins are also “connected to a
`
`stage . . . of the same shift register”), 2:52-57 (describing a control signal for
`
`
`
`21
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`connecting terminals to output lines of module logic circuitry in “normal operation”
`
`so the circuits “can perform in their intended manner” when “the modules are not
`
`being tested”), with ’505 Patent (Ex. 1001), 1:7-15 (“The invention relates to an
`
`electronic circuit comprising: a plurality of input/output (I/O) nodes for connecting
`
`the electronic circuit to a further electronic circuit via interconnects, a main unit for
`
`implementing a normal mode function of the electronic circuit, and a test unit for
`
`testing the interconnects, the electronic circuit having a normal mode in which the
`
`I/O nodes are logically connected to the main unit and a test mode in which the I/O
`
`nodes are logically connected to the test unit.”), 11:62-12:2 (“The test unit . . . has a
`
`three-input XOR gate . . . which implements the exclusive-or function between the
`
`input pins . . . and the output pin[.]”).
`
`Hong is therefore analogous art to the ’505 Patent. Liu Dec. (Ex. 1004), ¶¶ 46-
`
`47.
`
`
`
`Claim 1
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`1[P] An electronic circuit comprising:
`
`Hong discloses “testing . . . interconnections between modules mounted on a
`
`card.” Hong (Ex. 1006), Abstract (emphasis added). Depicted below, Figure 3 shows
`
`“connections between . . . module pins and the card wiring” while Figure 4 shows
`
`
`
`22
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`“a card containing the embodiment of Fig. 3 with test signals superimposed on the
`
`terminals and pins of the card.”
`
`
`
`Id. at 2:15-34, Figs. 3-4 (annotated). A POSITA would have recognized each of
`
`Hong’s modules as an electronic circuit. Liu Dec. (Ex. 1004), ¶ 48 (noting Hong
`
`describes the interconnected, card-mounted modules as “subassembly circuit
`
`packages with logic circuitry thereon . . . mounted on a insulative base with an
`
`interconnecting network for interconnecting the input and output terminals of the
`
`subassembly circuit packages” at 5:24-28 (emphasis added) and concluding Hong
`
`uses “modules” and “circuit packages” interchangeably).
`
`1[a] a plurality of input/output (I/O) nodes for connecting the electronic circuit to
`a further electronic circuit via interconnects,
`
`Hong describes “testing . . . interconnections between modules mounted on a
`
`card . . . for stuck ones and zeros.” Id. at Abstract. Each module has a “plurality of
`23
`
`
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`both input pins 12 and output pins 14.” Hong (Ex. 1006), 2:25-27. Fig. 3 illustrates
`
`this arrangement with respect to Hong’s more complex embodiment:
`
`
`
`Id. at Fig. 3 (annotated to show module input and output pins); see also id. at Fig. 1
`
`(illustrating same arrangement, including input pins 12 and output pins 14 and 14a).
`
`Although Hong describes the input and output pins with respect to a first
`
`embodiment corresponding to Figure 1, a POSITA would have recognized the pins
`
`in Figure 3 of Hong’s second embodiment have the same structure and operation as
`
`those in the first embodiment. Liu Dec. (Ex. 1004), ¶¶ 49-50 (noting Hong identifies
`
`and describes the “input pins 12” and “output pins 14” of Figure 3 at 3:22-27 in
`
`
`
`24
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`identical fashion to the first embodiment’s “input pins 12” and “output pins 14”
`
`described at 2:25-31 and depicted in Figure 1, and concluding the pins replicated in
`
`both embodiments have equivalent structure and functionality).
`
`The input and output pins “are connected by conductors . . . on the card . . .
`
`to output and input pins of other modules on the card[.]” Hong (Ex. 1006), 2:27-30
`
`(emphasis added).
`
` Id. at Fig. 3 (annotated to show conductors). The conductors 13 are used to “permit[]
`
`the testing of interconnection nets on the cards.” Id. at 2:15-19. Figure 4 “contain[s]
`
`
`
`
`
`25
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`the embodiment of Fig. 3” and depicts this module-to-module interconnection
`
`testing:
`
`
`
`Id. at Fig. 4 (annotated), 2:20-22. A POSITA would have recognized the conductors
`
`as interconnections. Liu Dec. (Ex. 1004), ¶ 51 (noting Hong discloses an “object of
`
`the invention [is] to simplify the testing of connections between module pins and
`
`conductors on the cards” at 1:66-68 and concluding these connections are the same
`
`as the “pins 12 and 14 . . . connected by conductors 13 on the card” at 2:27-30
`
`(emphases added)).
`
`1[b] a main unit for implementing a normal mode function of the electronic
`circuit,
`
`
`
`26
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`Hong describes a main unit in terms of “logic circuits on each of the modules
`
`mounted on the card”). Hong (Ex. 1006), 1:24-29 (emphasis added).
`
`Id. at Fig. 1 (annotated), 2:32-35 (describing logic “circuits 16” in first embodiment).
`
`The same type of logic circuitry is replicated in the second embodiment:
`
`
`
`
`
`27
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`
`
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`Id. at Fig. 3 (annotated), 3:31-34 (describing logic circuitry in second embodiment).
`
`The logic circuitry drives normal module function:
`
`During normal operation, that is, operation when the modules are not
`being tested, a binary 1 is applied to each of the terminals 12b. This
`connects the output lines [20] of the logic circuits to the output
`terminals 14 so the circuits 16 on the cards can perform in their
`intended manner.
`
`Id. at 2:52-57 (emphases added). In its normal state, “[logic] circuits 16 on each of
`
`the modules are connected to the input pins 12 by input lines 18 and the output pins
`
`
`
`28
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`14 by output lines [20].” Id. at 2:32-34. This normal mode signal flow through the
`
`logic circuit is annotated in Fig. 1 below:
`
`
`
`Id. at Fig. 1 (annotated). A POSITA would have recognized Hong’s second
`
`embodiment uses the same logic circuitry functionality described in the first
`
`embodiment. Liu Dec. (Ex. 1004), ¶¶ 52-53 (noting Hong describes a plurality of
`
`“logic circuits on each of the modules” at 1:24-29, a first embodiment with “circuits
`
`16” at 2:31-33 depicted as “logic circuits” in Figure 1, and a second embodiment
`
`with “logic circuits 25” at 3:31-34 depicted as “logic circuits” in Figure 3, and
`
`
`
`29
`
`
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`IPR2021-01488
`U.S. Patent No. 6,807,505
`concluding the plurality of logic circuits have the same structure and functionality
`
`in both embodiments).
`
`1[c] and a test unit for testing the interconnects,
`
`Hong teaches a test unit comprising XOR gates and half-select circuits 24 that
`
`allow logically disconnecting the main unit from the I/O nodes and shifting test data
`
`in such that input pins 12 and output pins 14 (interconnects) can be tested to ensure
`
`no pin is stuck at a binary 1 or binary 0:
`
`When the circuits are to be tested a binary 0 is applied to terminals
`12b on all the modules. This ungates the connection between the
`output lines [20] of the original logic circuits and the terminals and
`instead connects all the terminals to line 26 so that test signals can be
`applied to the output terminals by their application to the card
`terminal connected to terminals 12a on all the modules. The test
`signals are a binary 0 followed by a binary 1. The first signal tests
`for any pin stuck at 1. If the card tests good, a binary 0 will appear at
`the card terminal connected to module terminals 14a, if not a binary 1
`appears at this terminal.
`The second signal tests for any pin stuck at binary 0. If the card tests
`good a binary 1 will appear in response to the test, while a bad card will
`produce a binary 0 in response thereto.
`
`Hong (Ex. 1006), 2:52-63:4 (emphases added); Liu Dec. (Ex. 1004), ¶¶ 54-56
`
`(explaining that properly
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