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`Attomey Docket No. I PHN 17,203A
`Rrst Inventor I Franciscus G.
`UTILITY
`DeJong
`PATENT APPLICATION
`
`
`CIRCUIT WITH INTERCONNECT TEST UNIT AND METHOD OF
`(Only for new nonprovisional applications under 37 C.F.R. 1.53(b))
`
`
`Tille TESTING INTERCONNECTS BETWEEN A FIRST ANO A SECOND
`TRANSMITTAL
`ELECTRONIC CIRCUIT
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`181 Divisional D Continuation-In-part
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`IPR2021-01488
`Apple EX1005 Page 1
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`IPR2021-01488
`Apple EX1005 Page 2
`
`

`

`WO 99/39118
`
`
`
`PCTnB99/00l 71
`
`CIRCUIT WITH INTERCONNECT TEST UNIT AND A METHOD OF TESTING INTERCONNECTS BETWEEN A FIRST
`AND A SECOND ELECTRONIC CIRCUIT
`
`
`
`
`
`
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`circuit to a further electronic circuit via
`
`
`
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`The invention relates to an electronic circuit comprising: a plurality of
`
`input/output (l/O) nodes for connecting the electronic
`
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`interconnects, a main unit for implementing a normal mode function of the electronic circuit,
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`and a test unit for testing
`
`
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`nonnal mode in the interconnects, the electronic circuit having a
`
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`connected 5 which the l/O nodes are logically to the main unit and a test mode in which the l/O
`
`
`
`
`
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`nodes are logically connected to the test unit.
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`
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`The invention further relates to a method of testing interconnects between a first
`
`
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`
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`
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`
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`electro
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`
`
`
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`circuit comprising a main nic circuit and a second electronic circuit, the first electronic
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`unit implementing a normal mode function of the first electronic circuit, and a test unit for
`
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`10 testing the interconnects, the method comprising the steps of logically connecting
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`the test unit
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`to the interconnects, and putting test data on the interconnects by the second electronic circuit.
`
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`Such a circuit is known from "Boundary-scan test, a practical approach", H.
`
`
`
`Bleeker, P. van den Eijnden and F. de Jong, Kluwer, Boston, 1993, ISBN 0-7923-9296-5,
`
`
`
`
`
`
`
`
`
`
`
`Figures 1-19, which shows an integrated (IC) in accordance with the boundary-scan test
`
`15 standard IEEE Std. 1149.1.
`
`for providing
`
`
`
`
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`some arbitrary specified function in a normal mode of the circuit. The known
`
`The known circuit has a main unit or core logic that is responsible
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`circuit
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`test, i.e. a test further has a test unit for in a test mode performing an interconnect
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`whether the circuit is pr,operly connected to a further circuit via its 1/0 nodes or IC pins.
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`Efficient interconnect
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`test of miniaturised and/or
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`20 part of the production process of such assemblies. The boundary-scan test technique is
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`co�plex circuit assemblies is a necessary
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`test. It is available in most of accepted as standardised solution for interconnect
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`the leading
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`
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`·microprocessor
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`families and is supported
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`for in-house developed application specific
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`!Cs
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`through automated tools in the IC design process.
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`The test unit of the known boundary-scan circuit includes a test control unit or
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`25 Test Access Port controller and a shift register or boundary-scan register along the circuit
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`
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`to the boundary, cells of the shift register being connected to·VO nodes c�rresponding
`interconnects
`
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`states machine controlling to be tested. The test control unit has a state
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`
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`of the
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`shift register, examples
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`
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`in/out data into the for shifting of such states being a shift state
`shift
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`
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`register
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`and a capture
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`tlie shift from the interconnects into state for capturing data originating
`
`
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`CONFIRMATION COPY
`
`IPR2021-01488
`Apple EX1005 Page 3
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`

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`2
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`WO 99/39218
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`PCT/1899/00172
`
`
`The shift register is accessible from outside the circuit via a Test Data In (TOI) node
`register.
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`
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`and a Test Data Out (TOO) node. A Test Clock signal (TCK) and a Test Mode Select
`signal
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`(TMS) are provided from outside the circuit to the test control unit for stepping through the
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`various �tates. In the normal mode of the known circuit, the 1/0 nodes are logically connected
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`
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`In the test to perfonn its nonnal mode function. allowing the circuit 5 to the main unit, thereby
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`
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`mode of the known circuit, the 1/0 nodes are logically connected to the test unit, thereby
`nnects.
`
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`giving the test unit access to the interco
`is equipped Provided that also the further circuit with a test unit in accordance
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`with the boundary-scan test standard, the interconnects between the two circuits can be tested
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`is first method. Hereto, appropriate test data 10 according to the standard boundary-scan test
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`shifted into the shift registers of the two circuits and is subsequently applied to the
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`interconnects. Then, response data originating from the interconnects is captured into the shift
`registers
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`for observation. From the response and subsequently shifted out of the shift registers
`
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`
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`data it can be determined whether the circuits are properly interconnected. For a single
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`
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`end it is is applied and at the other 15 interconnect this means that to one of its ends a signal
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`
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`observed whether that signal is transmitted. In this way, an open circuit in an interconnect can
`
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`be found. Additionally, a nwnber oftest patterns will be applied to the interconnects in order
`
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`to check for short-circuits between neighbouring interconnects, or between an interconnect
`
`
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`
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`and a power supply line. Essentially, interconnect testing comes down to applying test data to
`20 one end of an interconnec
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`data at another end, in such a way that open
`
`t and observing response
`
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`circuits and short circuits are detected.
`A problem with the boundary-scan approach is that for some circuits pin count
`
`
`
`
`
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`of extra pins to a circuit and pin compatibility considerations inhibit the addition
`
`design for the
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`TCK, TMS, TOI, TOO and the optional TRSTN signals.
`
`Moreover, the price-pressure
`in some
`25 semiconductor
`
`
`
`fields is such that it is considered to be too expensive to reserve area for
`
`
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`interconnect test of the size as required by boundary-scan circuitry.
`
`It is an object of the invention to provide a circuit as specified in the preamble,
`
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`
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`that allows interconnect testing with reduced overhead in terms of required 1/0 nodes and/or
`30 area.
`
`
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`in an electronic circuit, This object is achieved according to the invention
`
`
`which is
`characterised
`
`
`in that in the test mode the test unit is operable as a l�w complexity memory via
`the 1/0 nodes.
`
`
`
`Low complexity memories are those memories that do not have to be put
`through a complex
`
`
`
`
`initialisation process before they can be accessed, and that have simple
`
`
`
`
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`
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`access protocols without dynamic restrictions. Such a test unit enables an alternative procedure
`
`IPR2021-01488
`Apple EX1005 Page 4
`
`

`

`WO 99/39218
`
`3
`
`PCT/1899/00172
`
`
`
`for applying test data to one end of an interconnect and observing response data at the other
`memory has a read-only character
`
`and holds pre-stored test data.at
`
`end. If the low complexity
`
`
`
`a nwnber of addresses, the test unit produces this pre-stored test data at its side of the
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`
`
`
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`interconnects when address data and appropriate control data are applied to it by the further
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`
`
`
`
`
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`via the interconnects. The further circuit then receives response data, which should be
`. 5 circuit
`
`
`
`
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`·identical to the pre-stored test data. In this way, both the interconnects that are used to carry
`
`the address and control
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`datadata and the interconnects that are used to carry the pre-stored
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`
`
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`
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`itself are tested. It is important that particular input data for the test unit, i.e. the address, result
`
`
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`
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`in output data from the test unit that are known a priori, i.e. the stored data. If the low
`
`
`
`
`y memory allows both read and write access, the further circuit can apply test data to
`10 complexit
`
`
`
`the test data in the in a write mode of the test unit, thereby storing
`its side of the interconnects
`
`test unit. In a subsequent
`
`
`read mode of the test unit, the further circuit can read back response
`data.
`behaviour, it does not need the test unit has a read-only or a read/write
`
`
`
`Whether
`
`
`
`
`
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`15 a state machine like the boundary,scan state machine and can therefore be implemented
`
`
`
`
`
`consuming less area. Moreover, the simple operation of the test unit allows less pins or even
`no pins at all to be reserved
`the test unit in the test mode. For both a read-only
`for controlling
`
`
`
`
`
`ng the·and a read/write test unit, a subset of the interconnects is used as a data bus for exchangi
`
`
`storage data. At least
`
`
`unit has a read/write behaviour, a further subset
`
`in the cll;Se that the test
`
`
`
`
`
`
`
`20 of the interconnects is used as a control bus, including, for example, control lines for
`
`
`
`
`
`. controlling the read and/or write process. At least in the case that the test unit has a read-only
`
`behaviour, a still
`
`
`
`
`
`further subset of the interconnects is used as an address bus for selecting the
`storage
`
`
`
`
`location to read from. An important aspect of the invention is that one is free how to
`
`
`bus on the interconnects map the data bus, the control bus and/or the address
`
`to be tested.
`25
`
`
`
`Access to the control bus, the address bus, and the data bus during test mode
`
`
`
`
`
`could be provided, for example, via boundary-scan circuitry of the further circuit. Then, with
`
`
`
`
`
`
`
`·ordinary boundary-scan test equipment, data can be shifted in and out of the further circuit. In
`
`
`
`
`this way, data to be supplied to the control bus and/or the address bus and data returned by the
`test unit on the data bus can be handled.
`
`
`As a further example, if the further circuit is a
`30 programmed microprocessor
`
`IC (ASIC), the further circuit
`or Application-Specific
`could
`
`
`perform the interconnect test in a stand alone fashion, without the n_eed for external
`equipment
`
`
`
`
`
`
`for feeding the further circuit with the test data and for evaluating the response data. It is noted
`that the further
`
`circuit alternatively could consist of two or more separate circuits,
`
`
`together
`
`
`operating the test unit as a low complexity memory.
`
`IPR2021-01488
`Apple EX1005 Page 5
`
`

`

`WO 99/39218
`
`4
`PCT /1899/00 J 72
`
`
`
`
`
`An embodiment of the electronic circuit according to the invention is defined in
`
`
`
`
`
`Claim 2. A Read-Only Memory (ROM) is a_suitable device for holding the data required by
`
`
`
`
`
`
`the interconnect test. When control data, in the form of an address and, if necessary, a limited
`
`
`
`
`
`
`number of further control signals, is applied to the circuit, the ROM outputs data pre-stored at
`5 that address on the data bus. It will be clear
`that in this way both the data bus, the address bus
`
`
`pre-stored bus are tested. A small number oftest patterns
`
`
`and, if present, the control
`in the
`
`
`
`
`
`
`.ROM would normally suffice for an interconnect test capable of detecting open circuits in
`interconnects
`
`
`
`and short circuits between interconnects. It will further be clear that for the test
`
`
`
`
`unit being operable as a low complexity memory, it is not required that the test unit is
`10 implemented
`
`
`
`as a real ROM table. Especially if only a small number oftest patterns is used,
`
`
`
`
`
`the test unit could be implemented as a combinatorial circuit, leading to mo.re efficient area
`usage.
`An embodiment of the electronic circuit according to the invention is defined in
`
`
`
`
`
`
`
`Claim 3. In relation
`
`
`with such a read/write register, the control bus at least controls whether
`15 the register
`
`is in a read mode or in a write mode, and the data bus is used for both supplying
`
`to the test unit and for receiving the data to be read back from the test
`the data to be written
`
`
`
`
`register is used. since only a single no address bus is needed
`
`unit. In this embodiment,
`
`
`
`
`
`in is defined An embodiment of the electronic according to the invention circuit
`
`
`
`
`
`
`area of the substrate requires comparatively little Claim 5. The test circuit of this embodiment
`20 on which it is manufactured.
`
`
`
`
`Furthermore, it enables to test the interconnects in a single type
`
`of test and with a very good test coverage,
`
`
`i.e. a small set of patterns suffices to detect the
`possible
`nects. Furthermore,
`
`
`the diagnostic resolution of the test is very
`
`defects in the intercon
`
`
`good since almost all faults have a unique signature.
`
`
`
`High complexity memory devices are those devices which have complex
`25 protocols
`
`memory array. Therefore, as opposed
`
`for reading from and wri ting into their
`to low
`complexity
`
`
`
`memories are not suited as test units for interconnect
`memories, high complexity
`
`
`
`
`
`testing, as the process of exchanging data is too complex and therefore takes too much time.
`
`
`Examples of high complexity memory devices are Synchronous
`Dynamic Random Access
`
`
`
`
`memories (SDRAMs) and non-volatile memory like flash memory devices. Besides complex
`30 access
`protocols,
`
`
`
`high complexity memories often need initialisation and have dynamic
`
`
`
`
`
`
`
`
`restrictions. The initialisation is troublesome for testing because (al�ost) all control lines and
`
`address lines
`
`
`to succeed in initialisation. Although
`have to be connected correctly
`
`interconnect
`
`
`
`
`
`
`
`
`problems with control and address lines can be detected because the failing initialisation will
`
`IPR2021-01488
`Apple EX1005 Page 6
`
`

`

`WO 99/39218
`
`PCT/1899/00172
`s
`of the pins is not i.e. exactly which of the failure, the diagnosis block all access to the devices,
`
`
`
`
`
`
`connected correctly has a very low resolution.
`
`The dynamic restrictions of SDRAM s, usually
`
`identified by the refresh time
`
`
`
`
`
`and the maximum RAS pulse width, hamper interconnect test because the test patterns (i.e.
`5 writing into and reading
`
`
`from the memory array) have tp meet the dynamic requirements. The
`
`
`
`
`speed of application of test patterns using a boundary-scan circuit is determined by the length
`
`
`of the boundary-scan register and the maximum test clock frequency. The test clock frequency
`
`
`
`
`is determined either by the circuit implementation of the boundary-scan circuit in the I Cs on
`
`the board or by the maximum speed of the boundary-scan tester,
`For these reasons, high complexity memories form a class of circuits that could
`
`
`
`10
`
`
`efficient interconnect very well benefit from adding a low complexity memory for enabling
`
`
`
`
`testing. This is especially true because boundary-scan is hardly available in memory devices
`due to pin count and/or pin compatibility considerations.
`An embodiment of the circuit according to the invention is described in Claim
`
`
`
`
`
`
`
`
`15 6. This particular way of activating the test mode is possible because
`in most SD RAMs the
`
`
`
`first action to be performed after power up is prescribed to be a write action. Thus at power up,
`
`
`
`by utilising the read action for activating the test mode, the nonnal operation of the SD RAM is
`
`
`
`
`
`not effected. As an alternative, the circuit in accordance with the invention can be brought into
`
`
`
`test mode via a particular combination of input signals on the 1/0 nodes, or via a dedicated
`20 node that is dedicated to this function.
`
`Non-volatile memories like flash memory devices hamper interconnect test,
`
`
`
`
`because writing into the memory array for test purposes is not allowed when the device is
`
`already pre-programmed.
`This test would destroy the functional data. An un-programmed
`
`device can be written into but has to be erased
`
`
`afterwards. Erasure of large memory blocks can
`
`
`
`
`25 take up to several seconds, lengthening considerably the board interconnect test.
`
`
`By including a test unit in accordance with the invention, high complexity
`
`
`
`
`
`·memories, including non-volatile memories, can undergo an efficient interconnect test. One
`
`
`
`
`could use the normal mode data bus, address bus and/or control bus for the test mode as well.
`
`
`To also test interconnects that provide signals that are specific for the high complexity
`
`
`
`30 memory functionality, and therefore are not needed to control the test unit in the test mode,
`
`
`
`
`either the data bus or the address bus can be extended with these i�terconnects. The invention
`enables
`
`which take only milliseconds to execute
`interconnect
`and for
`
`testing using test patterns
`
`
`which test pattern generators are commercially available.
`
`IPR2021-01488
`Apple EX1005 Page 7
`
`

`

`6
`
`WO99/39218
`PCT/1B99/00172
`
`
`
`Low complexity memory· types like Static Random Access Memories (SRAMs)
`
`
`
`
`and (Programmable) ROMs can readily be tested for their connectivity using neighbouring
`
`
`microprocessocircuhs equipped with boundary-scan or neighbouring
`rs and/or ASICs. For
`
`
`interconnect
`
`
`memories no extra measures in the fonn of added
`tes�g of such low complexity
`5 test units have to be taken.
`It is a further object of the invention to provide a method as specified in the
`
`
`
`
`
`
`
`
`
`preamble, which perfonn·s the interconnect test with reduced overhead in tenns of required 1/0
`
`
`
`
`
`nodes and/or area. This object is achieved according to the invention in a method, which is
`characterised
`
`
`
`
`in that the putting step comprises operating the first electronic circuit as a low
`
`
`10 complexity memory by the second electronic circuit.
`Although the invention is presented in the context of boundary-scan testing,
`
`
`
`
`
`
`
`
`which mainly applies to testing interconnects between !Cs on a carrier, such as a printed
`
`
`
`
`
`to the testing are equally applicable circuit board (PCB), the principles of the invention
`of
`interconnects
`
`
`
`such as interconnects between cores within a single IC
`
`between any two circuits,
`15 or interconnects
`
`
`into a cabinet. between ICs on distinct PCBs that are inserted
`
`
`The invention and its attendant advantages will be further elucidated with the
`
`
`
`
`
`aid of exemplary
`
`
`schematic drawings, whereby: embodiments and the accompanying
`
`20
`
`25
`
`Figure 3 shows a further way to provide access during interconnect test to a
`
`Figure I shows an embodiment of a circuit in accordance with the invention,
`
`
`access during interconnect
`Figure 2 shows a way to provide
`
`test to a circuit that
`
`
`is testable in accordance with the invention,
`
`
`circuit that is testable in accordance with the invention,
`
`
`
`
`Figure 4 shows an alternative embodiment of the invention,
`
`Figure 5 schematically shows the test unit for five inputs and two outputs,
`and
`
`
`
`for the test unit for five inputs and Figure 6 schematically shows an alternative
`two outputs.
`
`
`
`30 reference symbols.
`
`
`
`
`
`Corresponding features in the various Figures are denoted by the same
`
`with the Figure 1 shows an embodiment of a circuit 100 in accordance
`
`
`
`
`
`
`
`invention. The circuit 100 has 1/0 nodes 130, 140, through which the circuit 100 is
`
`
`
`connectable to external circuits. An I/O node may be an input node, i.e. a node only suitable to
`
`IPR2021-01488
`Apple EX1005 Page 8
`
`

`

`WO 99/39218
`
`7
`
`PCT/1B99/00172
`
`or a bi-directionan output node, i.e. a node only suitable to send signals,
`
`al
`
`receive signals,
`
`
`
`to either receive or send signals. For perfonning its intended
`node, i.e. a node suitable
`nonnal
`100 has a main unit 110, which is, by way of example,
`
`mode function, the circuit
`assumed to
`be an SDRAM. Thus, the circuit
`
`
`
`100 is in fact an SDRAM device. It is further assumed that
`
`
`between the circuit 5 the circuit 100 is part of an assembly, whereas interconnects
`
`100 and
`
`further-parts of the assembly
`
`
`the circuit 100 has a test unit 120,
`
`should be testable. Hereto,
`
`
`
`
`130. In and to the I/0 nodes connections which is connected to the main unit 110 via n parallel
`
`
`
`and signals can pass freely a nonnal mode of the circuit 100, the test unit 120 is transparent,
`
`between the 1/0 nodes 130 and the main unit 110. In a test mode of the circuit 100, the main
`
`
`disconnected from the 1/0 nodes 130 and the test unit 120 is in control. It
`10 unit 110 is logically
`
`
`
`
`is noted that preferably, but not necessarily, all 1/0 nodes are arranged for interconnect testing.
`
`
`
`To indicate this, the 1/0 nodes 140 are not connected to the test unit 120, and therefore, the test
`
`
`
`unit 120 does not offer testability for interconnects corresponding to these 1/0 nodes 140.
`
`
`
`SDRAM devices have a highly standardised pin lay-out. Figure 1 does not give·
`
`
`
`are shows which 1/0 nodes of such a pin-layout, but it schematically
`IS· an exact representation
`
`generally
`
`100 has a data bus D0-D3, an address bus
`
`
`present on an SD RAM device. The circuit
`
`
`AO-All, and a control bus including a Chip Select pin (CSn), an Output Enable pin (OEn),
`
`Strobe pin Write Enable pin (WEn), Clock pin (CLK), Clock Enable pin (CKE), Row Address
`
`
`
`(RAS), Column Address Strobe pin (CAS), and Data 1/0 Mask pins (DQML and DQMH).
`
`
`
`However, the 20 The precise functions of these pins are not relevant for the invention.
`
`
`
`
`
`
`
`
`
`standardised pin lay�out obstructs the addition of boundary-scan circuitry because of the
`
`
`
`
`required extra pins. Another reason for not using boundary-scan for interconnect testing of
`devices
`
`
`
`
`
`like circuit 100 is the enormous pressure on cost. As a result, the IC area available for
`
`
`
`
`
`
`
`extra features like interconnect testing is very limited. In accordance with the invention, as an
`
`
`
`
`
`25 alternative to an ordinary boundary-scan test unit, the test unit 120 is operable as a low
`
`
`
`complexity memory. Such a test unit can be implemented very efficiently in terms of IC area
`and requires
`less or even zero extra pins.
`A low complexity memory can have a read-only behaviour or a read/write
`
`
`
`
`behaviour.
`
`
`kind of behaviour, In accordance with the invention, a test unit has either
`
`or both
`
`
`
`
`30 kinds of behaviour in subsequent phases of an interconnect test. In the circuit 100, during a
`
`
`
`first part of a preferred interconnect test, the test unit 120 has a read�only behaviour
`and during
`
`
`
`a subsequent second part of the interconnect test, the test unit 120 has a read/write behaviour.
`
`
`
`
`
`
`
`This two-step approach enables a thorough interconnect test that is especially suited for
`
`IPR2021-01488
`Apple EX1005 Page 9
`
`

`

`. 1/ •
`
`8
`WO 99/39218
`PCT/1B99/00172
`SDRAM� like the circuit
`
`
`100. The first part of the interconnect test aims at testing the address
`
`
`
`bus of the circuit 100 and is functionally described by:
`
`After power up of the circuit I 00, a test mode is active which allows read
`
`
`
`1.
`
`Alternatively,to the test unit 120. The test unit 120 is then operable as a ROM table.
`
`5 access
`the test mode is activated
`
`
`such as a particular combination or sequence
`of
`by other means,
`
`applied to the 1/0 nodes 130, 140 of the circuit
`signals
`100.
`
`Read access to the test unit
`
`120 is controlled by CSn=O, OEn=0 and WEn=l,
`2.
`
`
`
`CKE.level of the clock enable and validated by a defined edge of the CLK and active
`
`
`The test unit's ROM table is addressed by the 'extended' address bus which is
`10 3.
`
`
`
`
`
`defined as the actual address bus, extended with the control signals RAS, CAS, DQML and
`DQMU.
`
`The width of the ROM table is equal to the width of the data bus plus possible
`4.
`
`
`additional outputs of the circuit
`100.
`15 5.
`Each of the primary addresses (all but one address bits equal to '0', one ad.dress
`
`
`
`
`bit equal to 'l ') reads the all 'l' data word. All other extended addresses read the all '0' data
`word.
`
`The table below shows the contents of the ROM table for the SDRAM device
`
`
`
`20 of circuit 100, with 12 bit wide address bus, RAS, CAS, DQML and DQMU and four data
`pins.
`
`IPR2021-01488
`Apple EX1005 Page 10
`
`

`

`WO99/39218
`
`9
`
`PCT /1B99/00172
`
`extended
`address data buf
`
`bus
`
`AAAAAMAAAAARCDD
`
`DODD
`
`119876543210AAQQ 3210
`
`10
`
`SSMM
`
`LH
`
`00000000