`
`US006807505B2
`
`
`(10)Patent No.:US 6,807,505 B2
`(12)United States Patent
`(45)Date of Patent:
`De Jong et al.
`Oct. 19, 2004
`
`(54)CIRCUIT WITH INTERCONNECT TEST
`
`
`UNIT
`
`(75)Inventors: Franciscus G. M. De Jong, Eindhoven
`
`
`
`(NL); Mathias N. M. Muris,
`
`
`Eindhoven (NL); Robertus M. W.
`
`
`Raaijmakers, Eindhoven (NL);
`(56)
`
`
`Guillaume E. A. Lousberg, Eindhoven
`(NL)
`
`(52)U.S. Cl. ........................................ 702/118; 324/500
`
`
`
`
`
`(58)Field of Search ............................. 702/57-59, 108,
`
`
`702/117, 118; 324/500, 512, 527; 326/16,
`
`
`
`106; 714/25, 27, 30, 718, 719, 726, 727,
`733
`
`
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(73)Assignee: Koninklijke Philips Electronics N.V.,
`
`
`
`
`
`
`Eindhoven (NL)
`
`5,103,450 A * 4/1992 Whetsel ...................... 714/724
`
`
`
`
`
`5,416,409 A * 5/1995 Hunter .................... 324/158.1
`
`5,781,559 A * 7/1998 Muris et al. ................ 714/726
`
`( *) Notice: Subject to any disclaimer, the term of this
`
`
`
`
`
`patent is extended or adjusted under 35
`EP
`
`U.S.C. 154(b) by 0 days.
`GB
`
`FOREIGN PATENT DOCUMENTS
`
`0588507a2 * 3/1994 ........... G0lR/31/04
`
`
`
`
`2278689 A * 12/1994 ........... G0lR/31/28
`
`
`
`(21) Appl. No.: 10/621,002
`
`
`
`(22)Filed: Jul. 16, 2003
`
`(65)
`
`
`
`Prior Publication Data
`
`
`
`* cited by examiner
`
`Primary Examiner-Marc S. Hoff
`
`
`
`Assistant Examiner-Craig Steven Miller
`
`
`(57)
`
`ABSTRACT
`
`
`
`
`
`US 2004/0059535 Al Mar. 25, 2004
`
`
`
`
`
`Related U.S. Application Data
`
`An electronic circuit comprises a plurality of input/output
`
`
`
`
`
`
`
`(1/0) nodes for connecting the electronic circuit to a further
`
`
`
`electronic circuit via interconnects. A main unit implements
`
`
`
`a normal mode function of the electronic circuit. A test unit
`( 62)Division of application No. 09/402,154, filed as application
`
`
`
`
`
`No. PCT/IB99/00172 on Jan. 29, 1999, now Pat. No. 6,622,
`
`
`
`
`tests the interconnects. The electronic circuit has a normal
`108.
`
`
`mode in which the 1/0 nodes are logically connected to the
`
`
`main unit and a test mode in which the 1/0 nodes are
`
`
`logically connected to the test unit. In the test mode the test
`
`Feb. 22, 1998 (EP) ............................................ 98200288
`
`
`
`unit is operable as a low complexity memory via the 1/0
`
`May 6, 1998 (EP) ............................................ 98201482
`nodes.
`
`Nov. 30, 1998 (EP) ............................................ 98204042
`
`
`
`
`
`(30) Foreign Application Priority Data
`
`
`
`
`9 Claims, 3 Drawing Sheets
`
`
`(51)Int. Cl.7 ................................................ G0lR 31/28
`
`DO
`
`01
`
`02
`
`03
`
`AO
`
`130 Al
`
`A11
`
`DQMH
`
`DOML
`
`RAS
`
`GAS
`
`110 100
`120
`
`130
`
`140
`
`IPR2021-01488
`Apple EX1001 Page 1
`
`
`
`US 6,807,505 B2
`U.S. Patent
`Oct. 19, 2004
`Sheet 1 of 3
`
`CU<
`
`CKE
`
`CSn 130
`
`WEn
`
`OEn
`
`n
`
`140
`
`DO
`
`01
`
`02
`
`03
`
`AO
`
`130 A1
`
`A11
`
`DQMH
`
`DOML
`
`RAS
`
`CAS
`
`120 110 100
`
`FtG. 1
`
`210
`
`200
`
`220
`
`230
`
`205
`
`240
`
`F-tG. 2
`
`IPR2021-01488
`Apple EX1001 Page 2
`
`
`
`U.S. Patent Oct. 19, 2004 Sheet 2 of 3 US 6,807,505 B2
`
`310 340
`
`300
`
`320
`
`330
`
`305
`
`FtG. 3
`
`210
`
`402
`
`410
`
`Input_ bus (1 :n) 404
`
`
`
`Output_bus (1:m)
`
`Control_bus (1:p) 406
`
`412 408
`
`240
`
`FtG. 4
`
`IPR2021-01488
`Apple EX1001 Page 3
`
`
`
`US 6,807,505 B2
`Sheet 3 of 3
`Oct. 19, 2004
`U.S. Patent
`
`i1
`
`i2
`
`i3
`
`i4
`
`i5
`
`i1
`
`i2
`
`i3
`
`i4
`
`i5
`
`406
`
`o1
`
`504
`
`o2
`
`� 406
`
`602
`
`604
`- )
`
`01
`
`o2
`
`FtG. 6
`
`IPR2021-01488
`Apple EX1001 Page 4
`
`
`
`
`
`US 6,807,505 B2
`
`1
`
`2
`the interconnects. Then, response data originating from the
`
`
`
`CIRCUIT WITH INTERCONNECT TEST
`
`
`
`interconnects is captured into the shift registers and subse
`UNIT
`
`
`
`
`quently shifted out of the shift registers for observation.
`This application is a divisional of Ser. No. 09/402,154
`
`
`
`
`
`
`From the response data it can be determined whether the
`
`
`
`filed Sep. 29, 1999 now U.S. Pat. No. 6,622,108 which is a
`
`
`
`
`5 circuits are properly interconnected. For a single intercon
`
`
`371 of PCT/1B99/00172 filed Jan. 29, 1999.
`
`
`nect this means that to one of its ends a signal is applied and
`
`
`
`
`The invention relates to an electronic circuit comprising:
`
`
`
`at the other end it is observed whether that signal is
`
`
`
`a plurality of input/output (1/0) nodes for connecting the
`
`
`transmitted. In this way, an open circuit in an interconnect
`
`
`
`
`
`electronic circuit to a further electronic circuit via
`
`
`can be found. Additionally, a number of test patterns will be
`
`
`interconnects, a main unit for implementing a normal mode
`
`
`10 applied to the interconnects in order to check for short
`
`
`
`
`function of the electronic circuit, and a test unit for testing
`
`
`
`
`
`circuits between neighbouring interconnects, or between an
`
`
`
`the interconnects, the electronic circuit having a normal
`
`
`
`interconnect and a power supply line. Essentially, intercon
`
`
`
`mode in which the 1/0 nodes are logically connected to the
`
`
`
`nect testing comes down to applying test data to one end of
`
`main unit and a test mode in which the 1/0 nodes are
`
`
`
`
`an interconnect and observing response data at another end,
`
`
`logically connected to the test unit.
`
`15 in such a way that open circuits and short circuits are
`
`
`
`
`The invention further relates to a method of testing
`detected.
`
`
`
`
`interconnects between a first electronic circuit and a second
`A problem with the boundary-scan approach is that for
`
`
`
`
`
`
`
`
`
`
`electronic circuit, the first electronic circuit comprising a
`
`
`
`some circuits pin count and pin compatibility considerations
`
`
`main unit implementing a normal mode function of the first
`
`
`
`inhibit the addition of extra pins to a circuit design for the
`
`
`electronic circuit, and a test unit for testing the
`
`
`20 TCK, TMS, TDI, TD0 and the optional TRSTN signals.
`
`
`interconnects, the method comprising the steps of logically
`
`
`
`Moreover, the price-pressure in some semiconductor fields
`
`
`
`connecting the test unit to the interconnects, and putting test
`
`
`
`is such that it is considered to be too expensive to reserve
`
`
`
`
`data on the interconnects by the second electronic circuit.
`
`
`
`area for interconnect test of the size as required by
`
`
`Such a circuit is known from "Boundary-scan test, a
`boundary-scan circuitry.
`
`practical approach", H. Bleeker, P. van den Eijnden and F. de 25
`
`
`
`
`
`It is an object of the invention to provide a circuit as
`Jong, Kluwer, Boston, 1993, ISBN 0-7923-9296-5, FIGS.
`
`
`
`
`specified in the preamble, that allows interconnect testing
`
`
`1-19, which shows an integrated (IC) in accordance with the
`
`
`
`with reduced overhead in terms of required 1/0 nodes and/or
`
`boundary-scan test standard IEEE Std. 1149.1. The known
`
`
`
`
`area. This object is achieved according to the invention in an
`
`circuit has a main unit or core logic that is responsible for
`
`
`
`
`electronic circuit, which is characterised in that in the test
`providing some arbitrary specified function in a normal
`
`
`
`
`
`
`
`30 mode the test unit is operable as a low complexity memory
`mode of the circuit. The known circuit further has a test unit
`
`
`
`
`
`via the 1/0 nodes. Low complexity memories are those
`
`for in a test mode performing an interconnect test, i.e. a test
`
`
`
`memories that do not have to be put through a complex
`
`whether the circuit is properly connected to a further circuit
`
`
`
`
`
`
`
`
`initialisation process before they can be accessed, and that
`
`via its 1/0 nodes or IC pins. Efficient interconnect test of
`
`
`
`
`
`
`have simple access protocols without dynamic restrictions.
`
`
`
`
`35 Such a test unit enables an alternative procedure for apply
`miniaturised and/or complex circuit assemblies is a neces
`
`
`
`
`
`
`
`ing test data to one end of an interconnect and observing
`
`
`
`
`
`sary part of the production process of such assemblies. The
`
`
`response data at the other end. If the low complexity
`
`
`
`boundary-scan test technique is accepted as standardised
`
`
`
`memory has a read-only character and holds pre-stored test
`
`
`
`
`solution for interconnect test. It is available in most of the
`
`
`
`data at a number of addresses, the test unit produces this
`
`
`
`leading microprocessor families and is supported for
`
`
`
`40 pre-stored test data at its side of the interconnects when
`
`
`
`
`in-house developed application specific ICs through auto
`
`
`
`
`
`address data and appropriate control data are applied to it by
`
`
`mated tools in the IC design process.
`
`
`The test unit of the known boundary-scan circuit includes
`
`
`
`
`the further circuit via the interconnects. The further circuit
`
`a test control unit or Test Access Port controller and a shift
`
`
`
`
`
`then receives response data, which should be identical to the
`register or boundary-scan register along the circuit
`
`
`
`
`
`pre-stored test data. In this way, both the interconnects that
`
`boundary, cells of the shift register being connected to 1/0
`
`
`
`
`
`45 are used to carry the address and control data and the
`
`
`
`nodes corresponding to the interconnects to be tested. The
`
`
`
`interconnects that are used to carry the pre-stored data itself
`
`
`
`test control unit has a state machine controlling states of the
`
`
`
`are tested. It is important that particular input data for the test
`
`
`
`
`shift register, examples of such states being a shift state for
`
`
`
`unit, i.e. the address, result in output data from the test unit
`
`
`
`shifting in/out data into the shift register and a capture state
`
`
`that are known a priori, i.e. the stored data. If the low
`
`
`
`50 complexity memory allows both read and write access, the
`
`
`
`
`for capturing data originating from the interconnects into the
`
`
`
`further circuit can apply test data to its side of the intercon
`shift register. The shift register is accessible from outside the
`
`
`
`nects in a write mode of the test unit, thereby storing the test
`circuit via a Test Data In (TDI) node and a Test Data Out
`
`
`
`
`
`
`data in the test unit. In a subsequent read mode of the test
`(TDO) node. A Test Clock signal (TCK) and a Test Mode
`
`
`
`Select signal (TMS) are provided from outside the circuit to
`
`
`
`
`
`
`
`unit, the further circuit can read back response data.
`
`
`
`
`the test control unit for stepping through the various states.
`
`Whether the test unit has a read-only or a read/write
`55
`
`In the normal mode of the known circuit, the 1/0 nodes are
`
`
`behaviour, it does not need a state machine like the
`
`logically connected to the main unit, thereby allowing the
`
`
`
`
`boundary-scan state machine and can therefore be imple
`
`
`
`circuit to perform its normal mode function. In the test mode
`
`
`
`
`mented consuming less area. Moreover, the simple operation
`
`
`
`of the known circuit, the 1/0 nodes
`
`
`of the test unit allows less pins or are logically connected even no pins at all to be
`
`
`
`
`
`to the test unit, thereby giving the test unit access to the 60 reserved for controlling the test unit in the test mode. For
`
`interconnects.
`
`
`
`
`both a read-only and a read/write test unit, a subset of the
`
`
`
`
`
`
`
`
`Provided that also the further circuit is equipped with a interconnects is used as a data bus for exchanging the
`
`
`
`
`test unit in accordance with the boundary-scan test standard, storage data. At least in the case that the test unit has a
`
`
`
`
`
`
`
`
`
`
`
`the interconnects between the two circuits can be tested read/write behaviour, a further subset of the interconnects is
`
`
`
`
`
`
`
`
`according to the standard boundary-scan test method. 65 used as a control bus, including, for example, control lines
`
`
`
`
`
`
`
`Hereto, appropriate test data is first shifted into the shift for controlling the read and/or write process. At least in the
`
`
`
`
`
`
`
`registers of the two circuits and is subsequently applied to case that the test unit has a read-only behaviour, a still
`
`IPR2021-01488
`Apple EX1001 Page 5
`
`
`
`
`
`US 6,807,505 B2
`
`4
`3
`
`
`further subset of the interconnects is used as an address bus
`
`
`( almost) all control lines and address lines have to be
`
`
`
`
`
`
`for selecting the storage location to read from. An important
`
`
`
`
`connected correctly to succeed in initialisation. Although
`
`
`
`aspect of the invention is that one is free how to map the data
`
`
`
`
`interconnect problems with control and address lines can be
`
`
`
`
`bus, the control bus and/or the address bus on the intercon
`
`
`
`
`detected because the failing initialisation will block all
`nects to be tested.
`
`
`
`
`
`5 access to the devices, the diagnosis of the failure, i.e. exactly
`
`
`Access to the control bus, the address bus, and the data
`
`
`
`which of the pins is not connected correctly has a very low
`
`
`
`bus during test mode could be provided, for example, via
`resolution.
`
`
`
`
`boundary-scan circuitry of the further circuit. Then, with
`The dynamic restrictions of SDRAMs, usually identified
`
`
`
`
`
`
`ordinary boundary-scan test equipment, data can be shifted
`
`by the refresh time and the maximum RAS pulse width,
`
`
`
`
`in and out of the further circuit. In this way, data to be
`
`
`
`10 hamper interconnect test because the test patterns (i.e.
`
`
`
`
`
`supplied to the control bus and/or the address bus and data
`
`
`
`writing into and reading from the memory array) have to
`
`
`
`
`
`returned by the test unit on the data bus can be handled. As
`
`
`meet the dynamic requirements. The speed of application of
`
`
`
`
`
`a further example, if the further circuit is a programmed
`test patterns using a boundary-scan circuit is determined by
`
`
`
`microprocessor or Application-Specific IC (ASIC), the fur
`
`
`
`the length of the boundary-scan register and the maximum
`
`
`
`ther circuit could perform the interconnect test in a stand
`
`
`15 test clock frequency. The test clock frequency is determined
`
`
`
`alone fashion, without the need for external equipment for
`
`
`either by the circuit implementation of the boundary-scan
`
`
`
`
`feeding the further circuit with the test data and for evalu
`
`
`
`circuit in the ICs on the board or by the maximum speed of
`
`ating the response data. It is noted that the further circuit
`the boundary-scan tester.
`
`
`
`alternatively could consist of two or more separate circuits,
`
`
`For these reasons, high complexity memories form a
`
`
`
`
`together operating the test unit as a low complexity memory.
`
`20 class of circuits that could very well benefit from adding a
`
`
`
`An embodiment of the electronic circuit according to the
`
`
`
`low complexity memory for enabling efficient interconnect
`
`invention is defined in claim 2. A Read-Only Memory
`
`
`
`
`testing. This is especially true because boundary-scan is
`
`
`
`
`(ROM) is a suitable device for holding the data required by
`
`
`
`
`hardly available in memory devices due to pin count and/or
`pin compatibility considerations.
`the interconnect test. When control data, in the form of an
`
`
`
`
`
`
`
`An embodiment of the circuit according to the invention
`
`
`
`
`address and, if necessary, a limited number of further control
`25
`
`signals, is applied to the circuit, the ROM outputs data
`
`
`
`
`is described in claim 6. This particular way of activating the
`
`
`
`test mode is possible because in most SDRAMs the first
`
`
`
`
`pre-stored at that address on the data bus. It will be clear that
`
`
`
`in this way both the data bus, the address
`
`
`
`action to be performed bus and, if present, after power up is prescribed to be a
`
`the control bus are tested. A small
`
`
`write action. number of test patterns Thus at power up, by utilising the read action
`
`
`pre-stored in the ROM would normally suffice for an inter
`
`
`
`
`30 for activating the test mode, the normal operation of the
`
`
`SDRAM is not effected. As an alternative, the circuit in
`
`
`
`
`connect test capable of detecting open circuits in intercon
`
`
`
`accordance with the invention can be brought into test mode
`
`
`
`nects and short circuits between interconnects. It will further
`
`
`
`
`via a particular combination of input signals on the 1/0
`
`
`be clear that for the test unit being operable as a low
`
`
`
`
`nodes, or via a dedicated node that is dedicated to this
`
`
`
`
`complexity memory, it is not required that the test unit is
`35 function.
`
`
`
`implemented as a real ROM table. Especially if only a small
`Non-volatile memories like flash memory devices ham
`
`
`
`
`
`number of test patterns is used, the test unit could be
`
`
`
`
`
`per interconnect test, because writing into the memory array
`
`
`
`implemented as a combinatorial circuit, leading to more
`
`
`
`
`for test purposes is not allowed when the device is already
`
`efficient area usage.
`
`
`
`pre-programmed. This test would destroy the functional
`
`
`
`An embodiment of the electronic circuit according to the
`
`
`
`data. An un-programmed device can be written into but has
`
`
`
`invention is defined in claim 3. In relation with such a 40
`
`
`
`
`to be erased afterwards. Erasure of large memory blocks can
`
`
`
`
`read/write register, the control bus at least controls whether
`
`
`take up to several seconds, lengthening considerably the
`
`
`
`the register is in a read mode or in a write mode, and the data
`board interconnect test.
`
`
`
`
`bus is used for both supplying the data to be written to the
`
`
`
`By including a test unit in accordance with the invention,
`
`
`
`test unit and for receiving the data to be read back from the
`
`
`
`high complexity memories, including non-volatile
`
`
`
`
`test unit. In this embodiment, no address bus is needed since 45
`
`
`
`
`memories, can undergo an efficient interconnect test. One
`
`only a single register is used.
`
`
`could use the normal mode data bus, address bus and/or
`
`
`
`
`
`An embodiment of the electronic circuit according to the
`
`
`control bus for the test mode as well. To also test intercon
`
`invention is defined in claim 5. The test circuit of this
`
`
`
`
`
`
`nects that provide signals that are specific for the high
`
`embodiment requires comparatively little area of the sub
`
`
`
`
`
`strate on which it is manufactured. Furthermore, it enables
`
`
`
`
`
`
`50 complexity memory functionality, and therefore are not
`
`
`to test the interconnects in a single type of test and with a
`
`
`needed to control the test unit in the test mode, either the
`
`
`very good test coverage, i.e. a small set of patterns suffices
`
`
`
`data bus or the address bus can be extended with these
`
`
`to detect the possible defects in the interconnects.
`
`
`
`
`interconnects. The invention enables interconnect testing
`
`
`Furthermore, the diagnostic resolution of the test is very
`
`
`using test patterns which take only milliseconds to execute
`
`
`good since almost all faults have a unique signature.
`
`
`
`55 and for which test pattern generators are commercially
`
`
`
`High complexity memory devices available. are those devices
`
`
`which have complex protocols for reading from and writing
`Low complexity memory types like Static Random
`
`
`
`
`
`
`into their memory array. Therefore, as opposed to low
`
`
`Access Memories (SRAMs) and (Programmable) ROMs
`
`
`
`
`complexity memories, high complexity memories are not
`
`
`
`can readily be tested for their connectivity using neighbour
`
`
`
`suited as test units for interconnect testing, as the process of
`
`
`ing circuits equipped with boundary-scan or neighbouring
`60
`
`
`
`
`exchanging data is too complex and therefore takes too
`
`
`
`
`microprocessors and/or ASICs. For interconnect testing of
`
`
`
`much time. Examples of high complexity memory devices
`
`
`
`such low complexity memories no extra measures in the
`
`
`are Synchronous Dynamic Random Access memories
`
`form of added test units have to be taken.
`
`
`(SDRAMs) and non-volatile memory like flash memory
`
`
`
`
`It is a further object of the invention to provide a method
`
`
`
`
`
`devices. Besides complex access protocols, high complexity
`
`
`
`
`as specified in the preamble, which performs the intercon
`65
`
`
`
`memories often need initialisation and have dynamic restric
`
`
`
`nect test with reduced overhead in terms of required 1/0
`
`
`
`
`tions. The initialisation is troublesome for testing because
`
`
`
`
`nodes and/or area. This object is achieved according to the
`
`IPR2021-01488
`Apple EX1001 Page 6
`
`
`
`US 6,807,505 B2
`
`FIG. 4 shows an alternative embodiment of the
`
`6
`5
`invention in a method, which is characterised in that the because of the required extra pins. Another reason for not
`
`
`
`
`
`
`
`
`
`
`
`
`using boundary-scan for interconnect testing of devices like
`
`
`
`
`
`
`putting step comprises operating the first electronic circuit as
`
`
`
`
`circuit 100 is the enormous pressure on cost. As a result, the
`
`
`
`a low complexity memory by the second electronic circuit.
`
`
`
`
`IC area available for extra features like interconnect testing
`
`
`
`
`Although the invention is presented in the context of
`
`
`
`as an 5 is very limited. In accordance with the invention,
`boundary-scan testing, which mainly applies to testing inter
`
`
`
`
`
`
`
`
`alternative to an ordinary boundary-scan test unit, the test
`
`
`connects between I Cs on a carrier, such as a printed circuit
`
`
`
`unit 120 is operable as a low complexity memory. Such a test
`
`
`board (PCB), the principles of the invention are equally
`
`
`
`unit can be implemented very efficiently in terms of IC area
`
`
`
`
`applicable to the testing of interconnects between any two
`
`
`and requires less or even zero extra pins.
`
`
`
`
`circuits, such as interconnects between cores within a single
`
`
`A low complexity memory can have a read-only behav-
`
`
`
`IC or interconnects between ICs on distinct PCBs that are
`10
`
`
`
`iour or a read/write behaviour. In accordance with the
`
`inserted into a cabinet.
`
`
`
`invention, a test unit has either kind of behaviour, or both
`
`
`
`The invention and its attendant advantages will be further
`
`
`
`kinds of behaviour in subsequent phases of an interconnect
`
`elucidated with the aid of exemplary embodiments and the
`
`
`
`
`
`
`test. In the circuit 100, during a first part of a preferred
`
`
`
`accompanying schematic drawings, whereby:
`
`
`
`interconnect test, the test unit 120 has a read-only behaviour
`FIG. 1 shows an embodiment of a circuit in accordance
`
`
`
`
`
`
`
`15 and during a subsequent second part of the interconnect test,
`
`with the invention,
`
`
`the test unit 120 has a read/write behaviour. This two-step
`
`
`
`
`FIG. 2 shows a way to provide access during intercon
`
`
`
`
`approach enables a thorough interconnect test that is espe
`
`
`
`nect test to a circuit that is testable in accordance with the
`
`
`
`
`
`cially suited for SDRAMs like the circuit 100. The first part
`invention,
`
`
`
`
`of the interconnect test aims at testing the address bus of the
`
`
`
`
`
`
`described by: circuit 100 and is functionally FIG. 3 shows a further way to provide access during
`20
`
`
`1.After power up of the circuit 100, a test mode is active
`
`
`
`interconnect test to a circuit that is testable in accordance
`
`
`
`which allows read access to the test unit 120. The test unit
`
`with the invention,
`
`
`
`120 is then operable as a ROM table. Alternatively, the
`
`
`
`
`
`test mode is activated by other means, such as a particular
`invention,
`
`
`
`combination or sequence of signals applied to the 1/0
`FIG. 5
`
`schematically shows the test unit for five inputs
`25
`
`nodes 130, 140 of the circuit 100.
`
`and two outputs, and
`2.Read access to the test unit 120 is controlled by CSn=0,
`
`
`FIG. 6
`
`
`schematically shows an alternative for the test unit
`
`OEn=0 and WEn=l, and validated by a defined edge of
`
`for five inputs and two outputs.
`
`
`
`the CLK and active level of the clock enable CKE.
`Corresponding features in the various Figures are
`
`
`
`
`
`
`
`3.The test unit's ROM table is addressed by the 'extended'
`
`
`
`denoted by the same reference symbols.
`30
`
`
`
`address bus which is defined as the actual address bus,
`
`
`FIG. 1 shows an embodiment of a circuit 100 in accor
`
`
`
`
`
`extended with the control signals RAS, CAS, DQML and
`dance with the invention. The circuit 100 has 1/0 nodes 130,
`
`
`
`DQMU.
`140, through which the circuit 100 is connectable to external
`
`
`
`4.The width of the ROM table is equal to the width of the
`
`
`
`
`
`circuits. An 1/0 node may be an input node, i.e. a node only
`
`
`
`
`data bus plus possible additional outputs of the circuit
`
`
`
`
`suitable to receive signals, an output node, i.e. a node only 35
`100.
`
`
`
`
`suitable to send signals, or a bi-directional node, i.e. a node
`5.Each of the primary addresses (all but one address bits
`
`
`
`
`
`
`
`
`
`
`
`suitable to either receive or send signals. For performing its
`
`
`equal to '0', one address bit equal to '2') reads the all '1'
`
`
`
`intended normal mode function, the circuit 100 has a main
`
`
`data word. All other extended addresses read the all '0'
`
`
`unit 110, which is, by way of example, assumed to be an
`data word.
`
`
`SDRAM. Thus, the circuit 100 is in fact an SDRAM device.
`40
`The table below shows the contents of the ROM table for
`
`
`
`
`
`
`It is further assumed that the circuit 100 is part of an
`
`
`
`
`the SDRAM device of circuit 100, with 12 bit wide address
`
`
`
`
`assembly, whereas interconnects between the circuit 100 and
`
`
`bus, RAS, CAS, DQML and DQMU and four data pins.
`
`
`
`further parts of the assembly should be testable. Hereto, the
`
`
`circuit 100 has a test unit 120, which is connected to the
`
`
`
`main unit 110 via n parallel connections and to the 1/0 nodes 45
`extended address
`
`
`
`130.In a normal mode of the circuit 100, the test unit 120
`bus
`
`
`
`is transparent, and signals can pass freely between the 1/0
`AAAAAAAAAAAARCDD
`119876543210AAQQ data bus
`
`
`nodes 130 and the main unit 110. In a test mode of the circuit
`10
`SSMM
`
`
`100, the main unit 110 is logically disconnected from the 1/0
`LH
`
`
`
`nodes 130 and the test unit 120 is in control. It is noted that 50
`0000000000000001 1111
`
`
`
`
`preferably, but not necessarily, all 1/O nodes are arranged for
`0000000000000010 1111
`
`
`
`interconnect testing. To indicate this, the 1/0 nodes 140 are
`0000000000000100 1111
`
`
`
`not connected to the test unit 120, and therefore, the test unit
`0000000000001000 1111
`
`
`120 does not offer testability for interconnects correspond-
`0000000000010000 1111
`0000000000100000 1111
`ing to these 1/0 nodes 140.
`55
`0000000001000000 1111
`
`
`SDRAM devices have a highly standardised pin lay-out.
`0000000010000000 1111
`
`FIG. 1 does not give an exact representation of such a
`0000000100000000 1111
`
`
`
`pin-layout, but it schematically shows which 1/0 nodes are
`0000001000000000 1111
`0000010000000000 1111
`
`
`
`
`
`generally present on an SD RAM device. The circuit 100 has
`0000100000000000 1111
`
`
`
`a data bus D0-D3, an address bus AO-All, and a control bus 60
`0001000000000000 1111
`
`
`
`including a Chip Select pin (CSn), an Output Enable pin
`0010000000000000 1111
`(OEn), Write Enable pin (WEn), Clock pin (CLK), Clock
`0100000000000000 1111
`1000000000000000 1111
`
`
`
`Enable pin (CKE), Row Address Strobe pin (RAS), Column
`
`'any other address'
`0000
`
`
`Address Strobe pin (CAS), and Data 1/0 Mask pins (DQML
`
`
`
`and DQMH). The precise functions of these pins are not 65
`relevant for the invention. However, the standardised pin With the above described functional behaviour of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`lay-out obstructs the addition of boundary-scan circuitry circuit 100 after power up, an efficient test for the extended
`
`DODD
`3210
`
`IPR2021-01488
`Apple EX1001 Page 7
`
`
`
`US 6,807,505 B2
`
`DDDDDDDDDDDDDDDD
`
`1111119876543210
`
`543210
`
`8
`7
`As mentioned above, the mechanism for switching the
`
`
`
`address bits consist of just reading all primary addresses (16
`
`
`
`
`
`
`circuit from the normal mode into the test mode may be
`
`
`in the above case) and one other address. The test sequence
`
`
`implemented in different ways. In the SD RAM embodiment,
`
`
`covers the following faults:
`
`
`
`the circuit is brought into the test mode by performing a read
`1.any stuck-at 1 on an extended address pin
`
`
`
`
`
`
`5 action after power up. Such a read action after power up, is
`
`
`
`
`2.any stuck-at O on an extended address pin
`
`
`
`a special action which does not form part of the normal
`
`
`3. any 2-net AND-type short between any pair of address
`
`
`
`actions for the circuit and has been given the special
`pins
`
`
`meaning of a command for switching into the test mode. In
`
`
`
`
`
`4. any 2-net OR-type short between any pair of address pins
`
`
`
`general, any pattern or sequence of patterns applied to one
`
`5.any stuck-at 1 on a data pin
`10
`
`
`or more 1/0 nodes of the circuit can be given the special
`
`6.any stuck-at O on a data pin
`
`meaning of a command for going into test mode, provided
`
`
`
`An interconnect with a stuck-at fault remains at either
`
`
`
`
`that this pattern or sequence is not used in the normal mode
`
`logic high or logic low, no matter what signals are applied
`
`
`
`
`of the circuit. An alternative is to provide the circuit with a
`
`
`
`to it. A 2-net AND-type short between a first and a second
`
`
`
`
`the 1/0 nodes, to 15 dedicated test control node, in addition to
`
`
`
`interconnect causes the two interconnects to carry the same
`
`
`
`control whether the circuit is to behave in the normal
`
`
`logic value as determined by either one of the interconnects.
`
`
`operational mode or in the test mode. The actual signal value
`
`
`
`
`A 2-net OR-type short between a first and a second inter
`
`
`
`on the test control node, in relation with predefined values
`
`
`
`connect causes the two interconnects to carry complemen
`
`
`
`
`tary logic values as determined by either one of the inter
`
`
`corresponding to the respective modes, brings the circuit
`connects.
`
`20 into the desired mode.
`
`
`
`The above test sequence provides a diagnostic resolution
`FIG. 2 shows a way to provide access during interconnect
`
`
`
`
`
`
`
`down to a single pin. Note that this test concept is indepen
`
`
`
`test to a circuit 200 that is testable in accordance with the
`
`
`
`
`
`dent from the number of extended address lines or the
`
`
`invention. The circuit 200 includes a test unit 205 that is
`
`
`number of data lines, nor is there any relation assumed
`
`
`operable as a low complexity memory. A neighbouring
`
`between the two numbers.
`
`
`
`25 circuit 210, which has boundary-scan circuitry, can provide
`
`
`
`The second part of the interconnect test aims at testing for
`
`
`
`
`data to and receive data from the circuit 200 via a control and
`
`
`
`shorts between the interconnects making up the data bus,
`
`
`address bus 220 and a bi-directional data bus 230.
`
`and is functionally described by:
`
`
`
`Alternatively, when only a ROM behaviour is implemented
`
`
`
`1. Write access is provided to a command register, which is
`in the test unit 205, the data bus 230 would be unidirectional,
`
`
`loaded with the value of the ( actual) address bus.
`
`
`
`30 i.e. from the circuit 200 to the circuit 210.
`
`
`
`2. There will be a certain combination of address bits, which,
`A number of interconnects make up the control and
`
`
`
`
`
`
`after being loaded into the aforementioned command
`
`
`
`address bus 220 and the data bus 230. The function of these
`
`
`
`
`register, select a single write/read register that logically
`
`
`
`interconnects during a normal mode is irrelevant for the
`
`
`
`forms part of the test unit, with a width equal to the width
`
`invention. When the circuit 200 is a memory device, there
`
`
`
`of the data bus. This combination of address bits is to be 35
`
`
`will also be a 'normal mode data bus'. The 'test mode data
`
`
`
`determined by the manufacturer of the device and to be
`
`
`
`bus' 230 could partly or completely coincide with the normal
`
`specified in the data sheet.
`
`
`mode data bus. The same applies to the control and address
`
`
`
`
`This single write/read register can then be used to write
`bus 220.
`
`
`
`
`data and read data. Algorithms are available to generate a
`Via a boundary-scan chain 240 data is shifted into circuit
`
`
`
`
`
`minimal set of test patterns which cover all AND-type and 40
`
`
`210, that data making up read and/or write commands to be
`
`
`
`
`
`OR-type shorts between any pair of data lines. The table
`
`
`
`supplied to the circuit 200. After a read command, the
`
`
`below shows a set of test patterns for a 16-bit wide data bus.
`
`
`
`boundary-scan chain 240 captures data supplied to the data
`
`
`bus 230 by the circuit 200. That data subsequently are
`
`
`
`shifted out to be analysed externally.
`
`
`FIG. 3 shows a further way to provide access during
`45
`
`
`interconnect test to a circuit 300 that is testable in accor
`
`
`dance with the invention. The circuit 300 includes a test unit
`
`
`305 that is operable as a low complexity memory via control
`
`and address bus 320 and data bus 330. A neighbouring
`
`
`
`50 circuit 310, which is a microprocessor, executes the program
`
`
`with the necessary read and write commands. The test
`
`
`
`program and the test data are stored in a memory 340 of the
`
`
`
`
`circuit 310. Preferably, the circuit 310 also analyses the data
`
`
`
`obtained from the circuit 300. The circuit 310 could alter-
`
`natively be an ASIC.
`
`
`
`For dynamic memory devices, like the circuit 100, the 55
`The above presented design-for-test method does not
`
`
`
`
`above described two parts of the interconnect test have read
`
`
`
`require any additional pins to the device for test access,
`and write access to the test unit which is not affected with
`
`
`
`
`
`meeting pin count and pin compat