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`US006807505B2
`
`
`(10)Patent No.:US 6,807,505 B2
`(12)United States Patent
`(45)Date of Patent:
`De Jong et al.
`Oct. 19, 2004
`
`(54)CIRCUIT WITH INTERCONNECT TEST
`
`
`UNIT
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`(75)Inventors: Franciscus G. M. De Jong, Eindhoven
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`(NL); Mathias N. M. Muris,
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`Eindhoven (NL); Robertus M. W.
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`Raaijmakers, Eindhoven (NL);
`(56)
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`Guillaume E. A. Lousberg, Eindhoven
`(NL)
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`(52)U.S. Cl. ........................................ 702/118; 324/500
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`(58)Field of Search ............................. 702/57-59, 108,
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`702/117, 118; 324/500, 512, 527; 326/16,
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`106; 714/25, 27, 30, 718, 719, 726, 727,
`733
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`References Cited
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`U.S. PATENT DOCUMENTS
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`(73)Assignee: Koninklijke Philips Electronics N.V.,
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`Eindhoven (NL)
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`5,103,450 A * 4/1992 Whetsel ...................... 714/724
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`5,416,409 A * 5/1995 Hunter .................... 324/158.1
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`5,781,559 A * 7/1998 Muris et al. ................ 714/726
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`( *) Notice: Subject to any disclaimer, the term of this
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`
`
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`patent is extended or adjusted under 35
`EP
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`U.S.C. 154(b) by 0 days.
`GB
`
`FOREIGN PATENT DOCUMENTS
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`0588507a2 * 3/1994 ........... G0lR/31/04
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`2278689 A * 12/1994 ........... G0lR/31/28
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`(21) Appl. No.: 10/621,002
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`(22)Filed: Jul. 16, 2003
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`(65)
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`Prior Publication Data
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`* cited by examiner
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`Primary Examiner-Marc S. Hoff
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`Assistant Examiner-Craig Steven Miller
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`(57)
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`ABSTRACT
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`US 2004/0059535 Al Mar. 25, 2004
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`Related U.S. Application Data
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`An electronic circuit comprises a plurality of input/output
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`(1/0) nodes for connecting the electronic circuit to a further
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`electronic circuit via interconnects. A main unit implements
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`a normal mode function of the electronic circuit. A test unit
`( 62)Division of application No. 09/402,154, filed as application
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`No. PCT/IB99/00172 on Jan. 29, 1999, now Pat. No. 6,622,
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`tests the interconnects. The electronic circuit has a normal
`108.
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`mode in which the 1/0 nodes are logically connected to the
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`main unit and a test mode in which the 1/0 nodes are
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`logically connected to the test unit. In the test mode the test
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`Feb. 22, 1998 (EP) ............................................ 98200288
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`unit is operable as a low complexity memory via the 1/0
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`May 6, 1998 (EP) ............................................ 98201482
`nodes.
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`Nov. 30, 1998 (EP) ............................................ 98204042
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`(30) Foreign Application Priority Data
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`9 Claims, 3 Drawing Sheets
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`(51)Int. Cl.7 ................................................ G0lR 31/28
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`DO
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`130 Al
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`DQMH
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`GAS
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`110 100
`120
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`130
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`CU<
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`CSn 130
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`03
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`AO
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`130 A1
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`A11
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`DQMH
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`RAS
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`CAS
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`120 110 100
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`FtG. 1
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`U.S. Patent Oct. 19, 2004 Sheet 2 of 3 US 6,807,505 B2
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`310 340
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`FtG. 3
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`Input_ bus (1 :n) 404
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`Output_bus (1:m)
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`Control_bus (1:p) 406
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`412 408
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`US 6,807,505 B2
`Sheet 3 of 3
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`U.S. Patent
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`US 6,807,505 B2
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`1
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`2
`the interconnects. Then, response data originating from the
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`CIRCUIT WITH INTERCONNECT TEST
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`interconnects is captured into the shift registers and subse­
`UNIT
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`quently shifted out of the shift registers for observation.
`This application is a divisional of Ser. No. 09/402,154
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`From the response data it can be determined whether the
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`filed Sep. 29, 1999 now U.S. Pat. No. 6,622,108 which is a
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`5 circuits are properly interconnected. For a single intercon­
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`371 of PCT/1B99/00172 filed Jan. 29, 1999.
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`nect this means that to one of its ends a signal is applied and
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`The invention relates to an electronic circuit comprising:
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`at the other end it is observed whether that signal is
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`a plurality of input/output (1/0) nodes for connecting the
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`transmitted. In this way, an open circuit in an interconnect
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`electronic circuit to a further electronic circuit via
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`can be found. Additionally, a number of test patterns will be
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`interconnects, a main unit for implementing a normal mode
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`10 applied to the interconnects in order to check for short­
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`function of the electronic circuit, and a test unit for testing
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`circuits between neighbouring interconnects, or between an
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`the interconnects, the electronic circuit having a normal
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`interconnect and a power supply line. Essentially, intercon­
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`mode in which the 1/0 nodes are logically connected to the
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`nect testing comes down to applying test data to one end of
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`main unit and a test mode in which the 1/0 nodes are
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`an interconnect and observing response data at another end,
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`logically connected to the test unit.
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`15 in such a way that open circuits and short circuits are
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`The invention further relates to a method of testing
`detected.
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`interconnects between a first electronic circuit and a second
`A problem with the boundary-scan approach is that for
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`electronic circuit, the first electronic circuit comprising a
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`some circuits pin count and pin compatibility considerations
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`main unit implementing a normal mode function of the first
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`inhibit the addition of extra pins to a circuit design for the
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`electronic circuit, and a test unit for testing the
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`20 TCK, TMS, TDI, TD0 and the optional TRSTN signals.
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`interconnects, the method comprising the steps of logically
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`Moreover, the price-pressure in some semiconductor fields
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`connecting the test unit to the interconnects, and putting test
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`is such that it is considered to be too expensive to reserve
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`data on the interconnects by the second electronic circuit.
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`area for interconnect test of the size as required by
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`Such a circuit is known from "Boundary-scan test, a
`boundary-scan circuitry.
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`practical approach", H. Bleeker, P. van den Eijnden and F. de 25
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`It is an object of the invention to provide a circuit as
`Jong, Kluwer, Boston, 1993, ISBN 0-7923-9296-5, FIGS.
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`specified in the preamble, that allows interconnect testing
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`1-19, which shows an integrated (IC) in accordance with the
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`with reduced overhead in terms of required 1/0 nodes and/or
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`boundary-scan test standard IEEE Std. 1149.1. The known
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`area. This object is achieved according to the invention in an
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`circuit has a main unit or core logic that is responsible for
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`electronic circuit, which is characterised in that in the test
`providing some arbitrary specified function in a normal
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`30 mode the test unit is operable as a low complexity memory
`mode of the circuit. The known circuit further has a test unit
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`via the 1/0 nodes. Low complexity memories are those
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`for in a test mode performing an interconnect test, i.e. a test
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`memories that do not have to be put through a complex
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`whether the circuit is properly connected to a further circuit
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`initialisation process before they can be accessed, and that
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`via its 1/0 nodes or IC pins. Efficient interconnect test of
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`have simple access protocols without dynamic restrictions.
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`35 Such a test unit enables an alternative procedure for apply­
`miniaturised and/or complex circuit assemblies is a neces­
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`ing test data to one end of an interconnect and observing
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`sary part of the production process of such assemblies. The
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`response data at the other end. If the low complexity
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`boundary-scan test technique is accepted as standardised
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`memory has a read-only character and holds pre-stored test
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`solution for interconnect test. It is available in most of the
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`data at a number of addresses, the test unit produces this
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`leading microprocessor families and is supported for
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`40 pre-stored test data at its side of the interconnects when
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`in-house developed application specific ICs through auto­
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`address data and appropriate control data are applied to it by
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`mated tools in the IC design process.
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`The test unit of the known boundary-scan circuit includes
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`the further circuit via the interconnects. The further circuit
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`a test control unit or Test Access Port controller and a shift
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`then receives response data, which should be identical to the
`register or boundary-scan register along the circuit
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`pre-stored test data. In this way, both the interconnects that
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`boundary, cells of the shift register being connected to 1/0
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`45 are used to carry the address and control data and the
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`nodes corresponding to the interconnects to be tested. The
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`interconnects that are used to carry the pre-stored data itself
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`test control unit has a state machine controlling states of the
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`are tested. It is important that particular input data for the test
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`shift register, examples of such states being a shift state for
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`unit, i.e. the address, result in output data from the test unit
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`shifting in/out data into the shift register and a capture state
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`that are known a priori, i.e. the stored data. If the low
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`50 complexity memory allows both read and write access, the
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`for capturing data originating from the interconnects into the
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`further circuit can apply test data to its side of the intercon­
`shift register. The shift register is accessible from outside the
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`nects in a write mode of the test unit, thereby storing the test
`circuit via a Test Data In (TDI) node and a Test Data Out
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`data in the test unit. In a subsequent read mode of the test
`(TDO) node. A Test Clock signal (TCK) and a Test Mode
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`Select signal (TMS) are provided from outside the circuit to
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`unit, the further circuit can read back response data.
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`the test control unit for stepping through the various states.
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`Whether the test unit has a read-only or a read/write
`55
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`In the normal mode of the known circuit, the 1/0 nodes are
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`behaviour, it does not need a state machine like the
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`logically connected to the main unit, thereby allowing the
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`boundary-scan state machine and can therefore be imple­
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`circuit to perform its normal mode function. In the test mode
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`mented consuming less area. Moreover, the simple operation
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`of the known circuit, the 1/0 nodes
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`of the test unit allows less pins or are logically connected even no pins at all to be
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`to the test unit, thereby giving the test unit access to the 60 reserved for controlling the test unit in the test mode. For
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`interconnects.
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`both a read-only and a read/write test unit, a subset of the
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`Provided that also the further circuit is equipped with a interconnects is used as a data bus for exchanging the
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`test unit in accordance with the boundary-scan test standard, storage data. At least in the case that the test unit has a
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`the interconnects between the two circuits can be tested read/write behaviour, a further subset of the interconnects is
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`according to the standard boundary-scan test method. 65 used as a control bus, including, for example, control lines
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`Hereto, appropriate test data is first shifted into the shift for controlling the read and/or write process. At least in the
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`registers of the two circuits and is subsequently applied to case that the test unit has a read-only behaviour, a still
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`4
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`further subset of the interconnects is used as an address bus
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`( almost) all control lines and address lines have to be
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`for selecting the storage location to read from. An important
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`connected correctly to succeed in initialisation. Although
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`aspect of the invention is that one is free how to map the data
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`interconnect problems with control and address lines can be
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`bus, the control bus and/or the address bus on the intercon­
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`detected because the failing initialisation will block all
`nects to be tested.
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`5 access to the devices, the diagnosis of the failure, i.e. exactly
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`Access to the control bus, the address bus, and the data
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`which of the pins is not connected correctly has a very low
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`bus during test mode could be provided, for example, via
`resolution.
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`boundary-scan circuitry of the further circuit. Then, with
`The dynamic restrictions of SDRAMs, usually identified
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`ordinary boundary-scan test equipment, data can be shifted
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`by the refresh time and the maximum RAS pulse width,
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`in and out of the further circuit. In this way, data to be
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`10 hamper interconnect test because the test patterns (i.e.
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`supplied to the control bus and/or the address bus and data
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`writing into and reading from the memory array) have to
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`returned by the test unit on the data bus can be handled. As
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`meet the dynamic requirements. The speed of application of
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`a further example, if the further circuit is a programmed
`test patterns using a boundary-scan circuit is determined by
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`microprocessor or Application-Specific IC (ASIC), the fur­
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`the length of the boundary-scan register and the maximum
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`ther circuit could perform the interconnect test in a stand
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`15 test clock frequency. The test clock frequency is determined
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`alone fashion, without the need for external equipment for
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`either by the circuit implementation of the boundary-scan
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`feeding the further circuit with the test data and for evalu­
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`circuit in the ICs on the board or by the maximum speed of
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`ating the response data. It is noted that the further circuit
`the boundary-scan tester.
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`alternatively could consist of two or more separate circuits,
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`For these reasons, high complexity memories form a
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`together operating the test unit as a low complexity memory.
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`20 class of circuits that could very well benefit from adding a
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`An embodiment of the electronic circuit according to the
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`low complexity memory for enabling efficient interconnect
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`invention is defined in claim 2. A Read-Only Memory
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`testing. This is especially true because boundary-scan is
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`(ROM) is a suitable device for holding the data required by
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`hardly available in memory devices due to pin count and/or
`pin compatibility considerations.
`the interconnect test. When control data, in the form of an
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`An embodiment of the circuit according to the invention
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`address and, if necessary, a limited number of further control
`25
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`signals, is applied to the circuit, the ROM outputs data
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`is described in claim 6. This particular way of activating the
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`test mode is possible because in most SDRAMs the first
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`pre-stored at that address on the data bus. It will be clear that
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`in this way both the data bus, the address
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`action to be performed bus and, if present, after power up is prescribed to be a
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`the control bus are tested. A small
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`write action. number of test patterns Thus at power up, by utilising the read action
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`pre-stored in the ROM would normally suffice for an inter­
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`30 for activating the test mode, the normal operation of the
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`SDRAM is not effected. As an alternative, the circuit in
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`connect test capable of detecting open circuits in intercon­
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`accordance with the invention can be brought into test mode
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`nects and short circuits between interconnects. It will further
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`via a particular combination of input signals on the 1/0
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`be clear that for the test unit being operable as a low
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`nodes, or via a dedicated node that is dedicated to this
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`complexity memory, it is not required that the test unit is
`35 function.
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`implemented as a real ROM table. Especially if only a small
`Non-volatile memories like flash memory devices ham­
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`number of test patterns is used, the test unit could be
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`per interconnect test, because writing into the memory array
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`implemented as a combinatorial circuit, leading to more
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`for test purposes is not allowed when the device is already
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`efficient area usage.
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`pre-programmed. This test would destroy the functional
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`An embodiment of the electronic circuit according to the
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`data. An un-programmed device can be written into but has
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`invention is defined in claim 3. In relation with such a 40
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`to be erased afterwards. Erasure of large memory blocks can
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`read/write register, the control bus at least controls whether
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`take up to several seconds, lengthening considerably the
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`the register is in a read mode or in a write mode, and the data
`board interconnect test.
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`bus is used for both supplying the data to be written to the
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`By including a test unit in accordance with the invention,
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`test unit and for receiving the data to be read back from the
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`high complexity memories, including non-volatile
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`test unit. In this embodiment, no address bus is needed since 45
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`memories, can undergo an efficient interconnect test. One
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`only a single register is used.
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`could use the normal mode data bus, address bus and/or
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`An embodiment of the electronic circuit according to the
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`control bus for the test mode as well. To also test intercon­
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`invention is defined in claim 5. The test circuit of this
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`nects that provide signals that are specific for the high
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`embodiment requires comparatively little area of the sub­
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`strate on which it is manufactured. Furthermore, it enables
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`50 complexity memory functionality, and therefore are not
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`to test the interconnects in a single type of test and with a
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`needed to control the test unit in the test mode, either the
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`very good test coverage, i.e. a small set of patterns suffices
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`data bus or the address bus can be extended with these
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`to detect the possible defects in the interconnects.
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`interconnects. The invention enables interconnect testing
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`Furthermore, the diagnostic resolution of the test is very
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`using test patterns which take only milliseconds to execute
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`good since almost all faults have a unique signature.
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`55 and for which test pattern generators are commercially
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`High complexity memory devices available. are those devices
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`which have complex protocols for reading from and writing
`Low complexity memory types like Static Random
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`into their memory array. Therefore, as opposed to low
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`Access Memories (SRAMs) and (Programmable) ROMs
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`complexity memories, high complexity memories are not
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`can readily be tested for their connectivity using neighbour­
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`suited as test units for interconnect testing, as the process of
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`ing circuits equipped with boundary-scan or neighbouring
`60
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`exchanging data is too complex and therefore takes too
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`microprocessors and/or ASICs. For interconnect testing of
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`much time. Examples of high complexity memory devices
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`such low complexity memories no extra measures in the
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`are Synchronous Dynamic Random Access memories
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`form of added test units have to be taken.
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`(SDRAMs) and non-volatile memory like flash memory
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`It is a further object of the invention to provide a method
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`devices. Besides complex access protocols, high complexity
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`as specified in the preamble, which performs the intercon­
`65
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`memories often need initialisation and have dynamic restric­
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`nect test with reduced overhead in terms of required 1/0
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`tions. The initialisation is troublesome for testing because
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`nodes and/or area. This object is achieved according to the
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`IPR2021-01488
`Apple EX1001 Page 6
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`

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`US 6,807,505 B2
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`FIG. 4 shows an alternative embodiment of the
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`6
`5
`invention in a method, which is characterised in that the because of the required extra pins. Another reason for not
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`using boundary-scan for interconnect testing of devices like
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`putting step comprises operating the first electronic circuit as
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`circuit 100 is the enormous pressure on cost. As a result, the
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`a low complexity memory by the second electronic circuit.
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`IC area available for extra features like interconnect testing
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`Although the invention is presented in the context of
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`as an 5 is very limited. In accordance with the invention,
`boundary-scan testing, which mainly applies to testing inter­
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`alternative to an ordinary boundary-scan test unit, the test
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`connects between I Cs on a carrier, such as a printed circuit
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`unit 120 is operable as a low complexity memory. Such a test
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`board (PCB), the principles of the invention are equally
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`unit can be implemented very efficiently in terms of IC area
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`applicable to the testing of interconnects between any two
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`and requires less or even zero extra pins.
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`circuits, such as interconnects between cores within a single
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`A low complexity memory can have a read-only behav-
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`IC or interconnects between ICs on distinct PCBs that are
`10
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`iour or a read/write behaviour. In accordance with the
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`inserted into a cabinet.
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`invention, a test unit has either kind of behaviour, or both
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`The invention and its attendant advantages will be further
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`kinds of behaviour in subsequent phases of an interconnect
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`elucidated with the aid of exemplary embodiments and the
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`test. In the circuit 100, during a first part of a preferred
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`accompanying schematic drawings, whereby:
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`interconnect test, the test unit 120 has a read-only behaviour
`FIG. 1 shows an embodiment of a circuit in accordance
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`15 and during a subsequent second part of the interconnect test,
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`with the invention,
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`the test unit 120 has a read/write behaviour. This two-step
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`FIG. 2 shows a way to provide access during intercon­
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`approach enables a thorough interconnect test that is espe­
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`nect test to a circuit that is testable in accordance with the
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`cially suited for SDRAMs like the circuit 100. The first part
`invention,
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`of the interconnect test aims at testing the address bus of the
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`described by: circuit 100 and is functionally FIG. 3 shows a further way to provide access during
`20
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`1.After power up of the circuit 100, a test mode is active
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`interconnect test to a circuit that is testable in accordance
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`which allows read access to the test unit 120. The test unit
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`with the invention,
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`120 is then operable as a ROM table. Alternatively, the
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`test mode is activated by other means, such as a particular
`invention,
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`combination or sequence of signals applied to the 1/0
`FIG. 5
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`schematically shows the test unit for five inputs
`25
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`nodes 130, 140 of the circuit 100.
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`and two outputs, and
`2.Read access to the test unit 120 is controlled by CSn=0,
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`FIG. 6
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`schematically shows an alternative for the test unit
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`OEn=0 and WEn=l, and validated by a defined edge of
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`for five inputs and two outputs.
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`the CLK and active level of the clock enable CKE.
`Corresponding features in the various Figures are
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`3.The test unit's ROM table is addressed by the 'extended'
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`denoted by the same reference symbols.
`30
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`address bus which is defined as the actual address bus,
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`FIG. 1 shows an embodiment of a circuit 100 in accor­
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`extended with the control signals RAS, CAS, DQML and
`dance with the invention. The circuit 100 has 1/0 nodes 130,
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`DQMU.
`140, through which the circuit 100 is connectable to external
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`4.The width of the ROM table is equal to the width of the
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`circuits. An 1/0 node may be an input node, i.e. a node only
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`data bus plus possible additional outputs of the circuit
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`suitable to receive signals, an output node, i.e. a node only 35
`100.
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`suitable to send signals, or a bi-directional node, i.e. a node
`5.Each of the primary addresses (all but one address bits
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`suitable to either receive or send signals. For performing its
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`equal to '0', one address bit equal to '2') reads the all '1'
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`intended normal mode function, the circuit 100 has a main
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`data word. All other extended addresses read the all '0'
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`unit 110, which is, by way of example, assumed to be an
`data word.
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`SDRAM. Thus, the circuit 100 is in fact an SDRAM device.
`40
`The table below shows the contents of the ROM table for
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`It is further assumed that the circuit 100 is part of an
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`the SDRAM device of circuit 100, with 12 bit wide address
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`assembly, whereas interconnects between the circuit 100 and
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`bus, RAS, CAS, DQML and DQMU and four data pins.
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`further parts of the assembly should be testable. Hereto, the
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`circuit 100 has a test unit 120, which is connected to the
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`main unit 110 via n parallel connections and to the 1/0 nodes 45
`extended address
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`130.In a normal mode of the circuit 100, the test unit 120
`bus
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`is transparent, and signals can pass freely between the 1/0
`AAAAAAAAAAAARCDD
`119876543210AAQQ data bus
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`nodes 130 and the main unit 110. In a test mode of the circuit
`10
`SSMM
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`100, the main unit 110 is logically disconnected from the 1/0
`LH
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`nodes 130 and the test unit 120 is in control. It is noted that 50
`0000000000000001 1111
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`preferably, but not necessarily, all 1/O nodes are arranged for
`0000000000000010 1111
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`interconnect testing. To indicate this, the 1/0 nodes 140 are
`0000000000000100 1111
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`not connected to the test unit 120, and therefore, the test unit
`0000000000001000 1111
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`120 does not offer testability for interconnects correspond-
`0000000000010000 1111
`0000000000100000 1111
`ing to these 1/0 nodes 140.
`55
`0000000001000000 1111
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`SDRAM devices have a highly standardised pin lay-out.
`0000000010000000 1111
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`FIG. 1 does not give an exact representation of such a
`0000000100000000 1111
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`pin-layout, but it schematically shows which 1/0 nodes are
`0000001000000000 1111
`0000010000000000 1111
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`generally present on an SD RAM device. The circuit 100 has
`0000100000000000 1111
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`a data bus D0-D3, an address bus AO-All, and a control bus 60
`0001000000000000 1111
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`including a Chip Select pin (CSn), an Output Enable pin
`0010000000000000 1111
`(OEn), Write Enable pin (WEn), Clock pin (CLK), Clock
`0100000000000000 1111
`1000000000000000 1111
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`Enable pin (CKE), Row Address Strobe pin (RAS), Column
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`'any other address'
`0000
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`Address Strobe pin (CAS), and Data 1/0 Mask pins (DQML
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`and DQMH). The precise functions of these pins are not 65
`relevant for the invention. However, the standardised pin With the above described functional behaviour of the
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`lay-out obstructs the addition of boundary-scan circuitry circuit 100 after power up, an efficient test for the extended
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`IPR2021-01488
`Apple EX1001 Page 7
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`

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`US 6,807,505 B2
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`1111119876543210
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`As mentioned above, the mechanism for switching the
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`address bits consist of just reading all primary addresses (16
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`circuit from the normal mode into the test mode may be
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`in the above case) and one other address. The test sequence
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`implemented in different ways. In the SD RAM embodiment,
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`covers the following faults:
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`the circuit is brought into the test mode by performing a read
`1.any stuck-at 1 on an extended address pin
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`5 action after power up. Such a read action after power up, is
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`2.any stuck-at O on an extended address pin
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`a special action which does not form part of the normal
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`3. any 2-net AND-type short between any pair of address
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`actions for the circuit and has been given the special
`pins
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`meaning of a command for switching into the test mode. In
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`4. any 2-net OR-type short between any pair of address pins
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`general, any pattern or sequence of patterns applied to one
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`5.any stuck-at 1 on a data pin
`10
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`or more 1/0 nodes of the circuit can be given the special
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`6.any stuck-at O on a data pin
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`meaning of a command for going into test mode, provided
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`An interconnect with a stuck-at fault remains at either
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`that this pattern or sequence is not used in the normal mode
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`logic high or logic low, no matter what signals are applied
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`of the circuit. An alternative is to provide the circuit with a
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`to it. A 2-net AND-type short between a first and a second
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`the 1/0 nodes, to 15 dedicated test control node, in addition to
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`interconnect causes the two interconnects to carry the same
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`control whether the circuit is to behave in the normal
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`logic value as determined by either one of the interconnects.
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`operational mode or in the test mode. The actual signal value
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`A 2-net OR-type short between a first and a second inter­
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`on the test control node, in relation with predefined values
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`connect causes the two interconnects to carry complemen­
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`tary logic values as determined by either one of the inter­
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`corresponding to the respective modes, brings the circuit
`connects.
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`20 into the desired mode.
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`The above test sequence provides a diagnostic resolution
`FIG. 2 shows a way to provide access during interconnect
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`down to a single pin. Note that this test concept is indepen­
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`test to a circuit 200 that is testable in accordance with the
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`dent from the number of extended address lines or the
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`invention. The circuit 200 includes a test unit 205 that is
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`number of data lines, nor is there any relation assumed
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`operable as a low complexity memory. A neighbouring
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`between the two numbers.
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`25 circuit 210, which has boundary-scan circuitry, can provide
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`The second part of the interconnect test aims at testing for
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`data to and receive data from the circuit 200 via a control and
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`shorts between the interconnects making up the data bus,
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`address bus 220 and a bi-directional data bus 230.
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`and is functionally described by:
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`Alternatively, when only a ROM behaviour is implemented
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`1. Write access is provided to a command register, which is
`in the test unit 205, the data bus 230 would be unidirectional,
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`loaded with the value of the ( actual) address bus.
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`30 i.e. from the circuit 200 to the circuit 210.
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`2. There will be a certain combination of address bits, which,
`A number of interconnects make up the control and
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`after being loaded into the aforementioned command
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`address bus 220 and the data bus 230. The function of these
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`register, select a single write/read register that logically
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`interconnects during a normal mode is irrelevant for the
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`forms part of the test unit, with a width equal to the width
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`invention. When the circuit 200 is a memory device, there
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`of the data bus. This combination of address bits is to be 35
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`will also be a 'normal mode data bus'. The 'test mode data
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`determined by the manufacturer of the device and to be
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`bus' 230 could partly or completely coincide with the normal
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`specified in the data sheet.
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`mode data bus. The same applies to the control and address
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`This single write/read register can then be used to write
`bus 220.
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`data and read data. Algorithms are available to generate a
`Via a boundary-scan chain 240 data is shifted into circuit
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`minimal set of test patterns which cover all AND-type and 40
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`210, that data making up read and/or write commands to be
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`OR-type shorts between any pair of data lines. The table
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`supplied to the circuit 200. After a read command, the
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`below shows a set of test patterns for a 16-bit wide data bus.
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`boundary-scan chain 240 captures data supplied to the data
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`bus 230 by the circuit 200. That data subsequently are
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`shifted out to be analysed externally.
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`FIG. 3 shows a further way to provide access during
`45
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`interconnect test to a circuit 300 that is testable in accor­
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`dance with the invention. The circuit 300 includes a test unit
`
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`305 that is operable as a low complexity memory via control
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`and address bus 320 and data bus 330. A neighbouring
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`50 circuit 310, which is a microprocessor, executes the program
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`with the necessary read and write commands. The test
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`program and the test data are stored in a memory 340 of the
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`circuit 310. Preferably, the circuit 310 also analyses the data
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`obtained from the circuit 300. The circuit 310 could alter-
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`natively be an ASIC.
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`For dynamic memory devices, like the circuit 100, the 55
`The above presented design-for-test method does not
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`above described two parts of the interconnect test have read
`
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`require any additional pins to the device for test access,
`and write access to the test unit which is not affected with
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`meeting pin count and pin compat