`
`JTAG BOUNDARY-SCAN, FIRMLY BASED ON IEEE STANDARDS – JTAG
`
` Contact (https://www.jtag.com/contact-us/)
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` Login (https://www.jtag.com/login/) Language
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`(https://www.jtag.com)
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`JTAG boundary-scan, firmly based on IEEE standards
`JTAG boundary-scan, firmly based on IEEE standards
`
`The serial interface and logic were originally developed by a group of test professionals from Philips, BT,
`GEC, TI and others known as JTAG (the Joint Test Action Group) throughout the late 1980s. The group
`continued as an IEEE working group to complete the final standard which then got the official name IEEE
`Std 1149.1 (https://standards.ieee.org/standard/1149_1-1990.html), the IEEE Standard Test Access Port
`(JTAG interface) and Boundary-Scan Architecture. The standard was first released in 1990. Since then
`enhancements have been made and the latest update was done in 2013, see IEEE 1149.1-2013.
`
`The IEEE Std 1149.1 is often referred to by other names such as JTAG, JTAG boundary-scan, or Dot1. JTAG
`devices are officially referred to as IEEE 1149.1 compliant devices.
`
`The standard defines the serial (JTAG) interface, called the Test Access Port (TAP), and the test logic
`architecture built into chips. One specific example of test logic is defined in the standard, the so called
`boundary-scan register, for testing connections between devices on a PCBA.
`
`The TAP features four (or sometimes five) signals:
`
`TCK (Test clock)
`TMS (Test Mode Select)
`TDI (Test Data In)
`TDO (Test Data Out)
`TRST (Test logic Reset) (optional)
`
`•
`•
`•
`•
`•
`
`To simplify the test infrastructure within a PCBA it is common to connect the devices in serial (daisy chain)
`formation so that TDO from the first device connects to TDI of the next (and so on) to form a so-called scan
`chain.
`https://www.jtag.com/jtag-boundary-scan-firmly-based-on-ieee-standards/
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`JTAG BOUNDARY-SCAN, FIRMLY BASED ON IEEE STANDARDS – JTAG
`
`The test logic architecture comprises of one Instruction Register (IR) and multiple Data Registers (DR). By
`loading an opcode in the IR with an IR-scan a specific DR is selected which is then accessed with
`consecutive DR-scans.
`
`When the boundary-scan register is selected as DR, this register will control the device’s pins while
`isolating the primary core functions of the device.
`
`The test logic architecture from Dot1 is defined such that other data registers (DRs) can easily be added in a
`chip design. For example the debug logic of microprocessors and microcontrollers or the programming
`logic in modern CPLDs and FPGAs. These DRs are defined in additional standards building upon and
`enhancing the original Dot1 (https://www.jtag.com/other-standards-since-the-release-of-dot-1/).
`
`Happy to serve you!
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`engaging with our customers. Once you become a JTAG Technologies customer
`you are an integral part of our business with free access to our world-wide
`support network.
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`Contact
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`We are here to help you.
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`We have sales and factory-trained technical support in virtually every part of the world
`where electronics products are manufactured.
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`Worldwide Contacts (https://www.jtag.com/contact-us/)
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`https://www.jtag.com/jtag-boundary-scan-firmly-based-on-ieee-standards/
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`JTAG BOUNDARY-SCAN, FIRMLY BASED ON IEEE STANDARDS – JTAG
`
`-· .: J,1
`
`Quick links
`
`What is boundary-scan (https://www.jtag.com/boundary-scan/)
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`Hardware (https://www.jtag.com/products/hardware/)
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`Software (https://www.jtag.com/products/software/)
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`Software updates (https://www.jtag.com/software-download/)
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`Events (https://www.jtag.com/events/)
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`MarCom (https://www.jtag.com/marcom/)
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`Testing of electronics (https://www.jtag.com/testing-of-electronics/)
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`Hardware (https://www.jtag.com/products/hardware/)
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`Software (https://www.jtag.com/products/software/)
`Software updates (https://www.jtag.com/software-download/)
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`3/3
`
`IPR2021-01488
`Apple EX1002 Page 3
`
`
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