United States Patent [19]
`Bazinet et al.
`
`I 1111111111111111 11111 111111111111111 IIIII IIIII IIIII IIIII 111111111111111111
`.
`US005627460A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,627,460
`May 6, 1997
`
`[54] DC/DC CONVERTER HAVING A
`BOOTSTRAPPED HIGH SIDE DRIVER
`
`[75]
`
`Inventors: John P. Bazinet. Concord; John A.
`O'Connor, Merrimack, both of N.H.
`
`[73] Assignee: Unitrode Corporation, Billerica, Mass.
`
`[21] Appl. No.: 365,349
`
`Dec. 28, 1994
`[22] Filed:
`Int. Cl.6
`...................................................... G0SF 1/618
`[51]
`[52] U.S. Cl . .......................... 323/288; 323/224; 323/266;
`323/284
`[58] Field of Search ..................................... 323/223, 225,
`323/283-288, 266; 327/108
`
`[56]
`
`References Cited
`
`U.S. P.tXIENT DOCUMENTS
`
`6/1985 Phaneuf .................................. 323/282
`4,521,725
`4,559,590 12/1985 Davidson .................................. 363121
`4,577,268
`3/1986 Easter et al ............................... 363/21
`4,652,808
`3/1987 Mostyn et al . .................. :....... 323/222
`
`7/1987 Tanaka et al ........................... 323/290
`4,680,534
`8/1990 Peterson .................................. 363/124
`4,947,311
`6/1991 Kinzer .................................... 357/23.4
`5,023,678
`6/1992 Gauen ..................................... 323/222
`5,126,651
`8/1993 Ghotbi ...................................... 363/89
`5,233,509
`5,258,662 11/1993 Skovrnand ........................... 307/296.3
`4/1994 Smith ...................................... 307/571
`5,304,875
`5,408,150
`4/1995 Wtlcox .................................... 327/108
`1/1996 Wtlcox et al ........................... 323/287
`5,481,178
`
`Primary Examiner-Peter S. Wong
`Assistant Examiner-Shawn Riley
`Attorney, Agent, or Firm-Weingarten, Schurgin, Gagnebin
`& Hayes LLP
`
`[57]
`
`ABSTRACT
`
`A synchronous step-down DC to DC converter includes a
`bootstrap capacitor monitored by a controller for maintain(cid:173)
`ing a desired bootstrap voltage to drive a high side NMOS
`switch. The controller temporarily increases the duty cycle
`of the low side NMOS switch when the bootstrap voltage
`decreases below a predetermined level to maintain a mini(cid:173)
`mum level of charge on the bootstrap capacitor.
`
`14 Claims, 4 Drawing Sheets
`
`V1N - - - - - - - - - - - - - - - - - - - - - - ,
`
`46
`)!---.----Vs
`26
`
`38
`
`,.,--30
`~
`- - - REGULATOR CONTROL CIRCUIT 7
`I
`34 l
`
`90
`2
`I
`.----........ ...__~_, I
`GATE DRIVE
`~UIT (FIG. 6)
`1PWM Cot.MAND
`
`I
`
`BOOTSTRAP
`CONTROLLER
`(FIG. 2)
`
`Vsense
`
`:---.....
`14
`
`Vsense
`2.0V
`
`Vrallll
`
`I
`I
`I
`_
`I
`L------------------------------~ ~
`
`51
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1044
`Page 1 of 11
`
`

`

`0-\ =
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`I
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`
`FIG. 1
`. '-'
`
`*
`
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`
`Vsense
`
`20
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`
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`OUT
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`4
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`
`I
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`34 I
`I
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`
`CIRCUIT (FIG. 6) 1 :
`
`GATE DRIVE
`
`1
`
`REGULA TOR ctNTROL CIRCUIT
`
`/' -30
`
`38
`
`~8
`
`26
`' Y9
`
`Vramp
`
`140
`
`SOFTST ART /SLEEP
`
`l 2.0V
`I l Vsense
`
`(FIG. 2)
`CONTROLLER
`BOOTSTRAP
`
`42 ~
`
`-
`
`~ . .
`
`10~
`
`REG.
`LINEAR
`
`I
`
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`I
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`I
`I
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`I
`1
`r------------
`~ 44
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1044
`Page 2 of 11
`
`

`

`U.S. Patent
`
`May 6, 1997
`
`Sheet 2 of 4
`
`5,627,460
`
`3 6~
`
`FIG. 2
`
`PWM
`COMMAND
`
`V,00% OT
`
`90
`
`HIGH
`DRIVER
`
`4 Ov
`
`21
`
`z\
`
`zs
`
`75 ~4
`
`112~ 7 \7 \7 \7 \:::p
`\~:1~1-~n~ _ __.n~--n~--IL.
`I n n n rL
`GATE
`116
`'- DRIVE
`3 SIGNAL 40
`{S1G~~~38 I
`
`114
`
`PWM
`
`11
`
`11
`
`11
`
`I [,
`
`FIG.
`
`FIG.
`
`122
`\
`~ COMMAND
`SIGNAL 62 1--__,___~___.__ _
`
`___.______.__ _
`
`_,_____.__ _
`
`\-'¥ramp
`l
`_,__~>
`I
`
`120 ~ -z----=-\-Z---:,,-\-7-~\--Z--,,--\-;:~
`1.0v 7 V V V
`PWM l
`124 GATE l
`I
`\__ DRIVE
`GATE D
`4 SIGNAL 40 1---..1-. _
`
`_.____,__--1--___.___.......____.___ --'-~>
`
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`126 SIGNAL 38 -1-------1.._--1-___,_ _
`
`__._____,_ _
`
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`
`I .
`I
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1044
`Page 3 of 11
`
`

`

`~
`-..
`Ol
`
`~ =
`~ -.. .a;.
`
`,I::..
`~
`w
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`00 =(cid:173)
`
`FIG. 5
`
`2.5V REF
`
`'---J
`
`Vramp
`
`OSCLLATOR
`
`LOW POWER =--l N
`
`· RffGOOD
`146
`
`144
`
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`.
`2.s¥7
`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
`"---160
`
`20mV
`
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`VREF o------1
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`
`\..--------1 ~ LOW POWER
`
`159
`
`/158
`
`d
`
`162
`
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`
`-:-
`
`152
`
`150
`
`SS Done
`
`2.5V. REF
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1044
`Page 4 of 11
`
`

`

`I ~ ~ ~ $1',
`
`~
`\0
`\0
`I-"
`
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`
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`
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`159
`
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`
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`
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`
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`
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`
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`
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`
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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1044
`Page 5 of 11
`
`

`

`5,627,460
`
`1
`DC/DC CONVERTER HAVING A
`BOOTSTRAPPED HIGH SIDE DRIVER
`
`FIELD OF THE INVENTION
`
`This invention relates generally to switching converters
`and more particularly, to Buck, or step-down converters
`having a bootstrapped high side driver.
`
`BACKGROUND OF THE INVENTION
`
`As is known in the art of switching power supplies, or
`converters, a Buck topology is used to convert an input
`voltage to a lower output voltage. A synchronous Buck
`converter includes a pair of switching transistors coupled in
`series across the input voltage source, with a high side
`switch coupled to the input voltage and a low side switch
`coupled to ground. The switches are controlled to alternat(cid:173)
`ingly conduct with complementary duty cycles to maintain
`a predetermined output voltage. An output filter, including
`an inductor and a capacitor, is coupled to the interconnection
`between the pair of switching transistors and averages the
`switched input voltage to provide the output voltage.
`The use of N-channel MOSFEf devices for the converter
`switching elements is advantageous due to the relatively low
`drain to source resistance associated with such devices and
`thus, the correspondingly low power dissipation. More
`particularly, in order to realize the desired low drain to
`source resistance, the high side NMOS switch requires a
`gate drive signal of greater amplitude than the input voltage.
`Specifically, a gate to source voltage of approximately ten
`volts is required to fully enhance the NMOS switch.
`Various techniques are available for generating the req(cid:173)
`uisite gate voltage for the high side NM OS switch, including
`the use of a voltage doubler circuit or a boost converter.
`However, both of these techniques require an additional
`switching element and other circuitry, thereby disadvanta(cid:173)
`geously adding to the cost and complexity of the converter.
`Another technique for providing the necessary gate drive
`voltage to the high side NMOS switch is to charge a
`bootstrap capacitor with the input voltage, or a regulated
`version thereof. In order to avoid the necessity of using an
`additional switch, the charge path for the bootstrap capacitor
`includes the low side NMOS switch. However, in certain
`instances, such as where the input voltage is provided by a
`battery with a voltage which inherently decays over time or
`where the converter output is heavily loaded, a sufficient
`gate voltage level may not be continuously maintained. That
`is, in such applications, 100% duty cycle operation of the
`high side switch will be required. Since the bootstrap
`capacitor charges through the low side switch, its charge
`time and thus, the bootstrap voltage may decrease to an
`unacceptable level by the concomitantly reduced duty cycle
`of the low side switch.
`
`SUMMARY OF THE INVENTION
`In accordance with the invention, a step-down converter
`includes NMOS switches, a bootstrap capacitor for supply(cid:173)
`ing a bootstrap voltage to a high side gate drive circuit, and
`a bootstrap controller for sensing the bootstrap voltage and
`adjusting the duty cycle of the low side switch so as to
`increase the bootstrap voltage when such voltage falls below
`a predetermined level. More particularly, the bootstrap
`capacitor is charged by a voltage regulator which, in turn is
`powered by the input voltage. The charge path for the
`bootstrap capacitor includes the low side switch. The boot(cid:173)
`strap controller provides a control, or PWM override signal,
`
`5
`
`2
`to the PWM circuit to temporarily increase the duration of
`conduction of the low side switch when the bootstrap
`voltage falls below the predetermined level, thereby charg-
`ing the bootstrap capacitor.
`With this arrangement, a step-down converter utilizing
`NMOS switches is provided with a simple bootstrap capaci(cid:173)
`tor arrangement to generate and maintain the desired voltage
`level for driving the high side switch. Charging the bootstrap
`capacitor through a path including the low side switch
`IO eliminates the need for an additional switching device. The
`bootstrap controller maintains the bootstrap voltage at a
`desired level even during periods when full, or nearly full
`duty cycle is required of the high side switch.
`In one embodiment, the bootstrap controller includes a
`15 latch for providing the PWM override signal to increase the
`duty cycle of the low side switch when the following
`conditions occur simultaneously: the bootstrap voltage is
`below the predetermined level, at or near 100% duty cycle
`is commanded of the high side switch, and the high side
`20 switch is closed. The latch is reset when the following
`conditions occur simultaneously: the bootstrap voltage is
`equal to or greater than a second predetermined level and the
`high side switch is closed. This reset scheme ensures that the
`bootstrap controller does not affect the duty cycle of the
`25 switches unless the bootstrap voltage is below a predeter(cid:173)
`mined level corresponding to the desired gate drive level for
`the high side switch, so as to permit virtual 100% duty cycle
`operation of the high side switch. That is, the duty cycle of
`the high side switch deviates from a commanded 100% only
`30 for the relatively few switching cycles necessary to charge
`the bootstrap capacitor to the desired voltage level.
`
`35
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`This invention is pointed out with particularity in the
`appended claims. The above and further advantages of this
`invention may be better understood by referring to the
`following description taken in conjunction with the accom(cid:173)
`panying drawings, in which:
`FIG. 1 is a schematic of a step-down converter in accor-
`40 dance with the present invention;
`FIG. 2 is a schematic of the bootstrap controller of FIG.
`1;
`FIG. 3 is a PWM signal diagram showing the PWM
`45 related signals under illustrative operating conditions;
`FIG. 4 is a PWM signal diagram showing the PWM
`related signals under a different set of illustrative operating
`conditions;
`FIG. 5 is a schematic of additional features of the regu-
`50 lator control circuit of FIG. 1; and
`FIG. 6 is a schematic of the gate drive circuit of FIG. 1.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`Referring to FIG. 1, a Buck, or.step-down converter 10
`which converts a DC input voltage VIN to a lower DC output
`voltage V ouT includes a pair of series connected synchro(cid:173)
`nously operated switches, 12, 14 across which the input
`voltage VIN is switched at a relatively high frequency, such
`60 as one to two hundred kilohertz. An output filter 16, includ(cid:173)
`ing an inductor 18 and a capacitor 20, is coupled between the
`interconnection node 19 of the switches 12, 14 and an output
`terminal 24 of the converter 10 at which the output voltage
`V ouT is provided. A current sense resistor 22 is connected
`65 between the inductor 18 and the capacitor 20, as shown.
`A regulator control circuit 30 includes a pulse width
`modulator (PWM) circuit 32 and a gate drive circuit 34. In
`
`55
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1044
`Page 6 of 11
`
`

`

`5,627,460
`
`3
`general. the control circuit 30 receives a signal V sense
`indicative of the output voltage V ouT and signals 51, 53
`indicative of the output current Isense and provides. via the
`gate drive circuit 34. gate drive signals 38, 40 to control the
`switches 12, 14. respectively. Gate drive signals 38, 40 cause 5
`the switches 12, 14 to conduct in an alternating manner with
`complementary duty cycles, so as to maintain the output
`voltage V ouT at a predetermined level.
`Switches 12, 14 are NMOS FEI's. Use ofNMOS FEI's as
`the switching devices is advantageous due to the relatively 10
`low drain to source resistance associated therewith and thus,
`concomitantly low power dissipation. A first one of the
`switches 12 is connected to the input voltage VIN and will be
`referred to hereinafter as the high side switch 12. The second
`switch 14 is connected to ground and will be referred to 15
`hereinafter as the low side switch. High side switch 12 has
`a drain terminal connected to the input voltage VIN• a gate
`terminal receiving gate drive signal 38, and a source termi-
`nal connected to a drain terminal of low side switch 14 and
`to the output filter inductor 18. The low side switch 14 has 20
`a gate terminal receiving gate drive signal 40 and a source
`terminal connected to ground, as shown.
`A bootstrap capacitor 26 is charged through a charging
`path including low side switch 14, as indicated by arrows 28,
`and provides a bootstrap voltage VO to the gate drive circuit 25
`34 sufficient to fully enhance the high side switch 12. The
`control circuit 30 further includes a bootstrap controller 36
`which provides a virtual 100% duty cycle mode of
`operation, as will be described. Suffice it here to say that the
`bootstrap controller 36 senses the bootstrap voltage V 8
`across the bootstrap capacitor 26 and temporarily increases
`the duty cycle of the low side switch 14 in response to the
`bootstrap voltage falling below a first predetermined level to
`permit charging of the bootstrap capacitor 26. With this
`arrangement, the bootstrap voltage V 8 is maintained at a 35
`desired level corresponding to the gate drive voltage nec(cid:173)
`essary to fully enhance the high side switch 12.
`The converter 10 includes a linear regulator 42 which
`receives the input voltage VIN and which provides a regu- 40
`lated voltage V R to charge the bootstrap capacitor 26. A
`bypass capacitor 44 is connected between the regulated
`voltage output and ground and a diode 46 is provided with
`the anode connected to the regulated voltage V R and the
`cathode connected to a first terminal of the bootstrap capaci- 45
`tor 26. A second terminal of the bootstrap capacitor 26 is
`connected to the interconnection node 19 between the source
`terminal of high side switch 12 and the drain terminal of low
`side switch 14, as shown. In one illustrative embodiment, the
`input DC voltage VIN is provided by a battery with a 50
`nominal voltage range of between 11-36 volts and the linear
`regulator 42 provides a nominal regulated voltage V R of 11.0
`V. Preferably, the control circuit 30 and linear regulator 42
`are provided in a monolithic integrated circuit.
`During portions of each switching cycle when the high 55
`side switch 12 conducts, the bootstrap capacitor 26 dis(cid:173)
`charges through the gate drive circuit 34. During alternating
`portions of the switching cycle, when the low side switch 14
`conducts, the bootstrap capacitor 26 is charged by the
`regulated voltage V R so as to provide a bootstrap voltage V 8 60
`of 11.0 volts minus the forward voltage drop of diode 46, as
`is desired. The charge path is through the low side switch 14,
`as indicated by arrows 28.
`More particularly, since the bootstrap capacitor 26 is
`referenced to the interconnection node 19, the bootstrap 65
`is approximately ten volts above the input
`voltage V 8
`voltage VIN. That is, when the high side switch 12 turns on,
`
`30
`
`4
`the node 19, which is close to ground ( since the low side
`switch 14 was previously on) rises to approach the input
`voltage VIN. As this occurs, the bootstrap voltage V 8 , being
`referenced to this rising potential node 19 also rises, so as to
`provide a bootstrap voltage V 8 of approximately ten volts
`greater than the input voltage VIN.
`As noted above, the control circuit 30 receives a signal
`vsense indicative of the output voltage V OUT· More
`particularly, the output voltage indicative signal Vsense is
`derived from a resistor divider coupled between the output
`voltage V ouT and ground and including resistors 48, 50. The
`converter 10 of FIG. 1 is a current mode converter. Thus, the
`control circuit 30 further receives signals 51, 53 from across
`a current sense resistor 22, as shown. The voltage across the
`resistor 22 is sensed by a differential amplifier 52, the output
`of which provides a signal Isense indicative of the output
`current.
`The control circuit 30 includes a voltage amplifier 54 and
`a current amplifier 56. The voltage amplifier 54 provides a
`signal representative of the difference between the output
`voltage indicative signal V sense and a fixed reference
`voltage, such as 2.0 V. The voltage amplifier 54 may further
`receive a softstart signal 140 in order to clamp the output
`voltage of the amplifier 54 to provide a controlled start up of
`the converter. The user controllable softstart signal 140 also
`controls a "sleep mode" of converter operation, as will be
`described in conjunction with FIG. 5. The output of the
`voltage amplifier 54 is coupled to an input of the current
`amplifier 56 through a resistor divider 58. The current
`amplifier 56 provides an error signal 60 to an input of the
`PWM32.
`The PWM 32 compares the error signal 60 to a sawtooth
`ramp signal V ramp to provide a PWM command signal 62 to
`the gate drive circuit 34. The PWM command signal 62
`determines the duty cycles of the NMOS switches 12, 14.
`More particularly, the duty cycles of switches 12, 14 refer to
`the respective ratio of "on time" to the switching period. As
`noted above, the duty cycle of switches 12, 14 are comple(cid:173)
`mentary with respect to one another, such that when one of
`the switches is on, or closed, the other is off, or open. The
`gate drive circuit 34, which will be described in greater
`detail below in conjunction with FIG. 6, receives the PWM
`command signal 62 and the bootstrap voltage V 8 and
`provides gate drive signals 38, 40 to switches 12, 14,
`respectively.
`The bootstrap controller 36 receives and senses the boot(cid:173)
`strap voltage VO and provides a PWM override signal 64 to
`the PWM 32 in response to the bootstrap voltage VO being
`below a first predetermined level, as will be described
`further in conjunction with FIG. 2. Suffice it here to say that
`when the bootstrap voltage V 8 falls below the first prede(cid:173)
`termined level, corresponding to the desired level of gate
`drive signal for the high side switch 12, the PWM override
`signal 64 causes the PWM 32 to temporarily adjust the duty
`cycles of the switches 12, 14 in order to charge the bootstrap
`capacitor 26 to the desired voltage. In this way, the bootstrap
`voltage VO is maintained at the desired level. Moreover, this
`advantageous result is achieved without sacrificing output
`voltage regulation. This is because, when the bootstrap
`voltage VO is sensed to be below the first predetermined
`level, the duty cycle adjustment necessary to raise the
`bootstrap voltage back to the desired level lasts for only a
`few switching cycles.
`Referring now also to FIG. 2, the bootstrap controller 36
`is shown in greater detail. The controller 36 includes a
`comparator 80 which compares the input voltage VIN to a
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1044
`Page 7 of 11
`
`

`

`5,627,460
`
`5
`
`10
`
`5
`voltage equal to the bootstrap voltage VB minus a fixed
`offset voltage. such as 8.0 V. The output of the comparator
`80 thus indicates whether or not the bootstrap voltage VB is
`greater or less than the first predetermined level of VIN+8.0
`V. Specifically. the output of the comparator 80 is at a logic
`high level when the bootstrap voltage VB is less than
`VIN+8.0 V and is at a logic low level when the bootstrap
`voltage VB is greater than or equal to a second predeter(cid:173)
`mined level of VIN+9.5 V.
`The bootstrap controller 36 further includes a second
`comparator 82 which compares the PWM command signal
`62 (FIG. 1) to a fixed reference voltage V ioo%Dr• which
`corresponds to the voltage level of the PWM command
`signal 62 when an approximately 100% duty cycle is com(cid:173)
`manded of the high side switch 12. In the case where the
`voltage V ioo%Dr corresponds to a 100% duty cycle for the
`high side switch. the output signal 86 of the comparator 82
`is at a logic high level when the PWM command signal 62
`corresponds to 100% duty cycle of the high side switch 12
`and is at a logic low level when lesser duty cycles are
`required of the high side switch 12. The voltage level of the
`V ioo%Dr signal is selected so that the bootstrap controller 36
`only affects the duty cycles of the switches 12. 14 when the
`bootstrap voltage has decayed below the first predetermined
`level. thereby indicating that the low side switch is not
`closed for a long enough duration to permit the bootstrap
`capacitor to remain charged. The voltage V ioo%Dr will be
`described hereinafter as corresponding to the voltage level
`of the PWM command signal 62 when the duty cycle of
`switch 12 is at 100%. More generally however. voltage
`V ioo%D may correspond to the level of the PWM command
`signal 62 when the duty cycle of switch 12 is between
`approximately 85%-100%.
`Comparator output signals 84 and 86 are coupled to inputs
`of an AND gate 88. Coupled to a third input of AND gate 88
`is a high driver signal 90 provided by the gate drive circuit
`34 (FIGS. 1 and 6). The high driver signal 90 is in a logic
`high state when the high side switch 12 is closed and is in
`a logic low state when the high side switch 12 is open, as
`will become apparent from the discussion of FIG. 6 below. 40
`The output signal 92 of AND gate 88 is coupled to the input
`of a latch. or flip-flop 94. The reset input of latch 94 receives
`the output signal of a NOR gate 96, the inputs to which are
`provided by logic signals 84 and 90, as shown.
`The output logic signal 92 of AND gate 88 is in a logic
`high state when each of the three input signals 84, 86, and
`90 is in a logic high state. Thus. logic signal 92 is in a logic
`high state when the bootstrap voltage VB is less than
`VIN+8.0 V, the PWM command signal 62 is at a level 50
`corresponding to a 100% duty cycle of the high side switch
`12. and the high side switch 12 is closed. With the logic
`signal 92 in a logic high state. the latch 94 is set.
`When the latch 94 is set, the PWM override signal 64
`causes the PWM 32 to increase the duty cycle of the low side 55
`switch 14 and concomitantly to decrease the complementary
`duty cycle of the high side switch 12, to permit the charging
`of the bootstrap capacitor 26 (FIG. 1). More particularly, the
`output signal 98 of latch 94 is connected to the base terminal
`of a bipolar transistor 100. the emitter terminal of which is 60
`connected to ground. The collector terminal of transistor 100
`is connected to a resistor divider including resistors 102,
`104. The PWM override signal 64 is provided at the inter(cid:173)
`connection of series connected resistors 102. 104. as shown.
`In operation. when the latch 94 is set. output signal 98 is 65
`in a logic high state, causing the collector of transistor 100
`to approach ground and the voltage level of the PWM
`
`6
`override signal 64 to be determined by resistors 102, 104.
`More particularly, resistors 102. 104 are selected so that
`when the latch 94 is set. the PWM override signal 64 is at
`a voltage level less than the error signal 60 (FIG. 1) so that
`the override signal controls the PWM 32. Specifically, the
`PWM override signal 64 causes the duty cycles of switches
`12, 14 to be at a level that permits the bootstrap voltage VB
`to be replenished within a few switching cycles in order to
`avoid degradation of the output voltage V our, such as
`approximately 50%. In this way. the charging path from the
`input voltage VIN through the linear regulator 42. diode 46.
`capacitor 26. and low side switch 14 is available for approxi(cid:173)
`mately one-half of each switching cycle to charge the
`bootstrap capacitor 26.
`Once the latch 94 is set, bootstrap capacitor 26 is charged
`15 until the bootstrap voltage VB rises to a second
`predetermined. desired level. The second predetermined
`level corresponds to a hysteresis value above the first
`predetermined level, such as 1.5 volts greater than the first
`predetermined level of VIN+8.0 volts. More particularly,
`20 once the bootstrap voltage VB rises to the second predeter(cid:173)
`mined level. the output signal 106 of the NOR gate 96
`transitions to a logic high state, since the bootstrap voltage
`VB is greater than or equal to VIN+9.5 V and the high side
`switch 12 is closed, as indicated by logic high levels of
`25 signals 84. 90. respectively. When the latch 94 is reset, latch
`output signal 98 transitions to a logic low level. causing the
`PWM override signal 64 to be pulled to the error signal 60
`at the output of the current amplifier 56 through resistor 102.
`Since the error signal 60 will be less than the PWM override
`30 signal 64, the error signal 60 controls the PWM command
`signal 62 and thus also the duty cycles of the switches 12 and
`14. Thus, it is apparent that once the bootstrap voltage VB
`rises to a level greater than or equal to VIN+9.5 V and the
`high side switch 12 is closed, the bootstrap controller 36 no
`35 longer affects the PWM operation and the duty cycles of
`switches 12 and 14.
`The operation of the bootstrap controller 36 and the PWM
`32 is illustrated by the signal diagrams of FIGS. 3 and 4.
`Signal diagram 112 in FIG. 3 shows exemplary PWM input
`signals V ramp• error signal 60, and PWM override signal 64.
`The illustrated PWM override signal 64 is characteristic of
`the bootstrap voltage VB being greater than VIN+8.0 V. Since
`the error signal 60 is lower than the PWM override signal 64,
`the error signal controls the PWM command signal 62.
`Specifically, the PWM command signal 62 is high when the
`ramp voltage V ramp is greater than the error signal 60, as
`shown in signal diagram 114. The gate drive signal 40
`provided to the gate terminal of low side switch 14 is a
`buffered, amplified version of the PWM command signal 62,
`as shown in signal diagram 116, and as will be described
`further in conjunction with FIG. 6. The complementary gate
`drive signal 38 provided to the gate terminal of the high side
`switch 12 is an inverted version of gate drive signal 40, as
`shown in signal diagram 118.
`When the latch 94 is set, causing the PWM override signal
`64 to be at a voltage set by resistors 102, 104, the override
`signal 64 is lower than the error signal 60, as shown in signal
`diagram 120 of FIG. 4. Recall that the latch 94 is set, causing
`the PWM override signal 64 to be below the error voltage
`60, when the error signal 60 is at a level corresponding to at
`or near 100% duty cycle of the high side switch 12, as
`illustrated by the error signal 60 being at the top of the ramp
`signal V ramp· Under such operating conditions, the PWM
`override signal 64 governs the PWM command signal 62
`such that the PWM command signal 62 is high when the
`ramp signal V ramp is greater than the PWM override signal
`64, as is evident from the signal diagram 122.
`
`45
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1044
`Page 8 of 11
`
`

`

`5,627,460
`
`5
`
`35
`
`7
`It may be desirable to limit the extent to which the PWM
`override signal 64 can increase the duty cycle of the low side
`switch 14 in order to permit the bootstrap capacitor 26 to be
`replenished within a few switching cycles without sacrific(cid:173)
`ing output voltage regulation. In the illustrative
`embodiment, the PWM override signal 64 is limited to
`approximately two volts, thereby limiting the duty cycle that
`can be commanded of the switches 12, 14 to approximately
`50% when the PWM override signal 64 governs the PWM
`operation, as shown in FIG. 4.
`Referring also to FIG. 5 additional features of the control
`circuit 30 of FIG. 1 are shown to include an oscillator 130
`adapted for coupling to a timing capacitor 132. The oscil(cid:173)
`lator 130 provides a clock signal 134 and the ramp voltage
`V ramp• The clock signal 134 determines the switching fre(cid:173)
`quency of the converter 10.
`Start-up circuitry is provided for disabling the gate drive
`circuit 34 until the input voltage VIN has risen to a satisfac(cid:173)
`tory level for regulated converter operation. More
`particularly, the input voltage VIN is coupled to a comparator
`136 which compares the input voltage VIN to a reference
`voltage V ref' The output of the comparator 136 is coupled to
`an AND gate 138, a second input to which is provided by the
`softstart/sleep signal 140 (FIG. 1). Recall that the softstart
`input to the voltage amplifier 54 (FIG. 1) e°'sures a con- 25
`trolled start-up by clamping the voltage amplifier output for
`a selected duration after start-up. The softstart input also
`governs a user controllable low power, or "sleep" mode of
`operation ..
`Sleep mode operation is commenced when the softstart/ 30
`sleep signal 140 is below approximately 0.5 V. At this level.
`the output of AND gate 138 (i.e., the SS enable signal) is
`low, thereby preventing the 2.5 V reference voltage regulator
`144 from providing 2.5 V, which in turn is used to generate
`the 2.0 V input to the voltage amplifier 54 (FIG. 1). The SS
`enable signal also enables the softstart feature.
`An inverter 142 provides an under voltage lockout feature
`to inhibit the gate drive signals 38, 40 until the input voltage
`VIN has reached a level necessary for regulated operation. To 40
`this end, the inverter output UVLO signal 143 is coupled to
`the gate drive circuit 34, as described below.
`A comparator 146 monitors the 2.5 V reference voltage by
`comparing the reference voltage to a fixed voltage of 2.2 V.
`If the 2.5 V reference voltage is greater than 2.2 V, then a 45
`REFGOOD output signal 147 of comparator 146 is low;
`whereas, if the 2.5 V reference voltage is less than 2.2 V,
`then the REFGOOD output signal 147 of comparator 146 is
`high. The REFGOOD signal 147 is also coupled to the gate
`drive circuit 34, as described below.
`Also shown in FIG. 5 is circuitry for implementing an
`optional standby, or low power output mode of operation in
`which the control circuit 30 disables the gate drive circuit 34
`and the oscillator 130, preserving both quiescent supply
`current consumption and gate drive charge current. Standby
`mode operation is initiated when the current through the
`output inductor 18 drops to a user programmable fraction of
`the specified full load output current. During standby mode
`operation the output current requirements are supplied by
`the output capacitor 20 (FIG. 1). Normal operation resumes 60
`once the output voltage V ouT decays by approximately 1 %
`of its nominal value.
`More particularly, the output current level at which the
`standby mode commences is set by resistors 150, 152. The
`voltage 162 at the interconnection of resistors 150, 152 is 65
`coupled to the non-inverting input of comparator 154, the
`inverting input to which receives the output current indica-
`
`8
`tive signal I,ense (FIG. 1). The output of comparator 154 is
`coupled to an input of AND gate 156, the output of which
`is coupled to a flip-flop 158. The second input to AND gate
`156 is provided by an SS done signal which indicates when
`the softstart feature has timed out. A low power signal 159
`is provided at the output of the flip-flop 158 to disable the
`gate drive circuit 34, as described below in conjunction with
`FIG. 6. The flip-flop 158 is reset by the output of a
`comparator 160, the inverting input to which receives the
`10 output voltage indicative signal V sense and the non-inverting
`input to which receives a 2.0 V reference voltage shifted by
`a fixed offset, such as twenty millivolts.
`Referring to FIG. 6, th