HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`
`TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
`
`DESCRIPTION
`The SC1405 is a Dual-MOSFET Driver with an internal
`Overlap Protection Circuit to prevent shoot-through
`from VIN to GND in the main switching and syn-
`chronous MOSFET’s. Each driver is capable of driving
`a 3000pF load in 20ns rise/fall time and has ULTRA-
`FAST propagation delay from input transition to the
`gate of the power FET’s. The Overlap Protection circuit
`ensures that the second FET does not turn on until the
`top FET source has reached a voltage low enough to
`prevent shoot-through. The delay between the bottom
`gate going low to the top gate transitioning to high is
`externally programmable via a capacitor for optimal
`reduction of switching losses at the operating fre-
`quency. The bottom FET may be disabled at light loads
`by keeping S_MOD low to trigger asynchronous opera-
`tion, thus saving the bottom FET’s gate drive current
`and inductor ripple current. An internal voltage refer-
`ence allows threshold adjustment for an Output Over-
`Voltage protection circuitry, independent of the PWM
`feedback loop. Under-Voltage-Lock-Out circuit is in-
`cluded to guarantee that both driver outputs are low
`when the 5V logic level is less than or equal to 4.4V
`(typ) at supply ramp up (4.35V at supply ramp down). A
`CMOS output provides status indication of the 5V sup-
`ply. A low enable input places the IC in stand-by mode
`thereby reducing supply current to less than 10µA.
`SC1405 is offered in a high pitch (.025” lead spacing)
`TSSOP package.
`
`PIN CONFIGURATION
`
`Top View
`
`FEATURES
`•= Fast rise and fall times (20ns typical with 3000pf
`load)
`•= 20ns max. Propagation delay (BG going low)
`•= Adaptive/programmable shoot-through protection
`•= Wide input voltage range (4.5-25V)
`•= Programmable delay between MOSFET’s
`•= Power saving asynchronous mode control
`•= Output overvoltage protection/overtemp shutdown
`•= Under-Voltage lock-out and power ready signal
`•= Less than 10µA stand-by current (EN=low)
`•= Power ready output signal
`APPLICATIONS
`•= High Density/Fast transient power supplies
`•= Motor Drives/Class-D amps
`•= High frequency (to 1.2 MHz) operation allows use
`of small inductors and low cost caps in place of
` electrolytics
`•= Portable computers
`
`ORDERING INFORMATION
`DEVICE(1)
`PACKAGE
`TEMP. RANGE (TJ)
`SC1405TS.TR TSSOP-14
`0 - 125°C
`Note:
`(1) Only available in tape and reel packaging. A reel
`contains 2500 devices.
`BLOCK DIAGRAM
`
`(14-Pin TSSOP)
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`1
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 1 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`Conditions
`
`Tamb = 25°C, TJ = 125°C
`Tcase = 25°C, TJ = 125°C
`
`August 31, 2000
`ABSOLUTE MAXIMUM RATINGS
`Parameter
`VCC Supply Voltage
`BST to PGND
`BST to DRN
`DRN to PGND
`OVP_S to PGND
`Input pin
`Continuous Power Dissipation
`
`Thermal Resistance Junction to Case
`
`Thermal Resistance Junction to Ambient
`
`Operating Temperature Range
`Storage Temperature Range
`Lead Temperature (Soldering) 10 sec
`
`Symbol
`VMAX5V
`VMAXBST-PGND
`VMAXBST-DRN
`VMAXDRN-PGN
`VMAXOVP_S-PGND
`CO
`Pd
`
`θJC
`θJA
`TJ
`TSTG
`TLEAD
`
`NOTE:
`(1) Specification refers to application circuit in Figure 1.
`
`ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS)
`Unless specified: -0 < θJ < 125°C; VCC = 5V; 4V < VBST < 26V
`PARAMETER
`SYMBOL
`CONDITIONS
`POWER SUPPLY
`VCC
`Supply Voltage
` Iq_stby
`Quiescent Current
`Quiescent Current, operating Iq_op
`PRDY
`High Level Output Voltage
`Low Level Output Voltage
`
`MIN
`
`TYP
`
`4.15
`
`4.5
`
`5
`
`1
`
`4.55
`0.1
`
`VCC
`EN = 0V
`VCC = 5V,CO=0V
`
`VOH
`VOL
`
`VCC = 4.6V, lload = 10mA
`VCC < UVLO threshold, lload =
`10µA
`
`Maximum Units
`7
`V
`30
`V
`7
`V
`25
`V
`10
`V
`-0.3 to 7.3
`V
`0.66
`W
`2.56
`40
`
`°C/W
`
`150
`
`°C/W
`
`0 to +125
`-65 to +150
`300
`
`°C
`°C
`°C
`
`MAX UNITS
`
`6.0
`10
`
`0.2
`
`0.05
`
`4.6
`
`1.5
`
`V
`µA
`ma
`
`V
`V
`
`V
`V
`
`V
`V
`V
`
`2
`
`DSPS_DR
`High Level Output Voltage
`Low Level Output Voltage
`UNDER-VOLTAGE LOCKOUT
`Start Threshold
`Hysteresis
`Logic Active Threshold
`
`VOH
`VOL
`
`VCC = 4.6V, Cload = 100pF
`VCC = 4.6V, Cload = 100pF
`
`VSTART
`VhysUVLO
`VACT
`
`EN is low
`
`4.15
`
`4.2
`
`4.4
`0.05
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 2 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont.
`PARAMETER
`SYMBOL
`CONDITIONS
`MIN
`TYP MAX UNITS
`OVERVOLTAGE PROTECTION
`Trip Threshold
`Hysteresis
`S_MOD
`High Level Input Voltage
`Low Level Input Voltage
`ENABLE
`High Level Input Voltage
`Low Level Input Voltage
`CO
`High Level Input Voltage
`Low Level Input Voltage
`THERMAL SHUTDOWN
`Over Temperature Trip Point
`Hysteresis
`HIGH-SIDE DRIVER
`Peak Output Current
`Output Resistance
`
`VTRIP
`VhysOVP
`
`VIH
`VIL
`
`VIH
`VIL
`
`VIH
`VIL
`
`TOTP
`THYST
`
`IPKH
`RsrcTG
`
`LOW-SIDE DRIVER
`Peak Output Current
`
`Output Resistance
`
`RsinkTG
`
`IPKL
`RsrcBG
`
`RsinkBG
`
`V
`V
`
`V
`V
`
`V
`V
`
`V
`V
`
`°C
`°C
`
`A
`
`Ω Ω
`
`A
`
`Ω Ω
`
`3
`
`1.145
`
`1.255
`
`1.2
`0.8
`
`2.0
`
`2.0
`
`2.0
`
`0.8
`
`0.8
`
`0.8
`
`165
`10
`
`1.5
`1.4
`
`1.4
`
`2
`
`2 2
`
`duty cycle < 2%, tpw < 100µs,
`TJ = 125°C, VBST - VDRN = 4.5V,
`VTG = 4.0V (src)+VDRN
`or VTG = 0.5V (sink)+VDRN
`
`duty cycle < 2%, tpw < 100µs,
`TJ = 125°C
`VV_5 = 4.6V, VBG = 4V (src),
`or VLOWDR = 0.5V (sink)
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 3 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont.
`PARAMETER
`SYMBOL
`CONDITIONS
`MIN
`TYP MAX UNITS
`AC OPERATING SPECIFICATIONS
`HIGH-SIDE DRIVER
`rise time
`
`16
`
`25
`
`ns
`
`trTG,
`
`CI = 3nF, VBST - VDRN = 4.6V,
`
`fall time
`
`tfTG
`
`CI = 3nF, VBST - VDRN = 4.6V,
`
`17
`
`35
`
`25
`
`20
`
`18
`
`45
`
`12
`
`27
`
`56
`
`40
`
`32
`
`29
`
`72
`
`20
`
`10
`10
`
`10
`
`500
`
`20
`
`10
`
`10
`
`1
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`us
`us
`
`µs
`
`µs
`
`ns
`
`ns
`
`ns
`
`µs
`
`4
`
`tpdhTG
`
`tpdlTG
`
`CI = 3nF, VBST - VDRN = 4.6V,
`C-delay=0
`CI = 3nF, VBST - VDRN = 4.6V,
`
`propagation delay time,
`TG going high
`propagation delay time,
`TG going low
`LOW-SIDE DRIVER
`rise time
`
`fall time
`
`propagation delay time
`BG going high
`progagation delay time
`BG going low
`UNDER-VOLTAGE LOCKOUT
`V_5 ramping up
`V_5 ramping down
`PRDY
`EN is transitioning from low to
`high
`
`trBG
`
`trBG
`
`tpdhBGHI
`
`tpdlBG
`
`tpdhUVLO
`tpdlUVLO
`
`tpdhPRDY
`
`CI = 3nF, VV_5 = 4.6V,
`
`CI = 3nF, VV_5 = 4.6V,
`
`CI = 3nF, VV_5 = 4.6V,
` DRN < 1V
`CI = 3nF, VV_5 = 4.6V,
`
`EN is High
`EN is High
`
`V_5 > UVLO threshold, Delay
`measured from EN > 2.0V to
`PRDY > 3.5V
`V_5 > UVLO threshold. Delay
`measured from EN < 0.8V tp
`PRDY < 10% of V_5
`
`CI = 100pf, V_5 = 4.6V,
`
`S_MOD goes high and
`BG goes high or S_MOD goes low
`S_MOD goes high and BG goes
`low
`
`EN is transitioning from high to
`low
`
`tpdhUVLO
`
`DSPS_DR
`rise/fall time
`
`trDSPS_DR,
`tfDSPS_DR
`tpdhDSPS_DR
`
`tpdlDSPS_DR
`
`propagation delay,
`DSPS_DR going high
`propagation delay
`DSPS_DR goes low
`OVERVOLTAGE PROTECTION
`propagation delay
`OVP_S going high
`Note:
`(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
`
`tpdhOVP_S
`
`V_5 = 4.6V, TJ = 125°C, OVP_S >
`1.2V to BG > 90% of V_5
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 4 of 13
`
`

`

`August 31, 2000
`PIN DESCRIPTION
`Pin #
`Pin Name
`1
`OVP_S
`
`2
`
`3
`4
`5
`
`6
`
`7
`
`8
`
`9
`10
`11
`
`12
`
`13
`14
`
`EN
`
`GND
`CO
`S_MOD
`
`DELAY_C
`
`PRDY
`
`VCC
`
`BG
`PGND
`DSPS_DR
`
`DRN
`
`TG
`BST
`
`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`Pin Function
`Overvoltage protection sense. External scaling resistors required to set
`protection threshold.
`When high, this pin enables the internal circuitry of the device. When
`low, TG, BG and PRDY are forced low and the supply current (5V) is
`less than 10µA.
`Logic GND.
`TTL-level input signal to the MOSFET drivers.
`When low, this signal forces BG to be low. When high, BG is not a
`function of this signal.
`Sets the additional propagation delay for BG going low to TG going high.
`Total propagation delay= 20ns + 1ns/pF.
`This pin indicates the status of 5V. When 5V is less than 4.4V(typ) this
`output is driven low. When 5V is greater than or equals to 4.4V(typ) this
`output is driven to 5V level. This output has a 10mA drive capability and
`10µA sink capability.
`+5V supply. A .22-1µF ceramic capacitor should be connected from 5V
`to PGND very close to this pin.
`Output drive for the synchronous MOSFET.
`Power ground. Connect to the synchronous FET power ground.
`Dynamic Set Point Switch Drive. TTL level output signal. When S_MOD
`is high, this pin follows the BG driver pin voltage.
`This pin connects to the junction of the switching and synchronous
`MOSFET’s. This pin can be subjected to a -2V minimum relative to
`PGND without affecting operation.
`Output gate drive for the switching (high-side) MOSFET.
`Bootstrap pin. A capacitor is connected between BST and DRN pins to
`develop the floating bootstrap voltage for the high-side MOSFET. The
`capacitor value is typically between 0.1µF and 1µF (ceramic).
`
`NOTE:
`(1) All logic level inputs and outputs are open collector TTL compatible.
`
`PIN CONFIGURATION
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`5
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 5 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`
`APPLICATION CIRCUIT
`
`Typical Distributed Power Supply
`
`MTB75N03
`75A,30V
`
`MTB75N03
`75A,30V
`
`+
`
`+
`
`+
`
`+
`
`+
`
`+
`
`.22uF
`
`2.2
`
`2.2
`
`14
`
`13
`
`12
`
`9 1
`
`1
`10
`
`Over-Voltage Sense
`
`Figure 1.
`
`Figure 2.
`
`D1
`
`1N5819
`
`Vcc
`GND
`
`BST
`
`TG
`
`DRN
`
`BG
`
`PRDY
`EN
`CO
`DELAY_C
`OVP_S
`DSPS_DR
`S_MOD PGND
`
`SC1405
`
`8
`
`7
`
`3 2 1
`
`4
`
`6 5
`
`INPUT POWER
`
`+5V
`
`10uF,6.3V
`
`+
`
`.1uF
`
`<<
`
`>>
`
`P_READY
`
`PWM IN
`(20KHz-1MHz)
`
`<<
`
`DSPS_DR
`
`47pF
`
`<<< Output Feedback to PWM
` Controller
`
`TIMING DIAGRAM
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`6
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 6 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`1
`
`of
`
`1
`
`Sheet
`
`Thursday, June 10, 1999
`
`NC
`Rev
`
`Document Number
`
`PLATFORM SYNCHRONOUS 40A CONVERTER
`
`August 31, 2000
`
`APPLICATION EVALUATION BOARD SCHEMATIC
`SC1405/SC1144 Evaluation Board.
`4-Phase synchronous, Freq.=1MHz
`
`1000uf,6.3
`C51
`
`1000uf,6.3
`C39
`
`C38
`22u,10V
`
`C34
`22u,10V
`
`C33
`22u,10V
`
`C30
`22u,10V
`
`C29
`22u,10V
`
`C25
`22u,10V
`
`C24
`22u,10V
`
`C21
`22u,10V
`
`C20
`22u,10V
`
`C17
`22u,10V
`
`C15
`22u,10V
`
`C10
`22u,10V
`
`C6
`22u,10V
`
`C1
`22u,10V
`
`30BQ015
`
`FDB7030
`
`L7
`870nh
`
`D8
`
`Q8
`
`FDP6035
`
`Q7
`
`L5
`870nh
`
`30BQ015
`
`FDP6035
`
`D7
`
`Q6
`
`FDP6035
`
`Q5
`
`VOUT
`
`L3
`870nh
`
`30BQ015
`
`FDB7030
`
`D6
`
`Q4
`
`FDP6035
`
`Q3
`
`30BQ015
`
`FDB7030
`
`L1
`870nh
`
`D5
`
`Q2
`
`FDP6035
`
`Q1
`
`23
`
`0
`
`0R
`
`R17
`
`C36
`10u,16V
`
`16
`
`14
`
`0R
`
`0R
`
`C28
`10u,16V
`
`12
`
`0R
`
`R10
`
`0
`
`C19
`10u,16V
`
`2
`0R
`
`3
`0R
`
`C49
`
`.1u
`
`C35
`
`.1u
`
`C27
`
`.1u
`
`C18
`
`.1u
`
`Date:
`
`B
`
`Size
`
`Title
`
`R27=0,R26=OPENtodisableOVP_S.
`POINT.
`C48SETSTHETIMECONSTANT.
`R26ANDR27SETTHEOVERVOLTAGETRIP
`
`.1uC40
`
`C31
`
`.1u
`
`C22
`
`.1u
`
`C9
`
`.1u
`
`4.7
`
`R31
`
`4.7
`
`R30
`
`4.7
`
`R29
`
`4.7
`
`R28
`
`.1u
`.1u
`.1u
`.1u
`
`C5
`C4
`C3
`C2
`
`SS12
`
`SS12
`
`SS12
`
`SS12
`
`.1uC50
`
`D4
`
`D3
`
`D2
`
`D1
`
`10
`
`1
`9 1
`
`12
`
`13
`
`14
`
`10
`
`1
`9 1
`
`12
`
`13
`
`14
`
`10
`
`1
`9 1
`
`12
`
`13
`
`14
`
`10
`
`1
`9 1
`
`12
`
`13
`
`14
`
`BG
`
`DRN
`
`TG
`
`BST
`
`BG
`
`DRN
`
`TG
`
`BST
`
`OVP_S
`DELAY_C
`CO
`EN
`PRDY
`
`GND
`Vcc
`
`SC1405
`
`U4
`
`R26
`TBD
`
`*
`
`SC1405
`
`BG
`
`DRN
`
`TG
`
`BST
`
`SC1405
`
`U5
`
`S_MODPGND
`DSPS_DR
`
`SC1405
`
`U3
`
`S_MODPGND
`DSPS_DR
`
`BG
`
`DRN
`
`TG
`
`BST
`
`U1
`
`S_MODPGND
`DSPS_DR
`
`OVP_S
`DELAY_C
`CO
`EN
`PRDY
`
`GND
`Vcc
`
`S_MODPGND
`DSPS_DR
`
`OVP_S
`DELAY_C
`CO
`EN
`PRDY
`
`GND
`Vcc
`
`OVP_S
`DELAY_C
`CO
`EN
`PRDY
`
`GND
`Vcc
`
`
`
`8 7 43 2 16 5
`
`
`
`
`
`
`
`
`
`8 7 43 2 16 5
`
`
`
`
`
`
`
`
`
`8 7 43 2 16 5
`
`
`
`
`
`
`
`
`
`8 7 43 2 16 5
`
`
`
`
`
`
`
`*
`
`C48
`
`.01
`
`R27
`TBD
`
`EN
`
`C44
`47pf
`
`47pf
`
`C37
`
`C26
`47pf
`
`C16
`47pf
`
`.1u
`
`C14
`
`.1u
`
`C23
`
`.1u
`
`C32
`
`.1u
`
`C41
`
`2.2
`
`R25
`
`C47
`
`.1u
`
`R21
`
`10
`
`C43
`
`.022
`
`R20
`2.2k
`
`R24
`300k
`
`C42
`
`.01u
`
`VOUT
`
`R15
`3k
`
`13
`
`14
`
`15
`
`16
`
`FB
`
`FBG
`
`EN
`
`17
`
`R13
`22
`
`R11
`22
`
`R8
`22
`
`R9
`22
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`12V
`
`32
`
`0R
`
`CANBEDIRECTLYCONTROLLEDBYSEPARATINGTHETWOENABLES.
`DISABLEDTOGETHERWITHSC1144.
`BYJUMPERINGJMP1,ALLSC1405'SAREENABLEDAND
`
`THREEOFTHESC1405'S
`
`ENSYN
`
`R22
`15K
`
`12
`
`11
`
`10
`
`C46
`
`.001
`
`C45
`
`.01
`
`19
`
`0R
`
`R18
`3.92K
`
`U2
`SC1144-SOIC
`
`Comp
`
`Bgout
`
`Enable
`
`GND
`
`Drv2
`
`Drv0
`
`Drv1
`
`Drv3
`
`Outv
`
`OC-
`
`OC+
`
`Vid4
`
`Vid3
`
`Vid2
`
`Vid1
`
`Vid0
`
`Rref
`
`Extclk
`
`Clksel
`
`Divsel
`
`5v
`
`1
`
`2 3
`
`4
`
`5 6
`
`7
`
`8
`
`9
`
`10K
`
`10K
`
`10K
`
`10K
`
`R7
`
`R6
`
`R5
`
`R4
`
`SMOD
`
`R33
`10K
`
`R1
`10
`
`Long PCB Trace
`
`+5V power
`
`JMP1
`
`Vout/Clk switch
`
`EN
`
`12345678
`
`9
`
`16
`15
`14
`13
`12
`11
`10
`
`S1
`
`INPUT
`
`10uf,6.3v
`
`C7
`
`C8
`
`.1u
`
`C13
`
`C12
`
`C11
`
`330UF,16V
`
`1u,16V
`
`1u,16V
`
`123456
`
`J1
`
`+12V
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`Figure 3
`
`7
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 7 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`BILL OF MATERIAL
`Item Qty Reference
`1
`14 C1,C6,C10,C15,C17,C20,C21,C24,C25,C29,C30,C33,C34,C38
`
`2
`
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`
`14
`15
`16
`
`17
`
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`
`19 C2,C3,C4,C5,C7,C9,C14,C18,C22,C23,C27,C31,C32,C35,C40,
`C41,C47,C49,C50
`1 C8
`2 C11,C12
`1 C13
`4 C16,C26,C37,C44
`3 C19,C28,C36
`2 C39,C51
`3 C42,C45,C46
`1 C43
`1 C46
`4 D1,D2,D3,D4
`4 D5,D6,D7,D8
`
`2
`1
`4
`
`JMP1,JMP2
`J1
`L1,L3,L5,L7
`
`5 Q1,Q3,Q5,Q6,Q7
`
`3 Q2,Q4,Q8
`2 R1,R21
`10 R2,R3,R10,R12,R14,R16,R17,R19,R23,R32
`5 R4,R5,R6,R7,R33
`4 R8,R9,R11,R13
`1 R15
`1 R18
`1 R20
`1 R22
`1 R24
`1 R25
`2 R26,R27
`4 R28,R29,R30,R31
`1
`S1
`4 U1,U3,U4,U5
`1 U2
`
` Value
`22u, 10V
`
`.1uF
`
`Manufacturer
`Murata
`(GRM235Y5V226Z010)
`any
`
`10uF, 6.3V
`1uF, 16V
`330uf, 16V
`44pF
`10uF, 16V
`1000uF, 6.3V
`.01uf
`.022
`.001
`SS12
`30BQ015
`
`Jumper
`Input
`.87uh
`
`FDP6035
`
`IR7811
`FDB7030
`10
`0
`10k
`22
`3k
`3.92k
`2.2k
`15K
`300K
`2.2
`TBD
`4.7
`Vout/Clk switch
`SC1405
`SC1144CSW
`
`any
`any
`Sanyo
`any
`any
`any
`any
`Avx, any
`Avx, any
`General Instruments
`Int. Rectifier
`(310) 252-7099
`
`Falco, P/N: TO2509
`(305) 662-9076
`Fairchild Semi.
`(408) 822-2000
`Int. Rectifier
`Fairchild Semi.
`any
`any
`any
`any
`any
`any
`any
`any
`any
`any
`any
`any
`Digikey
`Semtech, (805) 499-2111
`Semtech, (805) 499-2111
`8
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 8 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`APPLICATION INFORMATION
`
`SC1405 is a high speed, smart dual MOSFET driver.
`It is designed to drive Low Rds_On power MOSFET’s
`with ultra-low rise/fall times and propagation delays.
`As the switching frequencies of PWM controllers is in-
`creased to reduce power supply and Class-D amplifier
`volume and cost, fast rise and fall times are necessary
`to minimize switching losses (TOP MOSFET) and re-
`duce Dead-time (BOTTOM MOSFET). While Low
`Rds_On MOSFET’s present a power saving in I2R
`losses, the MOSFET’s die area is larger and thus the
`effective input capacitance of the MOSFET is in-
`creased. Often a 50% decrease in Rds_On more than
`doubles the effective input gate charge, which must be
`supplied by the driver. The Rds_On power savings
`can be offset by the switching and dead-time losses
`with a sub-optimum driver. While discrete solution can
`achieve reasonable drive capability, implementing
`shoot-through, programmable delay and other house-
`keeping functions necessary for safe operation can be-
`come cumbersome and costly. The SC1405 family of
`parts presents a total solution for the high-speed, high
`power density applications. Wide input supply range of
`4.5V-25V allows use in battery powered applications,
`new high voltage, distributed power servers as well as
`Class-D amplifiers.
`
`THEORY OF OPERATION
`
`The control input (CO) to the SC1405 is typically sup-
`plied by a PWM controller that regulates the power
`supply output. (See Application Evaluation Schematic,
`Figure 3). The timing diagram demonstrates the se-
`quence of events by which the top and bottom drive
`signals are applied. The shoot-through protection is
`implemented by holding the bottom FET off until the
`voltage at the phase node (intersection of top FET
`source, the output inductor and the bottom FET drain)
`has dropped below 1V. This assures that the top FET
`has turned off and that a direct current path does not
`exist between the input supply and ground, a condition
`which both the top and bottom FET’s are on momen-
`tarily. The top FET is also prevented from turning on
`until the bottom FET is off. This time is internally set to
`20ns (typical) and may be increased by adding a ca-
`pacitor to the C-Delay pin. The delay is approximately
`1ns/pf in addition to the internal 20ns delay. The exter-
`nal capacitor may be needed if multiple High input ca-
`pacitance MOSFET’s are used in parallel and the fall
`time is substantially greater than 20ns.
`
`the parallel Schottky or the bottom FET body diode will
`have to conduct during dead-time.
`
`LAYOUT GUIDELINES
`
`As with any high speed , high current circuit, proper
`layout is critical in achieving optimum performance of
`the SC1405. The Evaluation board schematic (Refer
`to figure 3) shows a four-phase synchronous design
`with all surface mountable components.
`While components connecting to C-Delay, OVP_S,
`EN,S-MOD, DSPS_DR and PRDY are relatively non-
`critical, tight placement and short,wide traces must be
`used in layout of The Drives, DRN, and especially
`PGND pin. The top gate driver supply voltage is pro-
`vided by bootstrapping the +5V supply and adding it
`the phase node voltage (DRN). Since the bootstrap
`capacitor supplies the charge to the TOP gate, it must
`be less than .5” away from the SC1405. Ceramic X7R
`capacitors are a good choice for supply bypassing near
`the chip. The Vcc pin capacitor must also be less than
`.5” away from the SC1405. The ground node of this
`capacitor, the SC1405 PGND pin and the Source of
`the bottom FET must be very close to each other,
`preferably with common PCB copper land with multiple
`vias to the ground plane (if used). The parallel Schot-
`tky must be physically next to the Bottom FETS Drain
`and source. Any trace or lead inductance in these con-
`nections will drive current way from the Schottky and
`allow it to flow through the FET’s Body diode, thus re-
`ducing efficiency.
`
`PREVENTING INADVERTENT BOTTOM FET
`TURN-ON
`
`At high input voltages, (12V and greater) a fast turn-on
`of the top FET creates a positive going spike on the
`Bottom FET’s gate through the Miller capacitance,
`Crss of the bottom FET. The voltage appearing on the
`gate due to this spike is:
`
`Vspike=Vin*crss/(Crass+ciss)
`
`Where Ciss is the input gate capacitance of the bottom
`FET. This is assuming that the impedance of the drive
`path is too high compared to the instantaneous
`impedance of the capacitors. (since dV/dT and thus
`the effective frequency is very high). If the BG pin of
`the SC1405 is very close to the bottom FET, Vspike
`will be reduced depending on trace inductance, rate if
`rise of current,etc.
`
`It must be noted that increasing the dead-time by high
`values of C-Delay capacitor will reduce efficiency since
`
`While not shown in Figure 3, a capacitor may be added
`from the gate of the Bottom FET to its source, prefer-
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`9
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 9 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`ably less than .1” away. This capacitor will be added to
`Ciss in the above equation to reduce the effective spike
`voltage, Vspike.
`The selection of the bottom MOSFET must be done with
`attention paid to the Crss/Ciss ratio. A low ratio reduces
`the Miller feedback and thus reduces Vspike. Also
`MOSFETs with higher Turn-on threshold voltages will
`conduct at a higher voltage and will not turn on during
`the spike. The MOSFET shown in the schematic (figure
`3) has a 2 volt threshold and will require approximately 5
`volts Vgs to be conducting, thus reducing the possibility
`of shoot-through. A zero ohm bottom FET gate resistor
`will obviously help keeping the gate voltage low.
`Ultimately, slowing down the top FET by adding gate re-
`sistance will reduce di/dt which will in turn make the ef-
`fective impedance of the capacitors higher, thus allowing
`the BG driver to hold the bottom gate voltage low. It
`does this at the expense of increased switching times (
`and switching losses) for the top FET.
`
`RINGING ON THE PHASE NODE
`
`The top MOSFET source must be close to the bottom
`MOSFET drain to prevent ringing and the possibility of
`the phase node going negative. This frequency is de-
`termined by:
`
`Fring =1/(2¶* Sqrt(Lst*Coss))
`
` Where:
`
` Lst = The effective stray inductance of the top FET
`added to trace inductance of the connection between top
`FET’s source and the bottom FET’s drain added to the
`trace resistance of the bottom FET’s ground connection.
`Coss=Drain to source capacitance of bottom FET. If
`there is a Schottky used, the capacitance of the Schottky
`is added to the value.
`
`Although this ringing does not pose any power losses
`due to a fairly high Q, it could cause the phase node to
`go too far negative, thus causing improper operation,
`double pulsing or at worst driver damage. This ringing is
`also an EMI nuisance due to its high resonant frequency.
`Adding a capacitor, typically 1000-2000pf, in parallel with
`Coss can often eliminate the EMI issue. If double puls-
`ing is caused due to excessive ringing, placing 4.7-10
`ohm resistor between the phase node and the DRN pin
`of the SC1405 should eliminate the double pulsing.
`Proper layout will guarantee minimum ringing and elimi-
`nate the need for external components. Use of SO-8 or
`other surface mount MOSFETs will reduce lead induc-
`tance as well as radiated EMI.
`
`ASYNCHRONOUS OPERATION
`
`The SC1405 can be configured to operate in Asyn-
`chronous mode by pulling S-MOD to logic LOW, thus
`disabling the bottom FET drive. This has the effect of
`saving power at light loads since the bottom FET’s
`gate capacitance does not have to charged at the
`switching frequency. There can be a significant sav-
`ings since the bottom driver can supply up to 2A pulses
`to the FET at the switching frequency. There is an ad-
`ditional efficiency benefit to operating in asynchronous
`mode. When operating in synchronous mode, the in-
`ductor current can go negative and flow in reverse di-
`rection when the bottom FET is on and the DC load is
`less than 1/2 inductor ripple current. At that point, the
`inductor core and wire losses, depending on the mag-
`nitude of the ripple current, can be quite significant.
`Operating in asynchronous mode at light loads effec-
`tively only charges the inductor by as much as needed
`to supply the load current, since the inductor never
`completely discharges at light loads. DC regulation
`can be an issue depending on the type of controller
`used and minimum load required to maintain regula-
`tion. If there are no Schottkys used in parallel with bot-
`tom FET, the FET’s body diode will need to conduct in
`asynchronous mode. The high voltage drop of this
`diode must be considered when determining the crite-
`ria for this mode of operation.
`
`DSPS DR
`
`This pin produces an output which is a logical duplicate
`of the bottom FET’s gate drive, if S-MOD is held LOW.
`
`OVP_S/OVER TEMP SHUTDOWN
`
`Output over-voltage protection may be implemented on
`the SC1405 independent of the PWM controller . A
`voltage divider from the output is compared with the
`internal bandgap voltage of 1.2V (typical). Upon ex-
`ceeding this voltage, the overvoltage comparator dis-
`ables the top FET, while turning on the bottom FET to
`allow discharge of the output capacitors excessive volt-
`age through the output inductor. There should be suffi-
`cient RC time constant as well as voltage headroom on
`the OVP_S pin to assure it does not enter overvoltage
`mode inadvertently. The SC1405 will shutdown if its Tj
`exceeds 165 °C.
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`10
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 10 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`Performance diagrams, Application Evaluation Board. (Fig.3)
`
`Figure 4-Timing diagram:
`
`Ch1:CO input
`
`Ch2:TG drive
`
`Ch3:BG non-overlap drive
`
`Ch4:phase node
`Iout=20A (10A/phase)
`Refer to Eval. Schematic
` (fig.3)
`
`Figure 5-Timing diagram:
`Rise/Fall times
`
`Ch1:TG drive
`
`Ch2:BG drive
`
`Cursor:TpdhTG
`
`Iout=20A (10A/phase)
`Refer to Eval. Schematic
` (fig.3)
`
`Vin=10V, Vout=2V TOP FET IR7811, Bottom
` FET IR7030(L) Qg(tot)=35nc
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`11
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 11 of 13
`
`

`

`HIGH SPEED SYNCHRONOUS POWER
`MOSFET SMART DRIVER
`
`SC1405
`
`August 31, 2000
`
`OUTLINE DRAWING TSSOP-14
`
`ECN00-1259
`
`© 2000 SEMTECH CORP.
`
`652 MITCHELL ROAD NEWBURY PARK CA 91320
`
`12
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 12 of 13
`
`

`

`This datasheet has been download from:
`
`www.datasheetcatalog.com
`
`Datasheets for electronics components.
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1042
`Page 13 of 13
`
`