Preliminary Information
`
`TM
`
`AMD-756
`Peripheral Bus Controller
`Data Sheet
`
`Publication # 22548
`Issue Date: August 1999
`
`Rev: B
`
`
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 1 of 368
`
`

`

`Preliminary Information
`
`© 1999 Advanced Micro Devices, Inc. All rights reserved.
`
`The contents of this document are provided in connection with Advanced Micro
`Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with
`respect to the accuracy or completeness of the contents of this publication and
`reserves the right to make changes to specifications and product descriptions at any
`time without notice. No license, whether express, implied, arising by estoppel or oth-
`erwise, to any intellectual property rights is granted by this publication. Except as
`set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability
`whatsoever, and disclaims any express or implied warranty, relating to its products
`including, but not limited to, the implied warranty of merchantability, fitness for a
`particular purpose, or infringement of any intellectual property right.
`
`AMD’s products are not designed, intended, authorized or warranted for use as com-
`ponents in systems intended for surgical implant into the body, or in other applica-
`tions intended to support or sustain life, or in any other application in which the
`failure of AMD’s product could create a situation where personal injury, death, or
`severe property or environmental damage may occur. AMD reserves the right to dis-
`continue or make changes to its products at any time without notice.
`
`Trademarks
`
`AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-750, AMD-751, and AMD-756 are trademarks
`of Advanced Micro Devices, Inc.
`
`Microsoft and Windows are registered trademarks of Microsoft Corporation.
`
`Other product names used in this publication are for identification purposes only and may be trademarks of their
`respective companies.
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 2 of 368
`
`

`

`22548B/0—August 1999
`
`Contents
`
`1
`
`Features
`
`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`1
`
`1.1
`
`1.2
`
`PCI-to-ISA Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
`
`Enhanced IDE Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
`
`1.3 Universal Serial Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . 4
`
`1.4
`
`1.5
`
`Plug-n-Play Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
`
`Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
`
`2
`
`Overview
`
`7
`
`2.1
`
`PCI-to-ISA Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
`
`2.1.1 PCI Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
`2.1.2 PCI Bus Target Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
`
`ISA Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
`
`EIDE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
`
`2.2
`
`2.3
`
`2.4 Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`
`2.5
`
`Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`
`3
`
`4
`
`Ordering Information
`
`Signal Descriptions
`
`15
`
`17
`
`4.1
`
`4.2
`
`Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`
`Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
`
`4.2.1 A20M# (Processor A20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 18
`4.2.2 CPURST# (Processor Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
`4.2.3 FERR# (Floating Point Error) . . . . . . . . . . . . . . . . . . . . . . . . 18
`4.2.4 IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . . 19
`4.2.5 INIT# (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`4.2.6 INTR (Processor Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`4.2.7 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . 20
`
`Table of Contents
`
`iii
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 3 of 368
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`

`

`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`22548B/0—August 1999
`
`4.2.8 SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . . 20
`4.2.9 PICCLK (Interrupt Message Bus Clock) . . . . . . . . . . . . . . . . 20
`4.2.10 PICD0# and PICD1# (Interrupt Message Data Bits) . . . . . . . 20
`4.2.11 WSC# (Write Snoop Complete) . . . . . . . . . . . . . . . . . . . . . . . . 21
`4.2.12 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
`
`4.3
`
`PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
`
`4.3.1 AD[31:0] (PCI Address/Data Bus) Summary . . . . . . . . . . . . . 22
`4.3.2 C/BE[3:0]# (PCI Command/Byte Enable) . . . . . . . . . . . . . . . . . 22
`4.3.3 DEVSEL# (PCI Bus Device Select) . . . . . . . . . . . . . . . . . . . . . . 23
`4.3.4 FRAME# (PCI Bus Cycle Frame) . . . . . . . . . . . . . . . . . . . . . . . 24
`4.3.5 IDSEL (PCI Initialization Device Select) . . . . . . . . . . . . . . . . 24
`4.3.6 IRDY# (PCI Bus Initiator Ready) . . . . . . . . . . . . . . . . . . . . . . . 24
`4.3.7 PAR (PCI Bus Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`4.3.8 PCIRST# (PCI Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`4.3.9 PCLK (PCI Bus Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`4.3.10 PGNT# (PCI Grant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`4.3.11 PIRQ[D:A]# (PCI Interrupt Requests) . . . . . . . . . . . . . . . . . . . 27
`4.3.12 PREQ# (PCI Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`4.3.13 SERR# (System Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`4.3.14 STOP# (Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`4.3.15 TRDY# (PCI Target Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`
`4.4
`
`ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`
`4.4.1 AEN (Address Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`4.4.2 BALE (Bus Address Latch Enable) . . . . . . . . . . . . . . . . . . . . . 29
`4.4.3 BCLK (Bus Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`4.4.4 DACK[7:5]#, DACK[3:0]# (DMA Acknowledge) . . . . . . . . . . 30
`4.4.5 DRQ[7:5], DRQ[3:0] (DMA Request) . . . . . . . . . . . . . . . . . . . 30
`4.4.6 IOCHCK# (I/O Channel Check) . . . . . . . . . . . . . . . . . . . . . . . 30
`4.4.7 IOCHRDY (I/O Channel Ready) . . . . . . . . . . . . . . . . . . . . . . . 31
`4.4.8 IOCS16# (16-Bit I/O Chip Select) . . . . . . . . . . . . . . . . . . . . . . 31
`4.4.9 IOR# (I/O Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`4.4.10 IOW# (I/O Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`4.4.11 IRQ15, IRQ14, IRQ[12:9], IRQ[7:3] (Interrupt Requests) . . 32
`4.4.12 NMPIRQ (Native Mode Primary IDE Port IRQ) . . . . . . . . . . 33
`4.4.13 NMSIRQ (Native Mode Secondary IDE Port IRQ) . . . . . . . . 33
`4.4.14 LA[23:17] (Unlatched Address) . . . . . . . . . . . . . . . . . . . . . . . 33
`4.4.15 MASTER# (ISA Master Cycle Indicator) . . . . . . . . . . . . . . . . 33
`4.4.16 MEMCS16# (16-Bit Memory Chip Select) . . . . . . . . . . . . . . . 34
`4.4.17 MEMR# (Memory Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
`4.4.18 MEMW# (Memory Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
`4.4.19 OSC (Oscillator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`4.4.20 REFRESH# (Refresh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`4.4.21 ROM_KBCS# (ROM and Keyboard Chip Select) . . . . . . . . . 35
`4.4.22 RSTDRV (Reset Drive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`
`iv
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`Table of Contents
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 4 of 368
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`

`

`22548B/0—August 1999
`
`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`4.4.23 SA[16:0] (System Address Bus) . . . . . . . . . . . . . . . . . . . . . . . 36
`4.4.24 SBHE# (System Byte High Enable) . . . . . . . . . . . . . . . . . . . . 36
`4.4.25 SD[15:0] (ISA System Data) . . . . . . . . . . . . . . . . . . . . . . . . . . 36
`4.4.26 SMEMR# (Standard Memory Read) . . . . . . . . . . . . . . . . . . . . 36
`4.4.27 SMEMW# (Standard Memory Write) . . . . . . . . . . . . . . . . . . . 37
`4.4.28 SPKR (Speaker) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
`4.4.29 TC (Terminal Count) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
`
`4.5 Ultra DMA Enhanced IDE Interface . . . . . . . . . . . . . . . . . . . 38
`
`4.5.1 DADDRP[2:0] (Primary IDE Address) . . . . . . . . . . . . . . . . . . 38
`4.5.2 DADDRS[2:0] (Secondary IDE Address) . . . . . . . . . . . . . . . . 38
`4.5.3 DCS1P# (Primary Port Chip Select) . . . . . . . . . . . . . . . . . . . . 38
`4.5.4 DCS1S# (Secondary Port Chip Select) . . . . . . . . . . . . . . . . . . 39
`4.5.5 DCS3P# (Primary Port Chip Select) . . . . . . . . . . . . . . . . . . . . 39
`4.5.6 DCS3S# (Secondary Port Chip Select) . . . . . . . . . . . . . . . . . . 39
`4.5.7 DDATAP[15:0] (Primary IDE Data Bus) . . . . . . . . . . . . . . . . 39
`4.5.8 DDATAS[15:0] (Secondary IDE Data Bus) . . . . . . . . . . . . . . 40
`4.5.9 DDACKP# (Primary IDE DMA Acknowledge) . . . . . . . . . . . 40
`4.5.10 DDACKS# (Secondary IDE DMA Acknowledge) . . . . . . . . . 41
`4.5.11 DDMARDYP# (Primary Device DMA Ready,
`Ultra DMA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
`4.5.12 DDMARDYS# (Secondary Device DMA Ready,
`UltraDMAMode) 41
`4.5.13 DDRQP (Primary IDE DMA Request) . . . . . . . . . . . . . . . . . . 41
`4.5.14 DDRQS (Secondary IDE DMA Request) . . . . . . . . . . . . . . . . 42
`4.5.15 DIORP# (Primary I/O Read) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
`4.5.16 DIORS# (Secondary I/O Read) . . . . . . . . . . . . . . . . . . . . . . . . 42
`4.5.17 DIOWP# (Primary I/O Write) . . . . . . . . . . . . . . . . . . . . . . . . . 42
`4.5.18 DIOWS# (Secondary I/O Write) . . . . . . . . . . . . . . . . . . . . . . . 43
`4.5.19 DRDYP# (Primary Device Ready) . . . . . . . . . . . . . . . . . . . . . 43
`4.5.20 DRDYS# (Secondary Device Ready) . . . . . . . . . . . . . . . . . . . 43
`4.5.21 DSTROBEP (Primary Device Strobe, Ultra DMA Mode) . . . 44
`4.5.22 DSTROBES (Secondary Device Strobe, Ultra DMA Mode) . 44
`4.5.23 HDMARDYP# (Primary Host DMA Ready,
`Ultra DMA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
`4.5.24 HDMARDYS# (Secondary Host DMA Ready,
`Ultra DMA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
`4.5.25 HSTROBEP (Primary Host Strobe, Ultra DMA Mode) . . . . 45
`4.5.26 HSTROBES (Secondary Host Strobe, Ultra DMA Mode) . . 45
`4.5.27 STOPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
`4.5.28 STOPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
`
`4.6
`
`System Management Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
`
`4.6.1 C32KHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
`4.6.2 CACHE_ZZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
`4.6.3 PNPIRQ1 (Plug and Play Interrupt Request 1) . . . . . . . . . . 47
`
`Table of Contents
`
`v
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 5 of 368
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`

`

`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`22548B/0—August 1999
`
`4.6.4 CPUSLEEP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
`4.6.5 PNPCS0# (Plug and Play Chip Select 0) . . . . . . . . . . . . . . . . 48
`4.6.6 CPUSTOP# (Processor Clock Stop) . . . . . . . . . . . . . . . . . . . . 48
`4.6.7 PNPCS1# (Plug and Play Chip Select 1) . . . . . . . . . . . . . . . . 48
`4.6.8 DCSTOP# (DRAM Controller Stop) . . . . . . . . . . . . . . . . . . . . 48
`4.6.9 PNPIRQ2 (Plug and Play Interrupt Request 2) . . . . . . . . . . 49
`4.6.10 EXTSMI# (External SMI Input) . . . . . . . . . . . . . . . . . . . . . . . 49
`4.6.11 BMREQ# (PCI Bus Master Request) . . . . . . . . . . . . . . . . . . . 49
`4.6.12 FLAGRD# (Flag Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
`4.6.13 PNPDAK# (Plug and Play DMA Acknowledge) . . . . . . . . . . 50
`4.6.14 FLAGWR (Flag Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
`4.6.15 PNPDRQ (Plug and Play DMA Request) . . . . . . . . . . . . . . . . 50
`4.6.16 INTIRQ8# (Internal Real Time Clock Interrupt) . . . . . . . . . 51
`4.6.17 SQWAVE (Square Wave Clock) . . . . . . . . . . . . . . . . . . . . . . . 51
`4.6.18 PCISTOP# (PCI Bus Clock Stop) . . . . . . . . . . . . . . . . . . . . . . . 51
`4.6.19 PNPIRQ0 (Plug and Play Interrupt Request 0) . . . . . . . . . . 51
`4.6.20 PME# (Power Management Interrupt) . . . . . . . . . . . . . . . . . 52
`4.6.21 PWRBTN# (Power Button) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
`4.6.22 PWRGD (Power Good) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
`4.6.23 PWRON# (Main Power On) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
`4.6.24 RI# (Ring Indicator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
`4.6.25 SERIRQ (Serial IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
`4.6.26 MSIRQ (Mouse Interrupt Request) . . . . . . . . . . . . . . . . . . . . 53
`4.6.27 SMBALERT# (SMBus Alert) . . . . . . . . . . . . . . . . . . . . . . . . . . 54
`4.6.28 SMBUSC (System Management Bus Clock) . . . . . . . . . . . . . 54
`4.6.29 SMBUSD (System Management Bus Data) . . . . . . . . . . . . . . 54
`4.6.30 SLPBTN# (Sleep Button) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
`4.6.31 EXTIRQ8# (Real Time Clock Interrupt) . . . . . . . . . . . . . . . . 55
`4.6.32 SUSPEND# (Processor Suspend) . . . . . . . . . . . . . . . . . . . . . . 55
`4.6.33 THERM# (Thermal Warning Detect) . . . . . . . . . . . . . . . . . . . 55
`
`4.7 Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . 56
`
`4.7.1 USBCLK (Universal Serial Bus Clock) . . . . . . . . . . . . . . . . . . 56
`4.7.2 USBP[3:0] (USB Port [3:0] Data Positive) . . . . . . . . . . . . . . . 56
`4.7.3 USBN[3:0] (USB Port [3:0] Data Negative) . . . . . . . . . . . . . . 56
`4.7.4 USBOC0# (USB Over-Current Detect 0) . . . . . . . . . . . . . . . . 56
`4.7.5 USBOC1# (USB Over-Current Detect 1) . . . . . . . . . . . . . . . . 57
`
`4.8
`
`Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`
`4.8.1 KBCK (Keyboard Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`4.8.2 KA20G (Keyboard Gate A20) . . . . . . . . . . . . . . . . . . . . . . . . . 58
`4.8.3 KBDT (Keyboard Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`4.8.4 KBRC# (Keyboard Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`4.8.5 KEYLOCK (Keyboard Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`4.8.6 DBRDY (Debug Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`4.8.7 MSCK (Mouse Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`
`vi
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`Table of Contents
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 6 of 368
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`

`

`22548B/0—August 1999
`
`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`4.8.8 MSDT (Mouse Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`4.8.9 EKIRQ1 (External Keyboard Controller IRQ1) . . . . . . . . . . 59
`4.8.10 EKIRQ12 (External Keyboard Controller IRQ12) . . . . . . . . 60
`
`4.9
`
`Internal Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`
`4.9.1 RTCX_IN (Crystal/Oscillator Input) . . . . . . . . . . . . . . . . . . . . 61
`4.9.2 RTCX_OUT (Crystal/Oscillator Output) . . . . . . . . . . . . . . . . 61
`
`4.10 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`
`4.10.1 GND (Power Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`4.10.2 GND_USB (USB Differential Output Ground) . . . . . . . . . . . 62
`4.10.3 VDD3 (Power Supply for the Processor I/O Voltage) . . . . . . . 62
`4.10.4 VDD_REF (Power Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`4.10.5 VDD_RTC (Power Supply to RTC) . . . . . . . . . . . . . . . . . . . . . . 62
`4.10.6 VDD-SOFT (Power Supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`4.10.7 VDD-USB (USB Differential Output Power) . . . . . . . . . . . . . 62
`
`5
`
`Functional Operations
`
`63
`
`5.1
`
`PCI Bus-Initiated Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`
`5.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`
`5.2
`
`PCI Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`
`5.2.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`5.2.2 Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`5.2.3 I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
`5.2.4 Memory Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
`5.2.5 Configuration Read and Write . . . . . . . . . . . . . . . . . . . . . . . . 75
`5.2.6 Memory Read Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`5.2.7 Dual Address Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`5.2.8 Memory Read Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`5.2.9 Memory Write Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`
`5.3
`
`PCI Bus Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`
`5.3.1 Back-to-Back Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`5.3.2 Subtractive Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`5.3.3 ISA Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`
`5.4
`
`ISA Bus-Initiated Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`
`5.4.1 DMA-Initiated Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`5.4.2 ISA Bus Master Initiated Cycles . . . . . . . . . . . . . . . . . . . . . . . 80
`
`Table of Contents
`
`vii
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 7 of 368
`
`

`

`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`22548B/0—August 1999
`
`5.5
`
`5.6
`
`5.7
`
`5.8
`
`5.9
`
`PCI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`
`I/O and Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`
`5.6.1 I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
`5.6.2 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
`5.6.3 System ROM Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . 86
`
`Power Planes and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
`
`Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
`
`Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
`
`5.10 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
`
`5.10.1 DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
`5.10.2 DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
`5.10.3 Middle Address Bit Latches . . . . . . . . . . . . . . . . . . . . . . . . . . 93
`5.10.4 Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
`5.10.5 DMA Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
`5.10.6 Type F DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
`5.10.7 DMA Channel Mapping Registers . . . . . . . . . . . . . . . . . . . . . 98
`5.10.8 Ready Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
`5.10.9 External Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
`
`5.11 Distributed DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
`
`5.11.1 Target DMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
`5.11.2 DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
`5.11.3 DMA Software Commands . . . . . . . . . . . . . . . . . . . . . . . . . . 103
`5.11.4 DMA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
`5.11.5 PCI Target DMA Configuration Registers . . . . . . . . . . . . . . 105
`
`5.12 ISA Bus Refresh Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . 105
`
`5.13 Fast IDE/EIDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
`
`5.13.1 IDE Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
`5.13.2 IDE Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 106
`5.13.3 Ultra DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
`
`5.14 Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . 111
`
`5.14.1 Power Management Subsystem . . . . . . . . . . . . . . . . . . . . . . 111
`5.14.2 Power Plane Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
`5.14.3 SCI and SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
`5.14.4 System Inactivity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
`
`viii
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`Table of Contents
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 8 of 368
`
`

`

`22548B/0—August 1999
`
`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`5.14.5 Throttling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
`5.14.6 System Power State Controller (SPSC) . . . . . . . . . . . . . . . . 118
`5.14.7 Serial IRQ Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
`5.14.8 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
`5.14.9 Plug and Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
`5.14.10General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
`5.14.11General-Purpose I/O Functions . . . . . . . . . . . . . . . . . . . . . . . 126
`5.14.12AMD-751™ Controller Power Management . . . . . . . . . . . . 128
`5.14.13VDD_SOFT Registers and Logic . . . . . . . . . . . . . . . . . . . . . . 128
`5.14.14RTC and CMOS Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
`
`5.15 Universal Serial Bus Controller (USBC) . . . . . . . . . . . . . . . 131
`
`5.15.1 USBC Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . . 134
`5.15.2 System Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
`
`5.16 Programmable Interrupt Controller (PIC) . . . . . . . . . . . . . 141
`
`5.16.1 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
`
`5.17 I/O Advanced Programmable Interrupt Controller
`(IOAPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
`
`6
`
`Initialization
`
`157
`
`6.1
`
`6.2
`
`6.3
`
`Legacy I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
`
`PCI Function 1 Registers—IDE Controller . . . . . . . . . . . . . 164
`
`PCI Function 3 Registers—Power Management . . . . . . . . . 166
`
`6.3.1 Power Management Configuration Space Registers . . . . . 166
`6.3.2 Power Management I/O Space Registers . . . . . . . . . . . . . . . 169
`
`6.4
`
`PCI Function 4 Registers—USB Controller . . . . . . . . . . . . 171
`
`6.4.1 Pins Latched At The Trailing Edge Of RESET . . . . . . . . . . 172
`
`7
`
`Registers
`
`175
`
`7.1
`
`7.2
`
`7.3
`
`7.4
`
`Table Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
`
`PCI Mechanism #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
`
`Register Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
`
`Legacy I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
`
`Table of Contents
`
`ix
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 9 of 368
`
`

`

`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`22548B/0—August 1999
`
`7.4.1 Keyboard Controller Registers . . . . . . . . . . . . . . . . . . . . . . . 187
`7.4.2 DMA Controller I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . 192
`7.4.3 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . 194
`7.4.4 Interrupt Controller Shadow Registers . . . . . . . . . . . . . . . . 195
`7.4.5 Timer/Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
`7.4.6 CMOS/RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
`7.4.7 Miscellaneous I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . 201
`
`7.5
`
`Function 0 Registers (PCI-ISA Bridge) . . . . . . . . . . . . . . . . 202
`
`7.5.1 ISA Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
`7.5.2 Distributed DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
`
`7.6
`
`Function 1 Registers (Enhanced IDE Controller) . . . . . . . 212
`
`7.6.1 Function 1 PCI Configuration Space Header . . . . . . . . . . . 213
`7.6.2 IDE Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 218
`
`7.7
`
`Function 3 Registers (Power Management) . . . . . . . . . . . . 223
`
`7.7.1 Function 3 PCI Configuration Space Header . . . . . . . . . . . 224
`7.7.2 Power Management Configuration Registers . . . . . . . . . . . 225
`7.7.3 Power Management I/O Space Registers . . . . . . . . . . . . . . . 242
`7.7.4 Processor Power Management Registers . . . . . . . . . . . . . . . 247
`
`7.8
`
`Function 4 Registers (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . 270
`
`7.8.1 Function 4 USB Configuration . . . . . . . . . . . . . . . . . . . . . . . 270
`7.8.2 USB Memory Mapped Registers (Open HCI Registers) . . . 274
`7.8.3 I/O APIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
`
`8
`
`Electrical Data
`
`293
`
`8.1
`
`8.2
`
`8.3
`
`8.4
`
`Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
`
`Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
`
`DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
`
`Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
`
`9
`
`Switching Characteristics
`
`299
`
`9.1
`
`9.2
`
`OSC Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 300
`
`PCI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
`
`x
`
`Table of Contents
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 10 of 368
`
`

`

`22548B/0—August 1999
`
`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`9.3 USB Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
`
`9.4
`
`9.5
`
`9.6
`
`ISA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
`
`DMA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
`
`EIDE Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
`
`9.7 Ultra DMA-33 IDE Bus Interface Timing . . . . . . . . . . . . . . 325
`
`10 Pin Designations
`
`327
`
`10.1 Pin Designation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
`
`10.1.1 State of Pins At Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
`10.1.2 AMD-756™ Peripheral Bus Controller Pin Diagram . . . . . 335
`10.1.3 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
`
`11 Package Specifications
`
`339
`
`Table of Contents
`
`xi
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 11 of 368
`
`

`

`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`22548B/0—August 1999
`
`xii
`
`Table of Contents
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 12 of 368
`
`

`

`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`22548B/0—August 1999
`
`List of Figures
`
`AMD-750™ Chipset System Block Diagram . . . . . . . . . . . . . . . 2
`Figure 1.
`AMD-756™ Peripheral Bus Controller Block Diagram . . . . . . 8
`Figure 2.
`AMD-756™ Peripheral Bus Controller Signal Groups. . . . . . 14
`Figure 3.
`I/O Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
`Figure 4.
`I/O Cycle 16-Bit to 8-Bit Conversion . . . . . . . . . . . . . . . . . . . . 66
`Figure 5.
`Non-Posted PCI-to-ISA Access . . . . . . . . . . . . . . . . . . . . . . . . . 67
`Figure 6.
`Posted PCI-to-Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . 68
`Figure 7.
`ISA Bus Memory Access Cycle. . . . . . . . . . . . . . . . . . . . . . . . . 69
`Figure 8.
`ISA Bus Memory Cycle: 16-Bit to 8-Bit Conversion . . . . . . . . 70
`Figure 9.
`Figure 10. Memory Cycle 32-Bit to 8-Bit Conversion . . . . . . . . . . . . . . . . 71
`Figure 11. Memory Cycle 32-Bit to 16-Bit Conversion . . . . . . . . . . . . . . . 72
`Figure 12.
`ROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Figure 13.
`ROM Cycle 32-Bit to 8-Bit Conversion . . . . . . . . . . . . . . . . . . 74
`Figure 14.
`Configuration Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`Figure 15.
`Configuration Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Figure 16.
`Subtractive Decode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`Figure 17.
`DMA Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
`Figure 18.
`ISA Bus Master Arbitration Timing . . . . . . . . . . . . . . . . . . . . 81
`Figure 19.
`ISA Bus Master-to-PCI Memory (Memory Read) . . . . . . . . . . 82
`Figure 20.
`ISA Bus Master-to-PCI Memory (Memory Write). . . . . . . . . . 82
`Figure 21.
`Normal Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 90
`Figure 22.
`Type F DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
`Figure 23.
`DMA Ready Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
`Figure 24.
`IDE Controller Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 106
`Figure 25.
`Power Management and General Purpose I/O . . . . . . . . . . . 111
`Figure 26.
`Basic Power Management Block Diagram . . . . . . . . . . . . . . 112
`Figure 27.
`SCI/SMI Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
`Figure 28.
`Power State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
`Figure 29. Mechanical Off to Full On . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
`Figure 30.
`Soft Off to Full On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
`Figure 31.
`General-Purpose I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
`Figure 32.
`FPIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
`
`List of Figures
`
`xiii
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1038
`Page 13 of 368
`
`

`

`Preliminary Information
`AMD-756™ Peripheral Bus Controller Data Sheet
`
`22548B/0—August 1999
`
`PIC Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 146
`Figure 33.
`Priority Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
`Figure 34.
`System-Level Implementation of APIC Components . . . . . 154
`Figure 35.
`Figure 36. WSC# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
`Figure 37.
`OSC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
`Figure 38.
`PCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
`Figure 39.
`Setup, Hold, and Valid Delay Timing Diagram . . . . . . . . . . 302
`Figure 40.
`USBCLK Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
`Figure 41.
`USB DATA Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
`Figure 42.
`BCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
`Figure