CMOS, the Ideal Logic
`Family
`
`Fairchild Semiconductor
`Application Note 77
`January 1983
`
`l=AIRCHILC
`
`SEMICONDUCTOR
`
`TM
`
`CHARACTERISTICS OF CMOS
`The aim of this section is to give the system designer not fa
`miliar with CMOS a good feel for how it works and how it be
`haves in a system Much has been written about MOS de
`vices in general Therefore we will not discuss the design
`and fabrication of CMOS transistors and circuits
`The basic CMOS circuit is the inverter shown in Figure 1 t
`consists of two MOS enhancement mode transistors the up
`per a P channel type the lower an N channel type
`
`Vee
`
`G tl, P·CHANNEL
`0 J--o
`
`Vou,
`
`v,.
`
`(') s::
`0
`CJ) -::::T
`
`(D
`a.
`(D
`D)
`r-
`0
`
`(C er ,,
`
`D)
`3
`'<
`
`INTRODUCTION
`Lets talk about the characteristics of an ideal logic family
`should dissipate no power have zero propagation delay
`controlled rise and fall times and have noise immunity equal
`to 50% of the logic swing
`The properties of CMOS (complementary MOS) begin to ap
`proach these ideal characteristics
`First CMOS dissipates low power Typically the static power
`dissipation is 10 nW per gate which is due to the flow of leak
`age currents The active power depends on power supply
`voltage frequency output load and input rise time but typi
`cally gate dissipation at 1 MHz with a 50 pF load is less than
`10mW
`Second the propagation delays through CMOS are short
`though not quite zero Depending on power supply voltage
`the delay through a typical gate is on the order of 25 ns to
`50ns
`Third rise and fall times are controlled tending to be ramps
`rather than step functions Typically rise and fall times tend
`to be 20 to 40% longer than the propagation delays
`Last but not least the noise immunity approaches 50% be
`ing typically 45% of the full logic swing
`Besides the fact that it approaches the characteristics of an
`ideal logic family and besides the obvious low power battery
`applications why should designers choose CMOS for new
`systems? The answer is cost
`On a component basis CMOS is still more expensive than
`TTL However system level cost may be lower The power
`supplies in a CMOS system will be cheaper since they can
`be made smaller and with less regulation Because of lower
`currents the power supply distribution system can be sim
`pier and therefore cheaper Fans and other cooling equip
`ment are not needed due to the lower dissipation Because
`of longer rise and fall times the transmission of digital sig
`nals becomes simpler making transmission techniques less
`expensive Finally there is no technical reason why CMOS
`prices cannot approach present day TTL prices as sales vol
`ume and manufacturing experience increase So an engi
`near about to start a new design should compare the system
`level cost of using CMOS or some other logic family He may
`find that even at todays prices CMOS is the most economi
`cal choice
`Fairchild is building two lines of CMOS The first is a number
`of parts of the CD4000A series The second is the 54C/7 4C
`series which Fairchild introduced and which will become the
`industry standard in the near future
`The 54C/7 4C line consists of CMOS parts which are pin and
`functional equivalents of many of the most popular parts in
`the 7 400 TTL series This line is typically 50% faster than the
`4000A series and sinks 500/4 more current For ease of de
`sign it is spec d at TTL levels as well as CMOS levels and
`there are two temperature ranges available 54C --55•c to
`+ 125°C or 7 4C -40°C to +85°C Table 1 compares the port
`parameters of the 54C/74C CMOS line to those of the 54U
`7 4l low power TTL line
`
`8
`
`G ~HANNEL
`
`GNO
`
`AN0080.
`FIGURE 1. Baaic CMOS lnvcner
`
`The power supplies for CMOS are called V00 and Vss or
`Vee and Ground depending on the manufacturer V00 and
`V ss are carryovers from conventional MOS circuits and
`stand for the drain and source supplies These do not apply
`directly to CMOS since both supplies are really source sup
`plies V cc and Ground are carryovers from TTL logic and
`that nomenclature has been retained with the introduction of
`the 54C/74C line of CMOS Vee and Ground is the nomen
`clature we shall use throughout this paper
`The logic levels in a CMOS system are Vee (logic "1") and
`
`Ground (logic ·o, Since ·on· MOS transistor has virtually no
`
`voltage drop across it if there is no current flowing through it
`and since the input impedance to CMOS device is so high
`(the input characteristic of an MOS transistor is essentially
`capacitive looking like a 10120 resistor shunted by a 5 pF
`capacitor) the logic levels seen in a CMOS system will be
`essentially equal to the power supplies
`
`)> z I ......
`
`......
`
`Cl 1998 Fairchild SemicotdJctor Corporation
`
`AN006019
`
`www airchiktsemi com
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 1 of 10
`
`

`

`TABLE 1. Comparison of 541.J74L Low Power TTL and 54Cn4C CMOS Pon Parameters
`
`Family
`
`Vee
`
`54-l/74L
`
`54Cl74C
`
`54Cl74C
`
`5
`5
`
`10
`
`V1.
`
`Max
`
`0.7
`0.8
`
`2.0
`
`...
`
`Max
`
`0.18mA
`-
`-
`
`V1H
`
`~H
`
`.... 2.4V
`10pA
`-
`-
`
`2.0
`3.5
`
`8.0
`
`VOL
`
`Max
`
`0.3
`0.4
`
`1.0
`
`lot.
`
`2.0mA
`
`360µA
`(Note 1)
`10pA
`(Note 2)
`
`VQH
`Min
`2.4
`2.4
`
`9.0
`
`loH
`
`100µA
`
`100pA
`(Nole I)
`10µA
`(Nole 2)
`
`1J)(IO
`Typ
`31
`
`60
`
`25
`
`tp(JI
`Typ
`
`35
`45
`
`30
`
`Polss,'Gate
`
`Static
`lmW
`
`0.00001 mW
`
`0.00003mW
`
`PIJIS~818
`1 MHz, SO pf Load
`
`2.25mW
`
`1.25 mW
`
`5mW
`
`Notel Assumes imer1acing to low power TTL
`Note2 Assumes imer1acing to CMOS.
`
`Now lets look at the characteristic cuives of MOS transistors
`to get an idea of how rise and fall times propagation delays
`and power dissipation will vary with power supply voltage
`and capacitive loading Figure 2 shows the characteristic
`cuives of N channel and P channel enhancement mode
`transistors
`There are a number of important obseivations to be made
`from these cuives Refer to the cuive of VGs = 15V (Gate to
`Source Voltage) for the N channel transistor Note that for a
`constant drive voltage V GS the transistor behaves like a cur
`rent source for Voss (Drain to Source Voltage) greater than
`V GS - VT (VT is the threshold voltage of an MOS transistor)
`For Voss below VGS - VT the transistor behaves essentially
`like a resistor Note also that for lower VGs s there are simi
`lar cuives except that the magnitude of the os s are signifi
`cantly smaller and that in fact os increases approximately
`as the square of increasing V Gs The P channel transistor
`exhibits
`identical
`essentially
`but
`complemented
`characteristics
`
`45
`
`I
`
`I
`
`Vcs @Vee• 15V
`
`f we try to drive a capacitive load with these devices we can
`see that the initial voltage change across the load will be
`ramp like due to the current source characteristic followed
`by a rounding off due to the resistive characteristic dominat
`ing as V 0s approaches zero Referring this to our basic
`CMOS inverter in Figure 1 as Vos approaches zero V0 1JT
`will approach Vee or Ground depending on whether the
`P channel or N channel transistor is conducting
`Now if we increase V cc and
`therefore V GS the inverter
`must drive the capacitor through a larger voltage swing
`However for this same voltage increase the drive capability
`( os) has increased roughly as the square of V Gs and there
`fore the rise times and the propagation delays through the
`inverter as measured in Figure 3 have decreased
`So we can see that for a given design and therefore fixed
`capacitive load increasing the power supply voltage will in
`crease the speed of the system ncreasing V cc increases
`speed but ii also increases power dissipation This is true for
`two reasons First CV2t power increases This is the power
`dissipated in a CMOS circuit or any other circuit for that mat
`ter when driving a capacitive load
`
`-
`
`IIFtlS[
`
`Vee
`
`cc
`.s
`:§ 30
`...
`~
`a:
`a:
`::,
`...
`u
`f ...
`
`15
`
`::,
`0
`
`Vos@Vcc=10V
`
`-
`
`'
`
`..
`..,
`:;,
`:,;
`z
`~
`
`Vcs @Vee• SV- ,-+- +-
`
`0
`
`5
`
`10
`
`15
`
`OUTPUT VOLTAGE V'"' (VI
`
`OUTPUT VOLTAGE Vos (VI
`
`·15
`
`-10
`
`-5
`
`......
`,-,-~.~ ~ v~'. Jv ~
`
`_,
`z
`z
`""
`~
`"-
`
`I
`I
`
`I
`I
`_I
`I
`I
`I
`Vosli>Vcc = 10V _
`I
`I
`I I
`I
`I
`I
`I I
`I
`I
`I
`
`J0.'@~C:, 1 ,~v
`
`I
`
`I
`
`I
`
`lA
`
`~
`
`IJ
`J
`
`-
`
`• 2
`
`0
`
`0
`
`10
`
`~
`C:
`..,
`-<
`C:
`:0
`~
`z
`-<
`20 g
`3
`e
`
`~ I
`
`I
`
`30
`ANOOtlO 93
`FIGURE 2. Logical "1" Output Voltage
`vs Source Current
`
`www airchiktsemi com
`
`2
`
`v,.
`
`GNO
`
`Vee
`
`GNO
`
`You,
`
`f 90"
`~ 50%
`
`10"'
`
`- ,..., t--
`
`\
`
`\50%
`
`j l-- lFALl
`90% "!
`50%
`
`It 10%
`
`- ... , r--
`k'
`
`5D¼j
`
`AN0060 ••
`FIGURE 3. Rise and Fall Times and Propagation
`Delays aa Measured in a CMOS System
`
`For a given capacitive load and switching frequency power
`dissipation increases as the square of the voltage change
`across the load
`The second reason is that the V power dissipated in the
`CMOS circuit increases with Vee (for Vccs > 2VT) Each
`time the circuit switches a current momentarily flows from
`V cc to Ground through both output transistors Since the
`threshold voltages of the transistors do not change with in
`creasing V cc the input voltage range through which the up
`per and lower transistors are conducting simultaneously in
`creases as Vee increases At the same time the higher Vee
`provides higher V GS voltages which also increase the magni
`tude of the J05 currents ncidently if the rise time of the in
`put signal was zero there would be no current flow from V cc
`to Ground through the circuit This current flows because the
`input signal has a finite rise time and therefore
`the input
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 2 of 10
`
`

`

`voltage spends a finite amount of time passing through the
`region where both transistors conduct simultaneously Obvi
`ously input rise and fall times should be kept to a minimum
`to minimize V power dissipation
`Let s look at the transfer characteristics Figure 5 as they
`vary with V cc For the purposes of this discussion we will as
`sume that both transistors in our basic inverter have identical
`but complementary characteristics and threshold voltages
`Assume the threshold voltages VT to be 2V
`f Vee is less
`than the threshold voltage of 2V neither transistor can ever
`f V cc is equal
`be turned on and the circuit cannot operate
`to the threshold voltage exactly then we are on the curve
`shown on Figure 5a We appear to have 100% hysteresis
`However it is not truly hysteresis since both output transis
`tors are off and the output voltage is being held on the gate
`capacitances of succeeding circuits
`f Vee is somewhere
`between one and two threshold voltages (Figure 5b) then
`we have diminishing amounts of "hysteresis" as we ap
`preach Vee equal to 2VT (Figure 5c) At Vee equal to two
`thresholds we have no "hysteresis" and no current flow
`through both the upper and lower transistors during switch
`ing As V cc exceeds two thresholds the transfer curves be
`gin to round off (Figure 5d) As V N passes through the region
`where both transistors are conducting the currents flowing
`through the transistors cause voltage drops across them
`giving the rounded characteristic
`Considering the subject of noise in a CMOS system we
`must discuss at least two specs noise immunity and noise
`margin
`Fairchilds CMOS circuits have a typical noise immunity of
`0 45 Vee This means that a spurious input which is 0 45
`Vee or less away from Vee or Ground typically will not
`propagate through the system as an erroneous logic level
`This does not mean that no signal at all will appear at the
`output of the first circuit n fact there will be an output signal
`as a result of the spurious input but it will be reduced in am
`plitude As this signal propagates through the system it will
`
`be attenuated even more by each circuit it passes through
`until it finally disappears Typically it will not change any sig
`nal to the opposite logic level n a typical flip flop a O 45 V cc
`spurious pulse on the clock line would not cause the flop to
`change state
`Fairchild also guarantees that its CMOS circuits have a 1 V
`DC noise margin over the full power supply range and tem
`perature range and with any combination of inputs This is
`simply a variation of the noise immunity spec only now a
`specific set of input and output voltages have been selected
`and guaranteed Stated verbally the spec says that for the
`output of a circuit to be within O 1 V cc volts of a proper logic
`level (V cc or Ground) the input can be as much as O 1 V cc
`plus 1V away from power supply rail Shown graphically we
`have
`
`15V
`
`"' ~
`~ ; 4.05
`u
`.;
`~
`
`3.05
`
`1.45
`0.45
`
`13.5
`12.5
`
`2.5
`1.5
`
`4.50V
`
`10V
`
`15V
`
`AN0060 99
`FIGURE 4. Guaranteed CMOS DC margin over
`temperature aa a function of V cc•
`CMOS Guaranteea 1 V.
`
`This is similar in nature to the standard TTL noise margin
`spec which is O 4V
`
`3
`
`www airchildsemi com
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 3 of 10
`
`

`

`I
`Vee .. v,
`
`I
`I
`v, < Vee <2V,
`
`I
`Vet:.• 2v,
`
`~ -
`
`'~
`
`~
`
`V," (VOL TS)
`
`AN0060 ••
`
`(a)
`
`v,. (VOLTS)
`
`(b)
`
`AN0060 ••
`
`v,. (VOLTS)
`
`(c)
`
`AN0060 97
`
`Vcc>tv,
`IS ,__ r--.__
`
`A
`I
`
`'\.
`I
`\ I
`
`\\
`~
`
`-
`
`j
`I
`V
`
`4
`
`"
`
`\
`
`' ...... \
`
`8
`
`'
`V,._ (VOlTSI
`
`10
`
`11
`
`14
`
`AN0060 ••
`
`(cf)
`
`FIGURE 5. Transfer Characteristics vs Vee
`
`Unused inputs: Simply stated unused inputs should not be
`left open Because of the very high impedance ( ~ 1012n) a
`floating input may drift back and forth between a "O" and "1 •
`creating some very intriguing system problems All unused
`inputs should be tied to V cc Ground or another used input
`The choice is not completely arbitrary however since there
`will be an effect on the output drive capability of the circuit in
`question Take for example a four input NAND gate being
`used as a two input gate The internal structure is shown in
`Figure 7 Let inputs A and B be the unused inputs
`f we are going to tie the urused inputs to a logic level inputs
`A and B would have to be tied to V cc to enable the other in
`puts to function That would tum on the lower A and B Iran
`sistors and tum off the upper A and B transistors At most
`only two of the upper transistors could ever be turned on
`However if inputs A and B were tied to input C the input ca
`pacitance would triple but each time C went low the upper
`A B and C transistors would tum on tripling the available
`source current
`f input D was low also all four of the upper
`transistors would be on
`
`'.:'.:
`
`; ..,
`
`to g
`
`2.4
`
`2.0
`
`0.8
`
`0.4
`
`4.5
`
`,.o
`Vee
`
`,.,
`
`....,...
`
`• 0
`
`FIGURE 8. Guaranteed TTL DC margin over
`temperature as a function of V cc•
`TTL Guarantees 1 V.
`
`For a complete picture of VouT vs V N refer to the transfer
`characteristic curves in Figure 5
`
`SYSTEM CONSIDERATIONS
`This section describes how to handle many of the situations
`that arise in normal system design such as unused inputs
`paralleling circuits for extra drive data bussing power con
`siderations and interfaces to other logic families
`
`www airchiktsemi com
`
`4
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 4 of 10
`
`

`

`So tying unused NANO gate inputs to Vee (Ground for NOR
`gates) will enable them but tying unused inputs to other
`used inputs guarantees an increase in source current in the
`case of NANO gates (sink current in the case of NOR gates)
`
`There is no increase in drive possible through the series
`transistors By using this approach a multiple input gate
`could be used to drive a heavy current load such as a lamp
`or a relay
`
`A
`
`Vee
`
`8 o,,-------t----1----------t-----1~
`
`DO-➔---t--+--•------------41~
`
`A
`
`0
`
`FIGURE 7. MM74C20 Four Input NANO gate
`
`ANOOOO 9
`
`Parallel gatea: Depending on the type of gate tying inputs
`together guarantees an increase in either source or sink cur
`rent but not both To guarantee an increase in both currents
`a number of gates must be paralleled as in Figure 8 This in
`sures that there are a number of parallel combinations of the
`series string of transistors (Figure 7) thereby increasing
`drive in that direction also
`
`OR
`
`AN0060. 2
`FIGURE 8. Paralleling Gatea or lnvenera lnercaaea
`Output Drive in Both Directions.
`
`Data buaaing: There are essentially two ways to do this
`First connect ordinary CMOS parts to a bus using transfer
`gates (Part No CD4016C) Second and the preferred way
`is to use parts specifically designed with a CMOS equivalent
`of a 3 STATE output
`Power aupply filtering: Since CMOS can operate over a
`large range of power supply voltages (3V to 15V) the filter
`ing necessary is minimal The minimum power supply volt
`
`age required will be determined by the maximum frequency
`of operation of the fastest element in the system (usually
`only a very small portion of any system operates at maxi
`mum frequency) The filtering should be designed to keep
`the power supply voltage somewhere between this minimum
`voltage and the maximum rated voltage the parts can toler
`ate However if power dissipation is to be kept to a mini
`mum the power supply voltage should be kept as low as
`possible while still meeting all speed requirements
`Minimizing ayatem power diaaipation: To minimize power
`consumption in a given system it should be run at the mini
`mum speed to do the job with the lowest possible power sup
`ply voltage AC and DC transient power consumption both
`increase with frequency and power supply voltage The AC
`power is described as CV2t power This is the power dissi
`pated in a driver driving a capacitive load Obviously AC
`power consumption increases directly with frequency and as
`the square of the power supply t also increases with capaci
`tive load but this is usually defined by the system and is not
`alterable The DC power is the V power dissipated during
`switching n any CMOS device during switching there is a
`momentary current path from the power supply to ground
`(when Vee> 2VT) Figure 9
`
`5
`
`www airchildsemi com
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 5 of 10
`
`

`

`The maximum amplitude of the current is a rapidly increas
`ing function of the input voltage which in tum is a direct tune
`lion of the power supply voltage See Figure 5d
`The actual amount of V power dissipated by the system is
`determined by three things power supply voltage frequency
`and input signal rise time A very important factor is the input
`rise time
`f the rise time is long power dissipation increases
`since the current path is established for the entire period that
`the input signal is passing through the region between the
`threshold voltages of the upper and lower transistors Theo
`retically if the rise time were zero no current path would be
`
`established and the V power would be zero However with
`a finite rise time there is always some current flow and this
`current flow increases rapidly with power supply voltage
`Just a thought about rise time and power dissipation
`f a cir
`cuit is used to drive many loads its output rise time will suf
`fer This will result in an increase in V power dissipation in
`every device being driven by that circuit (but not in the drive
`circuit itself)
`f power consumption is critical it may be nee
`essary to improve the rise time of that circuit by buffering or
`by dividing the loads in order to reduce overall power
`consumption
`
`V,N
`
`Vee
`
`GNO-
`
`v,
`i
`
`v,
`-
`
`~IRIS~
`
`lsw
`
`IMAX-
`
`GNO-
`
`A
`
`t
`
`\
`- ~lfAl.l
`~
`
`GNO
`....,...
`
`• 3
`
`VT v,
`
`t-tTQTAl
`
`_______
`
`_
`
`....,... ..
`
`VI Power Is Given By:
`Pv1 = Ve,:; x 2 'Max x Rise Time to Period Ratio
`1
`.
`.
`
`1R1Se + tFALL
`Rise Time to Vee - 2Vr
`Period Ratio = ~ x
`tror Al
`1
`
`Where~
`
`- Frequency
`
`Pv1 - ½ {Vee -2Vr)
`
`Ice Max (li,15E + t,AU.l FREQ.
`
`FIGURE 9. DC Transient Power
`
`2
`
`So to summarize the effects of power supply voltage input
`voltage input rise time and output load capacitance on sys
`tern power dissipation we can say the following
`1 Power aupply voltage: CV2t power dissipation
`in
`creases as the square of power supply voltage V power
`dissipation increases approximately as the square of the
`power supply voltage
`Input voltage level: V power dissipation increases if
`the input voltage lies somewhere between Ground plus
`a threshold voltage and Vee minus a threshold voltage
`The highest power dissipation occurs when V,N is at ½
`Vee CV2f dissipation is unaffected
`Input riae time: V power dissipation increases with
`longer rise times since the DC current path through the
`device is established for a longer period The CV2t
`power is unaffected by slow input rise times
`4 Output load capacitance: The CV2f power dissipated
`in a circuit increases directly with load capacitance V
`power in a circuit is unaffected by its output load capaci
`lance However increasing output load capacitance will
`slow down the output rise time of a circuit which in tum
`will affect the V power dissipation in the devices it is
`driving
`
`3
`
`INTERFACES TO OTHER LOGIC TYPES
`There are two main ideas behind all of the following inter
`faces to CMOS First CMOS outputs should satisfy the cur
`rent and voltage requirements of the other family s inputs
`Second and probably most important the other family s out
`puts should swing as near as possible to the full voltage
`range of the CMOS power supplies
`P-Channel MOS: There are a number of things to watch for
`when interlacing CMOS and P MOS The first is the power
`supply set Most of the more popular P MOS parts are speci
`fied with 17V to 24V power supplies while the maximum
`power supply voltage for CMOS is 15V Another problem is
`that unlike CMOS the output swing of a push pull P MOS
`output is significantly less than the power supply voltage
`across it P MOS swings from very close to its more positive
`supply (V ssl to quite a few volts above its more negative
`supply (V00 ) So even if P MOS uses a 15V or lower power
`supply set its output swing will not go low enough for a reli
`able interlace to CMOS There are a number of ways to
`solve this problem depending on the configuration of the sys
`tern We will discuss two solutions for systems that are built
`totally with MOS and one solution for systems that include bi
`polar logic
`
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`
`6
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 6 of 10
`
`

`

`First MOS only P MOS and CMOS using the same power
`supply of less than 15V Figure 10
`n this configuration CMOS drives P MOS directly However
`P MOS cannot drive CMOS directly because of its output will
`not pull down close enough to the lower power supply rail
`Apo (R pull down) is added to each P MOS output to pull it
`all the way down to the lower rail
`ts value is selected such
`that it is small enough to give the desired RC time constant
`when pulling down but not so small that the P MOS output
`cannot pull it virtually all the way up to the upper power sup
`ply rail when it needs to This approach will work with
`push pull as well as open drain P MOS outputs
`Another approach in a purely MOS system is to build a
`cheap zener supply to bias up the lower power supply rail of
`CMOS Figure 11
`
`n this configuration the P MOS supply is selected to satisfy
`the P MOS voltage requirement The bias supply voltage is
`selected to reduce the total voltage across the CMOS (and
`therefore its logic swing) to match the minimum swing of the
`P MOS outputs The CMOS can still drive P MOS directly
`and now the P MOS can drive CMOS with no pull down re
`sistors The other restrictions are that the total voltage
`across the CMOS is less than 1 SV and that the bias supply
`can handle the current requirements of all the CMOS This
`approach is useful if the P MOS supply must be greater than
`15V and the CMOS current requirement is low enough to be
`done easily with a small discrete component regulator
`f the system has bipolar logic it will usually have at least two
`power supplies n this case the CMOS is run off the bipolar
`supply and it interfaces directly to P MOS Figure 12
`
`SUPPLY l
`
`l'MOS
`
`-.,,.
`
`< 15V -
`T
`Vee
`
`CMOS
`
`GND
`
`I -
`
`1
`v,.
`
`PMOS
`•••
`T
`
`~
`
`I
`Yee
`
`CMOS
`
`-
`"·• GND
`I
`
`AN0080 ••
`
`FIGURE 10. A One Power Supply Syetem
`Built Entirely of CMOS and P-MOS
`
`SUPPLY -.:
`
`"'0S
`
`1
`Yee
`
`CMOS
`
`GND
`l
`
`., ...L
`Vz ~
`l Tc,.L,u1
`
`1
`v,.
`
`...OS
`
`...
`
`I
`Vee
`
`CMOS
`
`CND
`I
`
`AN0060 ••
`
`Use a Bias supply to reduce the voltage aaoss the CMOS to match the logic swilg
`of the P·MOS. Make sure the res<Jtilg voltage across the CMOS is less than 1 5V.
`FIGURE 11. AP-MOS and CMOS Syatem Where the
`P-MOS Supply ia Greater than 15V
`
`11 ..... 1
`.
`':" --
`
`-
`
`SUPPLY
`
`PMOSI
`SU,rl Y
`.l.
`
`T
`
`.
`
`Vee
`
`CMOS
`
`GND
`I
`
`1
`v.,
`
`-
`
`PMOS
`
`Yoo
`
`I
`Yee
`
`CMOS
`
`GNO
`I
`
`AN0080. 7
`
`Run the CMOS from the bipolar sulll)ly and interlace directly to P-MOS.
`FIGURE 12. A Syatem with CMOS, P-MOS and Bipolar Logic
`
`N-Channel MOS: nterfacing to N MOS is somewhat simpler
`than interfacing to P MOS although similar problems exist
`
`First N MOS requires lower power supplies than P MOS
`being in the range of SV to 12V This is directly compatible
`
`7
`
`www airchildsemi com
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 7 of 10
`
`

`

`with CMOS Second N MOS logic levels range from slightly
`above the lower supply rail to about 1 V to 2V below the up
`per rail
`At the higher power supply voltages N MOS and CMOS can
`be interfaced directly since the N MOS high logic level will be
`only about 10 to 20 percent below the upper rail However at
`lower supply voltages the N MOS output will be down 20 to
`40 percent below the upper rail and something may have to
`be done to raise it The simplest solution is to add pull up re
`sistors on the N MOS outputs as shown in Figure 13
`-
`T
`~
`'A~
`'
`
`T
`V«
`
`CMOS
`
`-
`
`T
`Voo
`
`NMOS
`
`1
`
`I
`Vee
`
`CMOS
`
`1 NMOS
`
`..:.
`
`SUPPLY
`S TO 12V
`
`GNO
`I
`
`v,.
`I
`
`~
`
`GNO
`I
`
`AN0080.
`
`8
`
`~~gi,erate off same supply with pull up resistors optional from N·MOS to
`
`FIGURE 13. A Syatem with CMOS and N-MOS Only
`
`TTL, LPTTL, DTL: Two questions arise when interfacing bi
`polar logic families to CMOS First is the bipolar family s
`logic •1• output voltage high enough to drive CMOS directly?
`TTL LPTTL and DTL can drive 74C series CMOS directly
`over the commercial temperature range without external pull
`up resistors However TTL and LPTTL cannot drive 4000 se
`ries CMOS directly (DTL can) since 4000 series specs do not
`guarantee that a direct interface with no pull up resistors will
`operate properly
`DTL and LPTTL manufactured by Fairchild (FS LPTTL pulls
`up one diode drop higher than the LPTTL of other vendors)
`will also drive 7 4C directly over the entire military tempera
`lure range LPTTL manufactured by other vendors and stan
`dard TTL will drive 7 4C directly over most of the military tern
`the TTL logic •1 • drops to a
`perature range However
`somewhat marginal level toward the lower end of the military
`temperature range and a pull up resistor is recommended
`According to the curve of DC margin vs Vee for CMOS in
`Figure 4 if the CMOS sees an input voltage greater than
`Vee - 1 SV (Vee= SV) the output is guaranteed to be less
`than 0 SV from Ground The next CMOS element will amplify
`this 0 SV level to the proper logic levels of V cc or Ground
`The standard TTL logic ·1· spec is a V00 T min of 2 4V
`sourcing a current of 400 µA This is an extremely conserva
`live spec since a TTL output will only approach a one level of
`2 4V under the extreme worst case conditions of lowest tern
`perature high input voltage (0 8V) highest possible leakage
`currents (into succeeding TTL devices) and Vee at the low
`est allowable (Vee= 4 SV)
`Under nominal conditions (25"C v,N = 0 4V nominal leak
`age currents into CMOS and Vee= SV) a TTL logic •1• will
`be more like Vee - 2V0 or Vee - 1 2V Varying only tern
`perature the output will change by two times -2 mV per ·c
`or -4 mV per ·c Vee -1 2V is more than enough to drive
`CMOS reliably without the use of a pull up resistor
`f the system is such that the TTL logic "1 • output can drop
`below V cc - 1 SV use a pull up resistor to improve the logic
`•1 • voltage into the CMOS
`
`www airchiktsemi com
`
`8
`
`---=-5V •10%
`
`T
`
`TTL
`
`GNO
`1
`
`I
`Vee
`
`-
`T
`
`::: R,u
`
`..
`. - .. CMOS
`l
`
`GNO
`1
`
`AN0080 •
`Pull up resistor, Aro, is needed only at the lower end of the Mil
`ten-.,erature range .
`FIGURE 14. TTL to CMOS Interface
`
`•
`
`The second question is can CMOS sink the bipolar input
`current and not exceed the maximum value of the bipolar
`logic zero input voltage? The logic •1• input is no problem
`The LPTTL input current is small enough to allow CMOS to
`drive two loads directly Normal power TTL input currents are
`ten times higher than those in LPTTL and consequently the
`CMOS output voltage will be well above the input logic "O"
`maximum of 0 8V However by carefully examining the
`CMOS output specs we will find that a two input NOR gate
`can drive one TTL load albeit somewhat marginally For ex
`ample the logical "O" output voltage for both an MM74COO
`and MM74C02 over temperature is specified at 0 4V sinking
`360 µA (about 420 µA at 25°C) with an input voltage of 4 0V
`and a Vee of 4 75V Both schematics are shown in Figure
`15
`Both parts have the same current sinking spec but their
`structures are different What this means is that either of the
`lower transistors in the MM7 4C02 can sink the same current
`as the two lower series transistors in the MM7 4CO0 Both
`MM7 4C02 transistors together can sink twice the specified
`current for a given output voltage
`f we allow the output volt
`age to go to 0 8V then a MM74C02 can sink four times 360
`µA or 1 44 mA which is near1y 1 6 mA Actually 1 6 mA is the
`maximum spec for the TTL input current and most TTL parts
`run at about 1 mA Also 360 µA is the minimum CMOS sink
`current spec the parts will really sink somewhere between
`360 µA and 540 µA (between 2 and 3 LPTTL input loads)
`The 360 µA sink current is specified with an input voltage of
`4 0V Wrth an input voltage of 5 0V the sink current will be
`about 560 µA over temperature making it even easier to
`drive TTL At room temperature with an input voltage of SV
`a CMOS output can sink about 800 µA A 2 input NOR gate
`therefore will sink about 1 6 mAwith a VouT of about 0 4V if
`both NOR gate inputs are at SV
`The main point of this discussion is that a common 2 input
`CMOS NOR gate such as an MM7 4C02 can be used to drive
`a normal TTL load in lieu of a special buffer However the
`designer must be willing to sacrifice some noise immunity
`over temperature to do so
`
`TIMING CONSIDERATIONS IN CMOS MSla
`There is one more thing to be said in closing All the flip flops
`used in CMOS designs are genuinely edge sensitive This
`means that the J K flip flops do not ·ones catch" and that
`some of the timing restrictions that applied to the control
`lines on MS functions in TTL have been relaxed in the 74C
`series
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 8 of 10
`
`

`

`A 0-t---++--._J
`
`AN0080 • .,
`
`MM74C02
`
`AN0060 92
`
`MM74C00
`
`FIGURE 15.
`
`9
`
`www airchildsemi com
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 9 of 10
`
`

`

`>,
`E
`ca u.
`
`(.)
`C)
`0
`...J
`ca
`Cl)
`"C
`Cl)
`
`~ -
`
`......
`......
`I z
`<
`
`LIFE SUPPORT POLICY
`
`FA RCH LOS PRODUCTS ARE NOT AUTHOR ZED FOR USE AS CRT CAL COMPONENTS NL FE SUPPORT DE
`V CES OR SYSTEMS W THOUT THE EXPRESS WR TTEN APPROVAL OF THE PRES DENT OF FA RCH LO SEM
`CONDUCTOR CORPORA T ON As used herein
`Life support devices or systems are devices or sys
`terns which (a) are intended for surgical implant into
`the body or (b) support or sustain life and (c) whose
`failure to perform when properly used in accordance
`with instructions for use provided in the labeling can
`be reasonably expected to result in a significant injury
`to the user
`
`2 A critical component in any component of a life support
`device or system whose failure to perform can be rea
`sonably expected to cause the failure of the life support
`device or system or to affect its safety or effectiveness
`
`Fairchikl Semiconductor
`Corporation
`Americae
`customer Response Cen1er
`Tel 1 ·888·522•5372
`
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`
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`
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`
`F'alrChllO aoes not asslffl&
`
`,nv f8rpon&t11Hry IOI use 01 any arcunry oesatieo. ro cucu11 pa11en1 110enses a,e wr.,aea ana F'alrChllO 1868Ml6 1'18 rlgtt • "'If ane ~ l'IOIIC8 to cnange saJO circu1ry ana ~a:aons
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1017
`Page 10 of 10
`
`