United States Patent p91
`Hoshii
`
`I 11}
`(45)
`
`4,293,927
`Oct. 6, 1981
`
`(54] POWER CONSUMPTION CONTROL
`SYSTEM FOR ELECTRONIC DIGITAL DATA
`PROCESSING DEVICES
`(75] Inventor:
`Toshifumi Hoshii, Fussa, Japan
`(73) Assignee: Casio Computer Co., Ltd., Tokyo,
`Japan
`
`[21] Appl. No.: 102,768
`Dec. 12, 1979
`[22] Filed:
`[51) Int. CI.J ........................ G06F 11/30; H03K 5/13
`[52] U.S. Cl. .................................... 364/900; 307/269;
`365/227
`[58) Field of Search ................ 235/455, 472; 250/205,
`250/568; 340/146.3 F, 146.3 R, 365 R;
`365/226-229; 307/203, 269; 364/200 MS File,
`900 MS File, 736
`
`[56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,453,601 7/1969 Bogert et al. ....................... 364/200
`3,736,569 S/1973 Bouricius et al. ................... 365/227
`3,925,639 12/1975 Hesler ................................. 235/472
`
`3,941,989 3/1976 McLaughlin et al. ............. 307/203
`3,944,979 3/1976 Kwok .................................. 250/205
`4,072,859 2/1978 McWaters ........................... 250/568
`4,101,072 7/1978 Weaver et al ....................... 235/455
`4,137,563 1/1979 Tsunoda ............................. 307/269
`4,143,358 3/1979 Neff ........................... 34-0/146.3 SY
`4,144,580 3/1979 Seki et al ........................ 340/365 R
`4,160,156 7/1979 Sherer ................................. 235/472
`Primary Examiner-Leo H. Boudreau
`Attorney, Agent, or Firm-Frishauf, Holtz, Goodman
`and Woodward
`
`ABSTRACT
`(57]
`A power consumption control system for electronic
`digital data processing devices
`is provided with a
`counter circuit to update a time count operation and to
`count a given time every time any one of the keys in the
`key input section is depressed. When none of the keys in
`the key input section is depressed before the counter
`circuit finishes the count of the given time, the oscilla(cid:173)
`tion operation of the oscillator circuit which supplies
`the clock pulse to the data processing device is stopped.
`
`9 Claims, 39 Drawing Figures
`
`15
`
`18
`
`DISPLAY
`
`ROM
`
`CONTROL SIGNAL
`
`17
`
`TIMING SIGNAL
`
`16
`
`5
`
`
`
`...___, r-2
`
`3
`
`KEY
`INPUT
`SECTION
`
`I .;-- +Voe
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 1 of 18
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 2 of 18
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`

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`U.S. Patent Oct. 6, 1981
`
`Sheet 2 of 9
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 3 of 18
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`U.S. Patent Oct. 6, 1981
`
`Sheet 3 of 9
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`4,293,927
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 4 of 18
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 5 of 18
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 6 of 18
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`

`

`U.S. Patent Oct. 6, 1981
`
`Sheet 6 of 9
`
`4,293,927
`
`F I G. 6
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 7 of 18
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 8 of 18
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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 9 of 18
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`

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`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 10 of 18
`
`

`

`1
`
`4,293,927
`
`POWER CONSUMPTION CONTROL SYSTEM
`FOR ELECTRONIC DIGITAL DATA PROCESSING
`DEVICES
`
`15
`
`2
`power consumption in ek..:tromc d1g1tal data proces,ing
`devices, which can considerably reduce the power con(cid:173)
`sumption without
`interrupting
`the power source. To
`achieve this object, after a given time lapses from the
`5 final key-in operation in a power on state, an oscillating
`circuit
`to produce a clock pulse for forming various
`timing signals necessary
`for the circuit operation
`is
`automatically stopped thereby to decrease the effective
`frequency
`f.
`IO Another object nf the invention is to provide a power
`consumption
`control
`,ystt:m
`for effectively
`saving
`in the ekctronic device which can
`power consumption
`effectively release the automatic power off mode when
`the operation of a key i, performed after the autl)matic
`power off mode is set up.
`Another object of the invt'nlion is to provide a power
`.:011trol system which can release the auto(cid:173)
`consumption
`matic puwcr off mode by the operation by a proper key
`20 and at the same time can judge if the data processing for
`the depressed key is performed or not.
`•
`In the specification,
`the term "automatic power off'
`means that a power source system of the electronic
`device is automatically stopped and that the electronic
`25 device is placed in a low power consuming state sub(cid:173)
`stantially equivalent
`to a state that the power source is
`shut off.
`In the power consumption control system according
`to the invention, a pulse generator which consumes a
`relatively
`large power
`in the electronic device
`is
`stopped, so that the drive of 1he ele..:tronic device
`is
`stopped as if the power source is shut off.
`in the
`Accordingly,
`the term "automatic power off'
`specific?.tion of the present application is slightly differ(cid:173)
`ent from the sensed usually used. Since it has the same
`meaning as the general "autom;itic power off'. how-
`ever, the same term is used.
`
`BACKGROUND OF THE INVENTION
`The present
`invention relates to a power
`..:onsump(cid:173)
`tion control system for effectively saving power con(cid:173)
`sumption in an electronic device which is controlled
`in
`synchroni~m with a clock pulse from an oscillator cir(cid:173)
`cuit and digitally processes data.
`The electronic cievice of this type is miniaturized and
`mostly uses a battery as a power source. Therefore,
`the
`important problem in this type of device is how to re(cid:173)
`duce the power consumption of the electronic devi<.;e.
`is to prevent
`the useless power
`One of the proposals
`consumption of the battery when an operator
`fails to
`turn off the power switch of the electronic device.
`More specifically, a so-called automatic turn off system
`is known in which, after a given time lapses from the
`final key operation, a power source to drive the respec(cid:173)
`tive circuits is automatically
`turned off. This method is
`effective
`to save wasteful power consumption. How(cid:173)
`ever, when the key operation
`is held an in interrupted
`state during the operation
`for some reason, the power
`source is shut off upon a lapse of a given time after any
`key has been depressed immediately before it is put into
`the interrupted slate. As a result, the results of the oper(cid:173)
`ations are all cleared. In such a case, the operation must
`be newiy performed again. This is very onerous for the 30
`operator.
`(complementary
`The consumed power of CMOS
`type MOS) LSI chips, whi:;h has been employed in the
`electronic circuit of an electronic calculator
`in recent
`days, is generally expressed by fCV 2 where f is the 35
`frequency of the signal to the drive circuits, C is a stray
`capacitance and V is the operating voltage. lt can be
`seen from the expression that the decrease of the effec(cid:173)
`tive frequency f reduces the power consumption of the
`calculator.
`The conventional electronic calculator with an auto(cid:173)
`matic power off function
`involves another
`technical
`problem in releasing the automatic power off state. To
`release the automatic power off state, the conventional
`calculator uses a special key provided for the purpose of 45
`that release. Another conventional device employs an
`ON key and an OFF key and the ON key is used for
`releasing the automatic power off mode. A further con(cid:173)
`ventional calculator uses one (for example, a C (clear)
`key) of the various keys arranged
`in the key input sec- 50
`tion to release the automatic power off mode. The for(cid:173)
`mer cases need additional keys for its purpose. This
`leads to an increase of the number of keys and hinders
`the miniaturization of the device. The latter case does
`not need an additional key hut an operator must search 55
`for the specified key for the release from a number of
`keys. Further, before the data entering or the data pro(cid:173)
`cessing of an input, an operator must depress a key
`utterly unrelated
`to such operations. Therefore,
`the
`operability of the calculator
`is considerably deterio- 60
`rated.
`Accordingly, an object of the invention is to provide
`a power consumption
`control system for effectively
`saving power consumption
`in an electronic device
`which i~ controlled
`in syncrhonisrn with a clock pulse
`from an oscillator circuit and digitally processes data.
`Another object of the invention is to provide a power
`con~umption
`control
`system
`for effectively
`saving
`
`40
`
`SUMMARY OF THE INVENTION
`To achieve
`the above object,
`there
`is provided a
`power consumption control system for electronic digi(cid:173)
`tal data processing devices comprising: an oscillating
`circuit for producing a basic clock signal, for driving
`respective portions of the electronic device; a key input
`section having a plurality of key switches; counting
`means for updating and initiating a count operation
`every time any one of the key switches is operated; and
`control means for causing the oscillating circuit to stop
`generating the basic clock signal when none of the key
`switches is operated until said count means completes
`counting for a given period of time.
`With such a construction, when no keying in opera(cid:173)
`tion is performed for a given period of time while the
`power source is turned on, the oscillation of the oscillat(cid:173)
`to stop generation of the clock
`ing circuit
`is stopped
`signal and to thereby stop all the circuit operations.
`However,
`the operation results in the memory continue
`to be held or stored. Therefore,
`the wasteful power
`consumption when an operator
`fails to turn off the
`power source switch may be prevented. Additionally,
`the data obtained before the oscillation of the oscillating
`circuit stops is held and therefore
`the data is held even
`in the course of the operation execution. Ac.:ordingly,
`65 there is no need to reenter the identical data at the re(cid:173)
`start of the opcrafrm,
`thereby to allow the calculator
`to
`smoothly enter the execution of the operation.
`In this
`respect, the key in operation 1, tPm,,rkably improved.
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 11 of 18
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`

`

`4,293,927
`
`4
`oscillator 5 with such a construction operates when a
`signal with a logical level "l" is applied to the second
`input terminal of the NAND gate 11. That is to say,
`when the control signal C is logical "O", the oscillator 5
`oscillates, so that a clock pulse </) with frequency deter(cid:173)
`mined by a time constant C.R is outputted from the
`NAND gate 11. On the other hand, when a signal of
`logical "O" is applied to the second terminal of the
`NAND gate 11, that is, when the control signal C is
`logical "l ", the oscillator 5 stops its own operation so as
`not to produce the clock pulse </). The clock pulse </) is
`inputted to the frequency divider 6 to be frequency(cid:173)
`divided thus forming fundamental clock pulses </)1 and
`</)2 of a given frequency. These clock pulses cj)l and </)2
`are applied into a timing signal generator 19 in the CPU
`2.
`
`3
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 shows a block diagram of an overall construc(cid:173)
`tion of an embodiment when the power consumption
`control system of the invention is applied to an elec- 5
`tronic calculator;
`FIGS. 2(a) to 2(d) show a display state and a memory
`state
`in various operation modes of the calculator
`shown in FIG. l;
`FIGS. 3(a) to 3(d) illustrate levels at the respective 10
`portions in the oscillating circuit in the various opera(cid:173)
`tion modes of the calculator;
`FIG. 4 shows a block circuit diagram of an overall
`construction of another embodiment of this invention;
`FIGS. 5( a) to S(g) show a set of timing diagrams 15
`useful in explaining
`the operation of the calculator
`when a key is operated after the automatic power off
`mode is set up in the calculator;
`FIG. 6 shows a block diagram of an overall system of
`another embodiment when the system of the invention 20
`is applied to an electronic calculator;
`FIG. 7 shows a block diagram of the major portion of
`the circuit shown in FIG. 6;
`FIGS. 8(a) to 8(r) show a set of timing diagrams for
`explaining the operation of the circuit shown in FIG. 7; 25
`and
`FIGS. 9(a) to 9(/) show a set of timing diagrams for
`explaining another operation of the circuit shown in
`FIG. 7.
`
`DETAILED DESCRIPTION
`FIG. 1 is a block diagram of an overall system of an
`embodiment of the invention as applied to an electronic
`calculator. The embodiment of FIG. 1 comprises an
`oscillator circuit 1, a central processing unit (CPU) 2, a 35
`key input section 3, and a display section 4. The oscilla(cid:173)
`tor circuit 1 is further comprised of an oscillator 5, a
`frequency divider 6, and an input gate 7. To a first
`terminal of a NAND gate 9 in the input gate 7 through
`a inverter 8 is inputted a control signal C outputted 40
`from an ROM address section 16 in the CPU 2. An
`output signal from a NAND gate 10 is inputted to a
`second terminal of the NAND gate 9. An output signal
`from the NAND gate 9 is applied to a first input termi(cid:173)
`nal of the NAND gate 10. A second input terminal of 45
`the NAND gate 10 is directly coupled with an output
`terminal of the key input section 3 so that, when a key
`of the key input section 3 is operated, its key operation
`signal is inputted to the gate 10 and also is coupled
`through a resistor r with an input terminal of a power 50
`source (not shown) of a voltage + V DD• Accordingly,
`when a key of the key input section 3 is operated, a
`signal of a binary logical level "O" is applied to the
`NAND gate 10. When it is not operated, a signal of
`logical "l" is applied to the same. The control signal C 55
`is outputted as a signal of logical level "l" when none of
`the keys are operated during a given period, e.g. 10
`minutes or more. At this time, the input gate circuit 7
`stops the oscillation of the oscillator 5. The oscillator 5
`has a NAND gate 11, a resistor R of resistance Rand a 60
`capacitor C of capacitance C which are connected be(cid:173)
`tween the first input terminal and an output terminal of
`the NAND gate 11, and inverters 12 and 13 for sup(cid:173)
`pressing a wave distortion of a signal thercthrough
`connected in series across the capacitor C. Further, the 65
`output from the NAND gate 10 is applied to a second
`input terminal of the NAND gate 11 of which the out(cid:173)
`put signal(</)) is applied to the frequency divider 6. The
`
`The CPU 2 includes an ROM (read only memory) 15
`storing micro instructions to execute various operations
`of the calculator, an ROM address section 16 sequen(cid:173)
`tially specifying the addresses of the micro instructions
`stored in the ROM 15, an RAM (random access mem-
`ory) 17 for storing the data of the operation result of the
`entered data, an arithmetic and logic unit (ALU) 18 for
`executing given operations, and a timing signal genera(cid:173)
`tor 19 responsive to the clock pulses <pl and </)2 to pro(cid:173)
`duce various timing signals. When addressed by the
`ROM address section 16, the ROM 15 produces a micro
`instruction from the address specified. This micro in(cid:173)
`struction includes address data AD for specifying row
`30 and column addresses in a group of registers forming
`the RAM 17 and various control signals to control the
`arithmetic and logic unit 18 and the timing signal gener(cid:173)
`ator 19. The RAM 17, which is of a C-MOS static type,
`comprises a plurality of registers, for example, an X
`register 171 for storing a second operand (in this em(cid:173)
`bodiment, the X register also serves as a display regis-
`ter), an X register for storing a first operand, an A regis(cid:173)
`ter 173 used as a counter, a B register 174 and the like.
`The A register 173, to be more specific, is used as a
`counter to count time after none of the keys of the key
`input section 3 is operated. The operation of the time
`count is executed by the arithmetic and logic unit 18.
`When the contents of the register 173 becomes 10 min(cid:173)
`utes, the ROM address section 16 provides the control
`signal C.
`The B register 174 is used as another counter to count
`and store the column address at the time of the key
`sampling operation in the key input section 3 and the
`display digit of the display section 4. As will be de(cid:173)
`scribed later, the key sampling operation and the dis(cid:173)
`play operation are executed simultaneously. The opera-
`tion to update the contents of the counter is executed by
`the arithmetic and logic unit 18. In a normal operation
`mode, the arithmetic and logic unit 18 operates the data
`sequentially read out from the RAM 17 and loads the
`result of the operation into the register specified in the
`RAM 17. In a time count operation, the operation cir(cid:173)
`cuit 18 performs the given number of additions of the
`contents of the A register 173 in the RAM 17 which are
`periodically read out. The addition operations are each
`such as a "+ 1" operation. The result of the operation is
`transferred into the A register 173 and is stored therein.
`The operation circuit 18 performs periodically the key
`sampling operation as mentioned above and the opera(cid:173)
`tion to update the contents of the 8 register 174 in the
`display operation mode. Also in this operation mode,
`the contents of the R register 174 i~ read out into rhe
`operation circuit 18 where the "+I" operation is per-
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 12 of 18
`
`

`

`4,293,927
`
`5
`6
`P of the X register 171 represents the place of the deci(cid:173)
`formed. The result of the operation is transferred to the
`key input section 3 and the display section 4, and at the
`mal point. FIG. 3(a) shows the level at the respective
`portions of the oscillating circuit 1 at this time. After the
`same time to the B register 174 to be stored therein.
`numeral key II] is operated, if the key operation ceases
`The key input section 3 has a plurality of keys ar(cid:173)
`for 10 minutes or more, for example, in the course of the
`ranged in matrix fashion. In the key sampling operation, 5
`operation, the key sampling operation is performed
`when the column addresses are successively specified
`by the contents of the B register 174, an ON/OFF state
`during this period to judge that the key is not operated.
`Also during this period, the operation to make " + I" of
`of each key switch of each column are detected. The
`the contents of the A register 173 as serving as the
`ON/OFF state is once loaded into a given register in
`the RAM 17 and then is transferred to the. operation 10
`counter for time count in the RAM 17 is repeated.
`circuit 18 where it is processed properly. At this time, if
`When it is judged that the contents of the A register 173
`amounts to the contents corresponding to the 10 min(cid:173)
`there is a key switch with an ON state, the data repre(cid:173)
`senting the key switch is applied to the X register 171
`utes, the ROM address section 16 produces the control
`for display in the RAM 17.
`signal Casa
`logical "I" signal. For this, the output of
`the inverter 8 becomes logical "O", as shown in FIG.
`The display section 4 has a plurality of display ele- 15
`3(b), so that the output signals of the NAND gates 9 and
`ments located at the corresponding digits. The digits of
`the display section 4 are sequentially specified by the
`10 are inverted to be "l" and "O" and the inverted states
`contents of the B register 174. At the same time, the
`are held. Accordingly, the output signal of the NANO
`contents of the X register 171 corresponding to the
`gate 11 continues the logical "l" state and the frequency
`divider 6 stops the production of the clock pulses 4>1
`digits are applied through the operation circuit 18 to the 20
`and q,2. As a result, all the operations of the CPU 2 stop.
`display section 4 where the contents of the correspond(cid:173)
`At this time, as shown in FIG. 2(b), the contents of the
`ing digits are displayed.
`X register 171 is kept without being cleared and further
`The central processing unit 2 and the display section
`4 are supplied with a power source voltage + V DD, as
`the display section 4 is in a blank state since it is not
`shown in FIG. 4. While the power source switch (not 25
`supplied with the drive pulse signal. In this way, when
`a key operation is not carried out for 10 minutes or
`shown) is turned on, when the control signal C is pro(cid:173)
`more, the operation of the oscillator circuit 1 is stopped
`duced, the oscillating circuit l stops its operation to
`produce no clock pulse 4>, so that the clock pulses 4>1
`after the outputting of the control signal C to stop the
`production of the clock pulses q,1 and 4>2. This state of
`and 4>2 are not produced. In such a situation, the CPU
`2 stops its operation, so that the CPU 2 and the display 30
`the circuit is equivalent to the power stoppage state.
`section 4 consume little power. This state is substan(cid:173)
`Therefore, the power consumption during this period is
`almost zero but the result of the operation is kept as it is
`tially equivalent to a state that the power source switch
`is turned off. Further, in this embodiment of the inven(cid:173)
`to be ready for the restart of the operation.
`To restart the operation, a key switch of the key input
`tion, the operation result or the like having been stored
`in the RAM 17 are backed up by the power source 35
`section 3 is then operated. Upon the operation of the
`voltage + V DD, so that the data is held.
`key switch, the output of the key switch (logical "O"
`signal) is inputted to the NANO gate 10 to invert the
`The operation of the above-mentioned embodiment
`will be described with reference to FIGS. 2 and 3.
`output signal for the NANO gate 11 to be logical "l".
`Accordingly, the NANO gate 11 starts to produce the
`FIGS. 2(a) to 2(d) show the display contents of the
`clock pulse 4> and thus to produce the clock pulses q,1
`display section 4 and the contents of the X register 171 40
`and 4>2, so that the key sampling operation of the CPU
`in four operation modes. FIGS. 3(a) to 3(d ) show the
`2 begins again. In this case, the control signal C is not
`logical levels at the respective portions in the oscillating
`produced to have a logical ''O" state. As shown in FIG.
`the
`circuit l in the operation modes, correspondinLto
`contents of FIGS. 2(a) to l(d). Numeral keys W, (I)
`l{c), the display operation of the display section 4 also
`and Ill of the key input section 3 are operated to enter 45
`restarts to display the numeral data "123." previously
`numeral data "123", At the time point that the numeral
`inputted. FIG. 3(d) shows a state of the oscillation cir(cid:173)
`key [I] is operated, the control signal is not yet output(cid:173)
`cuit 1 when the operation of the key switch is com(cid:173)
`pleted, and indicates that the state is returned to the
`ted, and therefore the output of the inverter 8 is logical
`"I", Further, the output of the NANO gate 10 is logical
`state shown in FIG. 3(a).
`"I", so that the output signal of the NANO gate 11 50
`In the above-mentioned embodiment, the oscillation
`produces the clock pulse 4> which alternately changes
`circuit is comprised of an RC oscillator, the frequency
`its level "I" and "O" at the periods each defined by the
`divider, and the input gate. The circuit may be vari(cid:173)
`time constant C.R and is applied to the frequency di(cid:173)
`ously modified, however, if the circuit modified is such
`vider 6. The frequency divider 6 forms the fundamental
`that, when the key is not operated for a given time while
`clock pulses 4>1 and 4>2 on the base of the clock pulse 4> S5
`the power source is turned on, the oscillation stops but
`is restarts when the key is operated at the operation
`which are in turn applied to the timing signal generator
`circuit 19 in the CPU 2 thereby to produce a given
`restart. Now referring to FIG. 4, another embodiment
`timing signal. The CPU 2 executes the key sampling
`of the invention will be described, in which any key
`operation at given periods as in the above-mentioned
`which is depressed first after the circuit has been set to
`manner to detect the ON/OFF state of the key switch 60
`the automatic power off mode will release the auto(cid:173)
`in the key i~ut section 3. As a result, when the numeral
`matic power off mode and the key which is depressed
`keys [Il, 111 and II) are sequentially depressed, the
`next makes the data entering possible. In FIG. 4 like
`numeral data "I", "2" and "3" are inputted into the X
`numerals are used to denote like elements shown in
`register 171 in the RAM 17. The contents of the X
`FIG. 1 and a few blocks indicate combinations of some
`blocks shown in FIG. 1, for simplicity of explanation.
`register 171 is transferred to the display section 4 where 65
`it is displayed. FIG. l(a) shows the display of the con(cid:173)
`In FIG. 4, reference numeral 20 designates a control
`tents of the X register 171 when the operation of the
`section including the ROM 15, the ROM address sec(cid:173)
`tion 16 and the timing signal generating circuit 19
`
`numeral key rn is completed. The least significant digit
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1016
`Page 13 of 18
`
`

`

`25
`
`7
`shown in FIG. 1. The circuit construction is similar to
`that shown in FIG. 1 and therefore the explanation of it
`will be omitted. The control section 20 is connected to
`an operation/memory section 21 including the RAM 17
`and the arithmetic and logic unit 18, through a bus line 5
`Bl. The key sampling data produced from the opera(cid:173)
`tion/memory section 21 is applied to the decoder 22,
`through a bus line B2. The decoder 22 decodes the key
`sampling data received
`to sequentially produce key
`sampling signals KSl to KS5, which in turn are applied 10
`through OR gates 311 to 315 to input lines Ll to LS.
`Key switches corresponding
`to numeral keys corre(cid:173)
`sponding to the numerals O to 9, and function keys to
`direct the operations respectively are arranged at the
`crosspoints of the input lines Ll to LS of the key input 15
`section 3 and the output lines Ml to M4. Accordingly,
`when the key sampling signals KSl to KSS are sequen(cid:173)
`tially inputted into the input lines L1 to LS, the ON/(cid:173)
`OFF state of the four keys on the respective input lines
`are outputted in parallel as the key data DO to DJ of 4 20
`bits which are in turn transferred to a key buffer register
`23 in the CPU 2. When the calculator is in the automatic
`power off mode, a reset output signal rt of an RS flip(cid:173)
`flop 24 which is reset when the calculator is in the
`automatic power off state is applied through OR gates
`311 to 315 to the input lines L1 to LS, in order that the
`automatic power off mode may be released by operat(cid:173)
`ing any of the keys in the key input section 3. The key
`data DO to DJ are all inputted to the first input terminals 30
`of AND gates 27 and 28 in the power source control
`circuit 26, through an OR gate 25. To the second input
`terminal of the AND gate 27 is inputted a set output
`signal S2 of an RS type flip-flop 29. The RS type flip(cid:173)
`flop 29 takes a set state when the calculator is in the 35
`automatic power off mode. For
`this, an automatic
`power off signal APO (substantially identical with the
`control signal C in FIG. 1) is inputted to the set input
`terminal S of the flip-flop 29. The signal APO is pro(cid:173)
`duced when the key of the key input section 3 remains 40
`unoperated for a given time period, for example, 10
`minutes while the power source switch 30 is left ON.
`For this, the arithmetic and logic circuit 18 in the opera(cid:173)
`tion/memory section 21 is so designed that the opera(cid:173)
`tion for the time count (for example, + 1 operation) is 45
`performed every key operation under control of the
`control section 20. At the time of operation, the A regis-
`ter 173 (see FIG. 1) of the RAM in the operation/mem(cid:173)
`ory 21 is used for storing the count data.
`The output signal from the AND gate 27 is inputted 50
`to a binary counter 31 where it is counted. The signal
`APO is inputted to the reset terminal of the binary
`the
`counter 31. When the APO signal is produced,
`binary counter 31 is reset to "0". When the contents of
`the binary counter 31 is counted up and its contents are 55
`changed from "l" to "0", a carry signal CA produced
`from the binary counter 31 is inputted to the reset input
`terminal R of the flip-flop 29. The reset output signal r2
`of the flip-flop 29 which is placed in the reset state is
`applied to the first input terminal of an AND gate 32. 60
`To the second input terminal of the AND gate 32 is
`supplied a clock pulse CP from the control section 20.
`When both the signal r2 and the clock pulse CP are
`supplied to the AND gate 32, a clock pulse CP' in syn(cid:173)
`chronism with the clock pulse CP is applied as a data 65
`write control signal from the AND gate 32 to the key
`buffer register 23, whereby the key data DO to DJ are
`loaded into the key buffer register 23.
`
`4,293,927
`
`8
`The power source voltage V DD is inputted into the
`input terminal of the power source switch 30 of which
`the output signal is supplied to one-shot circuit 33, an
`AND gate 28 and an inverter 34. The output signal from
`the one-shot circuit 33 is applied through an OR gate 35
`to the set input terminal S of an RS type flip-flop 24.
`To the AND gate 2