`
`10-Bit, 105 MSPS/125 MSPS/150 MSPS,
`1.8 V Dual Analog-to-Digital Converter
`AD9600
`
`
`
`
`FEATURES
`SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS
`SFDR = 81 dBc to 70 MHz at 150 MSPS
`Low power: 825 mW at 150 MSPS
`1.8 V analog supply operation
`1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply
`Integer 1 to 8 input clock divider
`Intermediate frequency (IF) sampling frequencies up to 450 MHz
`Internal analog-to-digital converter (ADC) voltage reference
`Integrated ADC sample-and-hold inputs
`Flexible analog input: 1 V p-p to 2 V p-p range
`Differential analog inputs with 650 MHz bandwidth
`ADC clock duty cycle stabilizer
`95 dB channel isolation/crosstalk
`Serial port control
`User-configurable built-in self-test (BIST) capability
`Energy-saving power-down modes
`Integrated receive features
`Fast detect/threshold bits
`Composite signal monitor
`APPLICATIONS
`Point-to-point radio receivers (GPSK, QAM)
`Diversity radio systems
`
`I/Q demodulation systems
`Smart antenna systems
`Digital predistortion
`General-purpose software radios
`Broadband data applications
`Data acquisition
`Nondestructive testing
`PRODUCT HIGHLIGHTS
`1.
`Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.
`2. Fast overrange detect and signal monitor with serial output.
`3. Signal monitor block with dedicated serial output mode.
`4. Proprietary differential input maintains excellent SNR
`performance for input frequencies up to 450 MHz.
`5. The AD9600 operates from a single 1.8 V supply and
`features a separate digital output driver supply to
`accommodate 1.8 V to 3.3 V logic families.
`6. A standard serial port interface supports various product
`features and functions, such as data formatting (offset
`binary, twos complement, or gray coding), enabling the
`clock DCS, power-down mode, and voltage reference mode.
`7. The AD9600 is pin compatible with the AD9627-11, AD9627,
`and AD9640, allowing a simple migration from 10 bits to
`11 bits, 12 bits, or 14 bits.
`
`FUNCTIONAL BLOCK DIAGRAM
`SCLK/
`SDIO/
`DFS
`DCS
`
`AVDD
`
`DVDD
`
`FD[0:3]A
`
`CSB
`
`DRVDD
`
`AD9600
`
`FD BITS/THRESHOLD
`DETECT
`
`SPI
`
`D9A
`
`D0A
`
`CLK+
`CLK–
`
`DCOA
`DCOB
`
`D9B
`
`D0B
`
`
`
`06909-001
`
`OUTPUT BUFFER
`
`CMOS/LVDS
`
`OUTPUT BUFFER
`
`CMOS/LVDS
`
`DRGND
`
`
`
`
`
`VIN + A
`
`VIN – A
`
`VREF
`SENSE
`
`CML
`
`VIN – B
`
`VIN + B
`
`SHA
`
`ADC
`
`– +
`
`REFERENCE
`SELECT
`
`SHA
`
`ADC
`
`PROGRAMMING DATA
`
`DIVIDE 1
`TO 8
`
`SIGNAL
`MONITOR
`
`DUTY CYCLE
`STABLIZER
`
`DCO
`GENERATION
`
`SERIAL MONITOR
`DATA
`
`MULTICHIP
`SYNC
`
`FD BITS/THRESHOLD
`DETECT
`
`SERIAL MONITOR
`INTERFACE
`
`AGND
`
`SYNC
`
`FD[0:3]B
`
`SMI
`SMI
`SCLK/
`SDO/
`PDWN
`OEB
`NOTES
`1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
`SEE FIGURE 7 FOR LVDS PIN NAMES.
`Figure 1.
`
`SMI
`SDFS
`
`Rev. B
`Information furnished by Analog Devices is believed to be accurate and reliable. However, no
`responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
`rights of third parties that may result from its use. Specifications subject to change without notice. No
`license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
`Trademarks and registered trademarks are the property of their respective owners.
`
`
`
`
`
`
`
`One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
`www.analog.com
`Tel: 781.329.4700
`Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`AD9600
`
`
`
`TABLE OF CONTENTS
`Features .............................................................................................. 1 
`Applications ....................................................................................... 1 
`Product Highlights ........................................................................... 1 
`Functional Block Diagram .............................................................. 1 
`Revision History ............................................................................... 3 
`General Description ......................................................................... 4 
`Specifications ..................................................................................... 5 
`DC Specifications ......................................................................... 5 
`AC Specifications .......................................................................... 6 
`Digital Specifications ................................................................... 7 
`Switching Specifications .............................................................. 9 
`Timing Characteristics .............................................................. 10 
`Timing Diagrams ........................................................................ 10 
`Absolute Maximum Ratings .......................................................... 12 
`Thermal Characteristics ............................................................ 12 
`ESD Caution ................................................................................ 12 
`Pin Configuration and Function Descriptions ........................... 13 
`Equivalent Circuits ......................................................................... 17 
`Typical Performance Characteristics ........................................... 18 
`Theory of Operation ...................................................................... 23 
`ADC Architecture ...................................................................... 23 
`Analog Input Considerations .................................................... 23 
`Voltage Reference ....................................................................... 25 
`Clock Input Considerations ...................................................... 26 
`Power Dissipation and Standby Mode ..................................... 28 
`Digital Outputs ........................................................................... 28 
`Timing .......................................................................................... 29 
`ADC Overrange and Gain Control .............................................. 30 
`Fast Detect Overview ................................................................. 30 
`ADC Fast Magnitude ................................................................. 30 
`ADC Overrange (OR) ................................................................ 31 
`Gain Switching ............................................................................ 31 
`Signal Monitor ................................................................................ 33 
`
`
`
`
`Peak Detector Mode................................................................... 33 
`RMS/MS Magnitude Mode ....................................................... 33 
`Threshold Crossing Mode ......................................................... 34 
`Additional Control Bits ............................................................. 34 
`DC Correction ............................................................................ 35 
`Signal Monitor SPORT Output ................................................ 35 
`Built-In Self-Test (BIST) and Output Test .................................. 36 
`Built-In Self-Test (BIST) ............................................................ 36 
`Output Test Modes ..................................................................... 36 
`Channel/Chip Synchronization .................................................... 37 
`Serial Port Interface (SPI) .............................................................. 38 
`Configuration Using the SPI ..................................................... 38 
`Hardware Interface ..................................................................... 38 
`Configuration Without the SPI ................................................ 39 
`SPI Accessible Features .............................................................. 39 
`Memory Map .................................................................................. 40 
`Reading the Memory Map Table .............................................. 40 
`Memory Map .............................................................................. 41 
`Memory Map Register Description ......................................... 44 
`Applications Information .............................................................. 47 
`Design Guidelines ...................................................................... 47 
`Evaluation Board ............................................................................ 48 
`Power Supplies ............................................................................ 48 
`Input Signals................................................................................ 48 
`Output Signals ............................................................................ 48 
`Default Operation and Jumper Selection Settings ................. 49 
`Alternative Clock Configurations ............................................ 49 
`Alternative Analog Input Drive Configuration...................... 50 
`Schematics ................................................................................... 51 
`Evaluation Board Layouts ......................................................... 61 
`Bill of Materials ........................................................................... 69 
`Outline Dimensions ....................................................................... 71 
`Ordering Guide .......................................................................... 72 
`
`Rev. B | Page 2 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`
`
`
`REVISION HISTORY
`12/09—Rev. A to Rev. B
`Added new models to Specifications Section ................................ 5
`Changes to Table 7 .......................................................................... 12
`Updated Outline Dimensions ........................................................ 71
`Changes to Ordering Guide ........................................................... 72
`6/09—Rev. 0 to Rev. A
`Changes to Specifications Section ................................................... 4
`Changes to Figure 3 ......................................................................... 10
`Changes to Figure 11, Figure 12, and Figure 14 .......................... 16
`Changes to Table 12 ........................................................................ 28
`
`
`AD9600
`
`Changes to Configuration Using the SPI Section ....................... 37
`Changes to Table 22 ........................................................................ 40
`Changes to Signal Monitor Period (Register 0x113 to
`Register 0x115) Section .................................................................. 45
`Added Exposed Pad Notation to Outline Dimensions .............. 70
`11/07—Revision 0: Initial Version
`
`Rev. B | Page 3 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`AD9600
`
`
`
`GENERAL DESCRIPTION
`The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS
`ADC. It is designed to support communications applications
`where low cost, small size, and versatility are desired.
`The dual ADC core features a multistage, differential pipelined
`architecture with integrated output error correction logic. Each
`ADC features wide bandwidth, differential sample-and-hold
`analog input amplifiers supporting a variety of user-selectable
`input ranges. An integrated voltage reference eases design
`considerations. A duty cycle stabilizer is provided to compen-
`sate for variations in the ADC clock duty cycle, allowing the
`converters to maintain excellent performance.
`The AD9600 has several functions that simplify the automated
`gain control (AGC) function in a communications receiver. For
`example, the fast detect feature allows fast overrange detection
`by outputting four bits of input level information with very
`short latency.
`
`
`
`
`In addition, the programmable threshold detector allows moni-
`toring the amplitude of the incoming signal with short latency,
`using the four fast detect bits of the ADC. If the input signal level
`exceeds the programmable threshold, the fine upper threshold
`indicator goes high. Because this threshold is set from the four
`MSBs, the user can quickly adjust the system gain to avoid an
`overrange condition.
`Another AGC-related function of the AD9600 is the signal
`monitor. This block allows the user to monitor the composite
`magnitude of the incoming signal, which aids in setting the gain
`to optimize the dynamic range of the overall system.
`The ADC output data can be routed directly to the two external
`10-bit output ports. These outputs can be set from 1.8 V to 3.3 V
`CMOS or 1.8 V LVDS. In addition, flexible power-down options
`allow significant power savings.
`
`Rev. B | Page 4 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`
`
`AD9600
`
`
`
`SPECIFICATIONS
`DC SPECIFICATIONS
`AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
`DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
`
`Table 1.
`
`Parameter
`RESOLUTION
`ACCURACY
`No Missing Codes
`Offset Error
`Gain Error
`Differential Nonlinearity (DNL)1
`
`
`
`Integral Nonlinearity (INL)1
`
`
`MATCHING CHARACTERISTICS
`Offset Error
`Gain Error
`TEMPERATURE DRIFT
`Offset Error
`Gain Error
`INTERNAL VOLTAGE REFERENCE
`Output Voltage Error (1 V Mode)
`Load Regulation @ 1.0 mA
`INPUT-REFERRED NOISE
`VREF = 1.0 V
`ANALOG INPUT
`Input Span, VREF = 1.0 V
`Input Capacitance2
`VREF INPUT RESISTANCE
`POWER SUPPLIES
`Supply Voltage
`AVDD, DVDD
`DRVDD (CMOS Mode)
`Supply Current
`
`IAVDD1
`
`IDVDD1
`IAVDD and IDVDD1, 3
`
`IDRVDD (3.3 V CMOS)
`IDRVDD (1.8 V CMOS)
`IDRVDD (1.8 V LVDS)
`POWER CONSUMPTION
`DC Input
`Sine Wave Input1
`DRVDD = 1.8 V
`DRVDD = 3.3 V
`Standby Power3
`Power-Down Power
`
`Temp
`Full
`
`Full
`Full
`Full
`Full
`25°C
`Full
`25°C
`
`Full
`Full
`
`Full
`Full
`
`Full
`Full
`
`25°C
`
`Full
`Full
`Full
`
`
`Full
`Full
`
`Full
`Full
`
`Full
`Full
`
`
`Full
`
`Full
`Full
`Full
`Full
`
`AD9600ABCPZ-105/
`AD9600BCPZ-105
`Min
`Typ
`Max
`10
`
`
`
`
`
`Guaranteed
`±0.3
`±0.7
`−2.2
`−1.0
`
`±0.2
`±0.1
`
`
`±0.3
`±0.1
`
`
`
`±0.3
`±0.7
`±0.2
`±0.8
`
`
`±15
`
`±95
`
`
`
`±5
`±16
`7
`
`
`
`0.1
`
`
`2
`8
`6
`
`1.8
`3.3
`
`310
`34
`
`35
`15
`42
`
`
`
`1.9
`3.6
`
`
`
`365
`
`600
`
`650
`
`645
`740
`68
`2.5
`
`6
`
`
`−3.6
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1.7
`1.7
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`AD9600ABCPZ-125/
`AD9600BCPZ-125
`Min
`Typ
`Max
`10
`
`
`
`
`
`Guaranteed
`±0.3
`±0.7
`−2.5
`−1.3
`
`±0.2
`±0.1
`
`
`±0.3
`±0.1
`
`
`
`±0.3
`±0.7
`±0.3
`±0.8
`
`
`±15
`
`±95
`
`
`
`±5
`±16
`7
`
`
`
`0.1
`
`
`
`2
`
`8
`
`6
`
`
`
`
`
`1.8
`1.9
`3.3
`3.6
`
`
`385
`
`42
`
`
`455
`36
`
`18
`
`44
`
`
`
`750
`800
`
`
`813
`
`900
`
`77
`
`2.5
`6
`
`
`−4.0
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1.7
`1.7
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`AD9600ABCPZ-150/
`AD9600BCPZ-150
`Min
`Typ
`Max
`10
`
`
`
`
`
`Guaranteed
`±0.3
`±0.7
`−3.0
`−1.6
`
`±0.2
`±0.1
`
`
`±0.4
`±0.1
`
`
`
`±0.2
`±0.7
`±0.2
`±0.8
`
`
`±15
`
`±95
`
`
`
`±5
`±16
`7
`
`
`
`0.1
`
`
`
`2
`
`8
`
`6
`
`
`
`
`
`1.8
`1.9
`3.3
`3.6
`
`
`419
`
`50
`
`
`495
`42
`
`22
`
`46
`
`
`
`825
`890
`
`
`892
`
`990
`
`77
`
`2.5
`6
`
`
`−4.3
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1.7
`1.7
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Unit
`Bits
`
`
`% FSR
`% FSR
`LSB
`LSB
`LSB
`LSB
`
`% FSR
`% FSR
`
`ppm/°C
`ppm/°C
`
`mV
`mV
`
`LSB rms
`
`V p-p
`pF
`kΩ
`
`
`V
`V
`
`mA
`mA
`
`mA
`mA
`mA
`
`mW
`
`mW
`mW
`mW
`mW
`
` 1
`
` Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
`2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure.
`3 Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND.
`
`
`Rev. B | Page 5 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`AD9600
`
`
`
`
`AC SPECIFICATIONS
`AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
`enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
`
`Table 2.
`
`Parameter1
`SIGNAL-TO-NOISE RATIO (SNR)
`fIN = 2.3 MHz
`fIN = 70 MHz
`
`fIN = 140 MHz
`fIN = 220 MHz
`SIGNAL-TO-NOISE AND DISTORTION (SINAD)
`fIN = 2.3 MHz
`fIN = 70 MHz
`
`fIN = 140 MHz
`fIN = 220 MHz
`EFFECTIVE NUMBER OF BITS (ENOB)
`fIN = 2.3 MHz
`fIN = 70 MHz
`fIN = 140 MHz
`fIN = 220 MHz
`WORST SECOND OR THIRD HARMONIC
`fIN = 2.3 MHz
`fIN = 70 MHz
`
`fIN = 140 MHz
`fIN = 220 MHz
`SPURIOUS-FREE DYNAMIC RANGE (SFDR)
`fIN = 2.3 MHz
`fIN = 70 MHz
`
`fIN = 140 MHz
`fIN = 220 MHz
`WORST OTHER HARMONIC OR SPUR
`fIN = 2.3 MHz
`fIN = 70 MHz
`
`fIN = 140 MHz
`fIN = 220 MHz
`TWO-TONE SFDR
`fIN = 29.1 MHz, 32.1 MHz (−7 dBFS )
`fIN = 169.1 MHz, 172.1 MHz (−7 dBFS )
`CROSSTALK2
`ANALOG INPUT BANDWIDTH
`
`Temp
`
`25°C
`25°C
`Full
`25°C
`25°C
`
`25°C
`25°C
`Full
`25°C
`25°C
`
`25°C
`25°C
`25°C
`25°C
`
`25°C
`25°C
`Full
`25°C
`25°C
`
`25°C
`25°C
`Full
`25°C
`25°C
`
`25°C
`25°C
`Full
`25°C
`25°C
`
`25°C
`25°C
`Full
`25°C
`
`AD9600ABCPZ-150/
`AD9600ABCPZ-125/
`AD9600ABCPZ-105/
`AD9600BCPZ-150
`AD9600BCPZ-125
`AD9600BCPZ-105
`Min
`Typ Max Min
`Typ Max Min
`Typ Max
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`60.3
`
`60.3
`
`60.3
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`60.1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`72.0
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`60.2
`
`
`
`
`
`
`
`
`
`60.6
`60.6
`
`60.6
`60.5
`
`60.5
`60.5
`
`60.5
`60.4
`
`9.9
`9.9
`9.9
`9.9
`
`−86.5
`−85.0
`
`−84.0
`−83.0
`
`85.5
`85.0
`
`84.0
`81.0
`
`−92
`-88
`
`−86
`−86
`
`84
`82
`95
`650
`
`
`
`−72.0
`
`−81
`
`Unit
`
`dB
`dB
`dB
`dB
`dB
`
`dB
`dB
`dB
`dB
`dB
`
`Bits
`Bits
`Bits
`Bits
`
`dBc
`dBc
`−72.0 dBc
`dBc
`dBc
`
`
`
`dBc
`dBc
`dBc
`dBc
`dBc
`
`dBc
`dBc
`dBc
`dBc
`dBc
`
`dBc
`dBc
`dB
`MHz
`
`−80
`
`
`60.6
`60.6
`
`60.5
`60.4
`
`60.5
`60.5
`
`60.4
`60.3
`
`9.9
`9.9
`9.9
`9.9
`
`−88.5
`−84.0
`
`−83.5
`−77
`
`85.5
`84.0
`
`83.5
`77
`
`−92
`−88
`
`−86
`−86
`
`84
`82
`95
`650
`
`
`60.7
`60.6
`
`60.6
`60.5
`
`60.6
`60.5
`
`60.5
`60.4
`
`9.9
`9.9
`9.9
`9.9
`
`
`
`
`
`60.2
`
`
`
`
`
`−72.0
`
`−87.0
`−85.0
`
`−84.0
`−83.0
`
`85.5
`85.0
`
`83.0
`81.0
`
`−92
`−88
`
`−86
`−86
`
`84
`82
`95
`650
`
`72.0
`
`72.0
`
`
`
`−81
`
`
`
` 1
`
` See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
`2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.
`
`
`Rev. B | Page 6 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`
`
`AD9600
`
`
`DIGITAL SPECIFICATIONS
`AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS
`enabled, unless otherwise noted.
`
`Table 3.
`Parameter
`DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
`Logic Compliance
`Internal Common-Mode Bias
`Differential Input Voltage
`Input Voltage Range
`Input Common-Mode Range
`High Level Input Voltage
`Low Level Input Voltage
`High Level Input Current
`Low Level Input Current
`Input Capacitance
`Input Resistance
`SYNC INPUT
`Logic Compliance
`Internal Bias
`Input Voltage Range
`High Level Input Voltage
`Low Level Input Voltage
`High Level Input Current
`Low Level Input Current
`Input Capacitance
`Input Resistance
`LOGIC INPUT (CSB)1
`High Level Input Voltage
`Low Level Input Voltage
`High Level Input Current
`Low Level Input Current
`Input Resistance
`Input Capacitance
`LOGIC INPUT (SCLK/DFS)2
`High Level Input Voltage
`Low Level Input Voltage
`High Level Input Current (VIN = 3.3 V)
`Low Level Input Current
`Input Resistance
`Input Capacitance
`LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1
`High Level Input Voltage
`Low Level Input Voltage
`High Level Input Current
`Low Level Input Current
`Input Resistance
`Input Capacitance
`
`Temperature
`
`
`Full
`Full
`Full
`Full
`Full
`Full
`Full
`Full
`Full
`Full
`
`
`Full
`Full
`Full
`Full
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`Full
`Full
`
`Rev. B | Page 7 of 72
`
`Min
`
`
`
`0.2
`GND − 0.3
`1.1
`1.2
`0
`−10
`−10
`
`8
`
`
`
`
`
`GND − 0.3
`1.2
`0
`−10
`−10
`
`8
`
`1.22
`0
`−10
`40
`
`
`
`1.22
`0
`−92
`−10
`
`
`
`1.22
`0
`−10
`38
`
`
`
`Max
`Typ
`
`
`CMOS/LVDS/LVPECL
`1.2
`
`
`6
`
`AVDD + 1.6
`
`AVDD
`
`3.6
`
`0.8
`
`+10
`
`+10
`4
`
`10
`12
`
`
`CMOS
`1.2
`
`
`
`
`
`4
`10
`
`
`
`
`
`26
`2
`
`
`
`
`
`26
`2
`
`
`
`
`
`26
`5
`
`Unit
`
`
`V
`V p-p
`V
`V
`V
`V
`μA
`μA
`pF
`kΩ
`
`
`V
`V
`V
`V
`μA
`μA
`pF
`kΩ
`
`V
`V
`μA
`μA
`kΩ
`pF
`
`V
`V
`μA
`μA
`kΩ
`pF
`
`V
`V
`μA
`μA
`kΩ
`pF
`
`
`
`
`AVDD + 1.6
`3.6
`0.8
`+10
`+10
`
`12
`
`3.6
`0.6
`+10
`132
`
`
`
`3.6
`0.6
`−135
`+10
`
`
`
`3.6
`0.6
`+10
`128
`
`
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`Temperature
`
`Full
`Full
`Full
`Full
`Full
`Full
`
`
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`
`Min
`
`1.22
`0
`−90
`−10
`
`
`
`
`3.29
`3.25
`
`
`
`1.79
`1.75
`
`
`
`250
`1.15
`150
`1.15
`
`Typ
`
`
`
`
`
`26
`5
`
`
`
`
`
`
`
`
`
`
`
`
`350
`1.25
`200
`1.25
`
`Max
`
`3.6
`0.6
`−134
`+10
`
`
`
`
`
`
`0.2
`0.05
`
`
`
`0.2
`0.05
`
`450
`1.35
`280
`1.35
`
`
`
`Unit
`
`V
`V
`μA
`μA
`kΩ
`pF
`
`
`V
`V
`V
`V
`
`V
`V
`V
`V
`
`mV
`V
`mV
`V
`
`AD9600
`
`
`Parameter
`LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2
`High Level Input Voltage
`Low Level Input Voltage
`High Level Input Current (VIN = 3.3 V)
`Low Level Input Current
`Input Resistance
`Input Capacitance
`DIGITAL OUTPUTS
`CMOS Mode—DRVDD = 3.3 V
`High Level Output Voltage (IOH = 50 μA)
`High Level Output Voltage (IOH = 0.5 mA)
`Low Level Output Voltage (IOL = 1.6 mA)
`Low Level Output Voltage (IOL = 50 μA)
`CMOS Mode—DRVDD = 1.8 V
`High Level Output Voltage (IOH = 50 μA)
`High Level Output Voltage (IOH = 0.5 mA)
`Low Level Output Voltage (IOL = 1.6 mA)
`Low Level Output Voltage (IOL = 50 μA)
`LVDS Mode—DRVDD = 1.8 V
`Differential Output Voltage (VOD), ANSI Mode
`Output Offset Voltage (VOS), ANSI Mode
`Differential Output Voltage (VOD), Reduced Swing Mode
`Output Offset Voltage (VOS), Reduced Swing Mode
`
` 1
`
` Pull up.
`2 Pull down.
`
`
`Rev. B | Page 8 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`
`
`AD9600
`
`
`SWITCHING SPECIFICATIONS
`AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS
`enabled, unless otherwise noted.
`
`Table 4.
`
`Parameter
`CLOCK INPUT PARAMETERS
`Input Clock Rate
`Conversion Rate
`DCS Enabled
`DCS Disabled
`CLK Period (tCLK)
`CLK Pulse Width High
`Divide-by-1 Mode,
`DCS Enabled
`Divide-by-1 Mode,
`DCS Disabled
`Divide-by-2 Mode,
`DCS Enabled
`Divide-by-3 Through Divide-
`by-8 Modes, DCS Enabled
`DATA OUTPUT PARAMETERS
`CMOS Mode—DRVDD = 3.3 V
`Data Propagation Delay (tPD)1
`DCO Propagation Delay (tDCO)
`Setup Time (tS)
`Hold Time (tH)
`CMOS Mode—DRVDD = 1.8 V
`Data Propagation Delay (tPD)1
`DCO Propagation Delay (tDCO)
`Setup Time (tS)
`Hold Time (tH)
`LVDS Mode—DRVDD = 1.8 V
`Data Propagation Delay (tPD)1
`DCO Propagation Delay (tDCO)
`CMOS Mode Pipeline Delay
`(Latency)
`LVDS Mode Pipeline Delay
`(Latency) Channel A/Channel B
`Aperture Delay (tA)
`Aperture Uncertainty (Jitter, tJ)
`Wake-Up Time2
`OUT-OF-RANGE RECOVERY TIME
`
`AD9600ABCPZ-150/
`AD9600ABCPZ-125/
`AD9600ABCPZ-105/
`AD9600BCPZ-150
`AD9600BCPZ-125
`AD9600BCPZ-105
`Min
`Typ
`Max Min
`Typ
`Max Min
`Typ
`Max
`
`
`
`
`
`
`
`
`
`
`
`625
`
`
`625
`
`
`625
`
`
`
`
`
`
`
`
`
`20
`
`105
`20
`
`125
`20
`
`150
`10
`
`105
`10
`
`125
`10
`
`150
`9.5
`
`
`8
`
`
`6.66
`
`
`
`
`
`
`
`
`
`
`
`2.85
`4.75
`6.65
`2.4
`4
`5.6
`2.0
`3.33
`4.66
`
`Temp
`
`Full
`
`Full
`Full
`Full
`
`Full
`
`Full
`
`Full
`
`Full
`
`
`
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`
`Full
`
`Full
`Full
`Full
`Full
`
`4.28
`
`4.75
`
`5.23
`
`1.6
`
`0.8
`
`
`
`2.2
`3.8
`
`
`
`2.4
`4.0
`
`
`
`3.0
`5.2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`4.5
`5.0
`5.25
`4.25
`
`5.2
`5.6
`5.25
`4.25
`
`3.7
`6.4
`12
`
`12/12.5
`
`1.0
`0.1
`350
`2
`
`
`
`
`
`
`
`6.4
`6.8
`
`
`
`6.9
`7.3
`
`
`
`4.4
`7.6
`
`
`
`
`
`
`
`
`
`3.6
`
`1.6
`
`0.8
`
`
`
`2.2
`3.8
`
`
`
`2.4
`4.0
`
`
`
`3.0
`5.0
`
`
`
`
`
`
`
`
`
`4
`
`
`
`
`
`
`
`4.5
`5.0
`4.5
`3.5
`
`5.2
`5.6
`4.5
`3.5
`
`3.8
`6.2
`12
`
`12/12.5
`
`1.0
`0.1
`350
`3
`
`4.4
`
`
`
`
`
`
`
`6.4
`6.8
`
`
`
`6.9
`7.3
`
`
`
`4.5
`7.4
`
`
`
`
`
`
`
`
`
`3.0
`
`1.6
`
`0.8
`
`
`
`2.2
`3.8
`
`
`
`2.4
`4.0
`
`
`
`3.0
`4.8
`
`
`
`
`
`
`
`
`
`3.33
`
`3.66
`
`
`
`
`
`
`
`4.5
`5.0
`3.83
`2.83
`
`5.2
`5.6
`3.83
`2.83
`
`3.8
`5.9
`12
`
`12/12.5
`
`1.0
`0.1
`350
`3
`
`
`
`
`
`
`
`6.4
`6.8
`
`
`
`6.9
`7.3
`
`
`
`4.5
`7.3
`
`
`
`
`
`
`
`
`
`
`Unit
`
`MHz
`
`MSPS
`MSPS
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`
`
`ns
`ns
`ns
`ns
`
`ns
`ns
`ns
`ns
`
`ns
`ns
`Cycles
`
`Cycles
`
`ns
`ps rms
`μs
`Cycles
`
` 1
`
` Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load.
`2 Wake-up time is dependent on the value of the decoupling capacitors.
`
`
`Rev. B | Page 9 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`AD9600
`
`
`TIMING CHARACTERISTICS
`
`Table 5.
`Parameter
`SYNC TIMING REQUIREMENTS
`tSSYNC
`tHSYNC
`SPI TIMING REQUIREMENTS
`tDS
`tDH
`tCLK
`tS
`tH
`tHIGH
`tLOW
`tEN_SDIO
`
`tDIS_SDIO
`
`SPORT TIMING REQUIREMENTS
`tCSSCLK
`tSSCLKSDO
`tSSCLKSDFS
`
`
`TIMING DIAGRAMS
`
`Conditions
`
`Setup time between SYNC and the rising edge of CLK+
`Hold time between SYNC and the rising edge of CLK+
`
`Setup time between the data and the rising edge of SCLK
`Hold time between the data and the rising edge of SCLK
`Period of the SCLK
`Setup time between CSB and SCLK
`Hold time between CSB and SCLK
`SCLK pulse width high
`SCLK pulse width low
`Time required for the SDIO pin to switch from an input to an output
`relative to the SCLK falling edge
`Time required for the SDIO pin to switch from an output to an input
`relative to the SCLK rising edge
`
`Delay from the rising edge of CLK+ to the rising edge of SMI SCLK
`Delay from the rising edge of SMI SCLK to SMI SDO
`Delay from the rising edge of SMI SCLK to SMI SDFS
`
`Min
`
`
`
`
`2
`2
`40
`2
`2
`10
`10
`10
`
`Typ Max
`
`
`0.24
`
`0.40
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`
`
`
`
`
`3.2
`−0.4
`−0.4
`
`
`4.5
`0
`0
`
`
`6.2
`0.4
`0.4
`
`
`
`Unit
`
`ns
`ns
`
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`
`ns
`
`
`ns
`ns
`ns
`
`N + 1
`
`N + 2
`
`N + 3
`
`N
`
`tA
`
`tCLK
`
`tPD
`
`N + 4
`
`N + 5
`
`N + 6
`
`N + 7
`
`N + 8
`
`
`
`06909-012
`
`N – 13
`
`N – 12
`
`N – 11
`
`N – 10
`
`N – 9
`
`N – 8
`
`N – 7
`
`N – 6
`
`N – 5
`
`N – 4
`
`N – 3
`tS
`
`N – 2
`
`N – 1
`
`N
`
`N + 1
`
`N + 2
`
`N + 3
`
`N + 4
`
`N + 5
`
`N + 6
`
`tH
`
`tDCO
`
`tCLK
`
`Figure 2. CMOS Output Mode Data and Fast Detect Output Timing
`
`CLK+
`
`CLK–
`
`CH A/CH B DATA
`
`CH A/CH B FAST
`DETECT
`
`DCOA/DCOB
`
`
`
`Rev. B | Page 10 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`AD9600
`
`
`
`
`
`N + 1
`
`N + 2
`
`N + 3
`
`N
`
`tA
`
`CLK+
`
`CLK–
`
`tCLK
`
`tPD
`
`N + 4
`
`N + 5
`
`N + 6
`
`N + 7
`
`N + 8
`
`CH A/CH B DATA
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`N – 13
`
`N – 12
`
`N – 11
`
`N – 10
`
`N – 9
`
`N – 8
`
`N – 7
`
`N – 6
`
`N – 5
`
`N – 4
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`CH A/CH B FAST
`DETECT
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`B
`
`A
`
`
`
`06909-089
`
`N – 7
`
`N – 6
`
`N – 5
`
`N – 4
`
`N – 2
`
`N – 3
`tDCO
`
`N – 1
`tCLK
`
`N
`
`N + 1
`
`N + 2
`
`DCO+
`
`DCO–
`
`Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
`
`tSSYNC
`
`tHSYNC
`
`
`
`06909-072
`
`Figure 4. SYNC Input Timing Requirements
`
`CLK+
`
`SYNC
`
`tCSSCLK
`
`tSSCLKSDFS
`
`tSSCLKSDO
`
`
`
`06909-082
`
`DATA
`
`DATA
`
`Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)
`
`
`
`
`
`
`
`CLK+
`
`CLK–
`
`SMI SCLK/PDWN
`
`SMI SDFS
`
`SMI SDO/OEB
`
`Rev. B | Page 11 of 72
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`
`
`Unit
`°C/W
`°C/W
`
`°C/W
`
`
`
`
`THERMAL CHARACTERISTICS
`The exposed paddle must be soldered to the ground plane for
`the LFCSP package. Soldering the exposed paddle to the
`customer board increases the reliability of the solder joints,
`maximizing the thermal capability of the package.
`
`Table 7. Thermal Resistance
`Airflow
`Velocity
`(m/s)
`0
`1.0
`
`Package Type
`64-Lead, 9 mm × 9 mm
`LFCSP (CP-64-3,
`CP-64-6)
`
`θJA
`1, 2
`18.8
`16.5
`
`θJC1, 3
`
`0.6
`
`
`θJB1, 4
`
`6.0
`
`
`
`
`2.0
`
`15.8
`
`
`
`
`
` 1
`
` Per JEDEC 51-7 standard and JEDEC 25-5 2S2P test board.
`2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
`3 Per MIL-Std 883, Method 1012.1.
`4 Per JEDEC JESD51-8 (still air).
`
`Typical θJA and θJC are specified for a 4-layer board in still air.
`Airflow increases heat dissipation, effectively reducing θJA. In
`addition, metal (such as metal traces through holes, ground,
`and power planes) that is in direct contact with the package
`leads reduces the θJA.
`ESD CAUTION
`
`
`
`
`
`
`
`
`
`
`
`
`
` 1
`
` The output data pins are D0A/D0B to D9A/D9B for the CMOS configuration
`and D0+/D0− to D9+/D9− for the LVDS configuration.
`2 The fast detect output pins are FD0A/FD0B to FD3A/FD3B for the CMOS
`configuration and FD0+/FD0− to FD3+/FD3−.
`3 The data clock output pins are DCOA and DCOB for the CMOS configuration
`and DCO+ and DCO− for the LVDS configuration.
`
`
`Stresses above those listed under Absolute Maximum Ratings
`may cause permanent damage to the device. This is a stress
`rating only; functional operation of the device at these or any
`other conditions above those indicated in the operational
`section of this specification is not implied. Exposure to absolute
`maximum rating conditions for extended periods may affect
`device reliability.
`
`
`
`Rev. B | Page 12 of 72
`
`AD9600
`
`
`
`ABSOLUTE MAXIMUM RATINGS
`Table 6.
`Parameter
`ELECTRICAL
`AVDD, DVDD to AGND
`DRVDD to DRGND
`AGND to DRGND
`AVDD to DRVDD
`VIN + A/VIN + B, VIN − A/VIN − B to
`AGND
`CLK+, CLK− to AGND
`SYNC to AGND
`VREF to AGND
`SENSE to AGND
`CML to AGND
`RBIAS to AGND
`CSB to AGND
`SCLK/DFS to DRGND
`SDIO/DCS to DRGND
`SMI SDO/OEB
`SMI SCLK/PDWN
`SMI SDFS
`Output Data Pins to DRGND1
`Fast Detect Output Pins to DRGND2
`Data Clock Output Pins to DRGND3
`ENVIRONMENTAL
`Operating Temperature Range
`(Ambient)
`Maximum Junction Temperature
`Under Bias
`Storage Temperature Range
`(Ambient)
`
`Rating
`
`−0.3 V to +2.0 V
`−0.3 V to +3.9 V
`−0.3 V to +0.3 V
`−3.9 V to +2.0 V
`−0.3 V to AVDD + 0.2 V
`
`−0.3 V to +3.9 V
`−0.3 V to +3.9 V
`−0.3 V to AVDD + 0.2 V
`−0.3 V to AVDD + 0.2 V
`−0.3 V to AVDD + 0.2 V
`−0.3 V to AVDD + 0.2 V
`−0.3 V to +3.9 V
`−0.3 V to +3.9 V
`−0.3 V to DRVDD + 0.3 V
`−0.3 V to DRVDD + 0.3 V
`−0.3 V to DRVDD + 0.3 V
`−0.3 V to DRVDD + 0.3 V
`−0.3 V to DRVDD + 0.3 V
`−0.3 V to DRVDD + 0.3 V
`−0.3 V to DRVDD + 0.3 V
`
`−40°C to +85°C
`
`150°C
`
`−65°C to +150°C
`
`ADVANCED ENERGY INDUSTRIES INC.
`Exhibit 1020
`
`

`

`
`
`
`
`PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
`
`
`AD9600
`
`48
`47
`46
`45
`44
`43
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`
`SCLK/DFS
`SDIO/DCS
`AVDD
`AVDD
`VIN + B
`VIN – B
`RBIAS
`CML
`SENSE
`VREF
`VIN – A
`VIN + A
`AVDD
`SMI SDFS
`SMI SCLK/PDWN
`SMI SDO/OEB
`
`CLK+
`CLK–
`CSB
`SYNC
`FD0B
`FD1B
`FD2B
`FD3B
`DVDD
`DNC
`DNC
`DNC
`DNC
`D0B (LSB)
`D1B
`DRGND
`
`49
`50
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`
`PIN 1
`INDICATOR
`
`EXPOSED PADDLE, PIN 0
`(BOTTOM OF PACKAGE)
`
`AD9600
`PARALLEL CMOS
`TOP VIEW
`(Not to Scale)
`
`123456789
`
`10
`11
`12
`13
`14
`15
`16
`
`DRVDD
`D2B
`D3B
`D4B
`D5B
`D6B
`D7B
`D8B
`(MSB) D9B
`DCOB
`DCOA
`DNC
`DNC
`DNC
`DNC
`(LSB) D0A
`
`32
`31
`30
`29
`28
`27
`26
`25
`24
`23
`22
`21
`20
`19
`18
`17
`
`
`
`06909-002
`
`FD3A
`FD2A
`FD1A
`FD0A
`(MSB) D9A
`D8A
`D7A
`D6A
`DVDD
`D5A
`D4A
`DRVDD
`DRGND
`D3A
`D2A
`D1A
`
`NOTES
`1. DNC = DO NOT CONNECT.
`2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
`ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
`GROUND FOR PROPER OPERATION.
`Figure 6. Parallel CMOS Mode Pin Configuration (Top View)
`
`
`
`Table 8. Parallel CMOS Mode Pin Function Descriptions
`Pin No.
`Mnemonic
`Type
`ADC Power Supplies
`
`
`20, 64
`DRGND
`Ground
`1, 21
`DRVDD
`Supply
`24, 57
`DVDD
`Supply
`36, 45, 46
`AVDD
`Supply
`0
`AGND
`Ground
`ADC Inputs
`
`
`37
`VIN + A
`Input
`38
`VIN − A
`Input
`44
`VIN + B
`Input
`43
`VIN − B
`Input
`39
`VREF
`I/O
`40
`SENSE
`Input
`42
`RBIAS
`Input
`41
`CML
`Output
`49
`CLK+
`Input
`
`50
`
`CLK−
`
`Input
`
`Description
`
`Digital Output Ground.
`Digital Output Driver Supply (1.8 V to 3.3 V).
`Digital Power Supply (1.8 V Nominal).
`Analog Power Supply (1.8 V Nominal).
`Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
`
`Differential Analog Input Pin (+) for Channel A.
`Differential Analog Input Pin (−) for Channel A.
`Differential Analog Input Pin (+) for Channel B.
`Differential Analog Input Pin (−) for Channel B.
`Voltage Reference Input/Output.
`Voltage Reference Mode Select (see Table 11 for details).
`External Reference Bias Resistor.
`Common-Mode Level Bias Output for Analog Inputs.
`ADC Master Clock True. The ADC clock can be driven using a single-ended
`CMOS (see Figure 60 and Figure 61 for the recommended connection).
`ADC Master Clock Complement. The ADC clock can be driven using a single-
`ended CMOS (see Figure 60 and Figure 61 for the recommended connectio