158
`
`IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO. 2, MAY 1996
`
`nchmarking Semiconductor Manufacturing
`
`Robert C. Leach” and David A. Hodges, Fellow, ZEEE
`
`Abstract- We are studying the manufacturing performance
`of semiconductor wafer fabrication plants in the US, Asia, and
`Europe. There are great similarities in production equipment,
`manufacturing processes, and products produced at these plants.
`Nevertheless, data reported here show that important quantita-
`tive measures of productivity vary by factors of 3 to as much as
`5 across an international sample of 16 plants.
`We conducted on-site interviews with manufacturing personnel
`to better understand reasons for the observed wide variations in
`productivity. We have identified factors in the areas of infor-
`mation systems, organizational practices, process and technology
`improvements, and production control that correlate strongly
`with productivity.
`
`I. INTRODUCTION
`HE Competitive Semiconductor Manufacturing (CSM)
`
`T Program at the University of California, Berkeley, since
`
`plant and equipment of $500M to $lB each. They are the most
`costly manufacturing plants found in any industry today. The
`knowledge and skills required for efficient wafer fabrication
`require further large, ongoing investments. Manufacturing
`process sequences are exceedingly complex, with 400 or more
`sequential operations on a wafer over a span of 20 to 60 24-h
`days. A gross failure at any step can render a wafer worthless.
`The salable fraction of the total number of chips on a finished
`wafer, known as the “chip yield,” varies from zero to loo%,
`depending on the effectiveness of quality control in avoiding
`localized defects on chips.
`Today’s principal VLSI products including memories, mi-
`croprocessors, digital signal processors, application-specific
`logic, etc. are manufactured worldwide using very similar
`manufacturing equipment and processes. In many cases, 5
`to 15 firms world-wide compete in selling interchangeable
`final products to hundreds of customers. Economic success
`in wafer fabrication clearly requires maximizing the output
`of salable products from a large fixed investment. Despite
`these obvious facts, there is an amazingly large variation
`in the manufacturing performance of semiconductor firms.
`The present study is intended to quantify and benchmark
`manufacturing performance and to identify superior practices
`in manufacturing technology, factory operation, organization,
`and management.
`Our study has addressed only the wafer fabrication element
`of the total semiconductor manufacturing cycle. This is the
`most complex and capital-intensive element. The technologies
`and processes of packaging semiconductor chips are, how-
`ever, growing in significance. Semiconductor packaging is the
`subject of a forthcoming report from another group [2].
`m. SOURCES OF DATA AND LIMITATIONS ON ITS DISCLOSURE
`The data and analysis summarized in this report derive from
`measurements of manufacturing performance and investigation
`of underlying determinants of performance at 16 wafer fabrica-
`tion facilities in the United States, Europe, Japan and Taiwan.
`The companies operating these manufacturing facilities are
`listed in Table I. In selecting participants, we sought access
`to plants representing a cross-section of the industry, both
`internationally and in terms of business models and product
`mix. We asked for access to plants that had been in operation
`for at least three years. Substantial effort is required on the
`part of each participant. Some of those approached declined
`to participate. Participants who operate several semiconductor
`manufacturing lines generally opened one of their best lines to
`this study. Firms participate based on written agreement that
`we mask the relationship between individual firms and plants.
`We report results only in anonymous or aggregated forms.
`0894-6507/96$05.00 0 1996 IEEE
`
`April 1991, has been conducting a detailed study of quality,
`productivity, and competitiveness in semiconductor manufac-
`turing worldwide. The program is a joint activity of the College
`of Engineering, the Haas School of Business, and the Berkeley
`Roundtable on the International Economy at Berkeley, under
`sponsorship of the Alfred P. Sloan Foundation, and with the
`cooperation of semiconductor producers from Asia, Europe
`and the United States. The authors of tbls paper are the
`project’s CO-Directors. Other contributors are named in the
`Acknowledgments. This article is based on data and analysis
`drawn from the continuing program [l].
`The CSM program is being conducted by faculty, graduate
`students and research staff from UC Berkeley’s schools of En-
`gineering and Business, and Department of Economics. Many
`of the participating firms are represented on the program’s
`Industry Advisory Board. The Board played an important role
`in defining the research agenda. A pilot study was conducted
`in 1991 with the cooperation of three semiconductor plants.
`The research plan and survey documents were thereby refined.
`The main phase of the CSM benchmarking study began in
`mid-1992 and will continue at least through 1997.
`
`11. FOCUS OF THIS STUDY
`Our study focuses on semiconductor wafer processing as
`needed to produce VLSI chips including memories, micro-
`processors, signal processors, other logic, and mixed-signal
`products. Wafer processing takes place in manufacturing plants
`known as “fabs”. Modern fabs require capital investment in
`
`Manuscript received March 3, 1995; revised December 9, 1995. This work
`was supported by a grant from the Alfred P. Sloan Foundation, New York, as
`a part of the Foundation’s program of Manufacturing Industry Studies.
`The authors are with the College of Engineering and the Engineering
`Systems Research Center, University of Califomia, Berkeley, CA 94720 USA.
`Publisher Item Identifier S 0894-6507(96)03273-3.
`
`Applied Materials, Inc. Ex. 1011
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 1 of 12
`
`

`

`LEACHMAN AND HODGES: BENCHMARKING SEMICONDUCTOR MANUFACTURING
`
`159
`
`TABLE I
`
`COMPANIES PARTICIPATING IN THE MAIN PHASE OF THE C O M P E ~ V E
`
`SEMICONDUCTOR MANUFACTURING SURVEY (FIRST 18 MONTHS)
`Advanced Micro Devices, Inc.
`Nihon Semiconductor, Inc.
`Cypress Semiconductor, Inc.
`NEC Corp.
`Oki Electric Industry, Ltd.
`Delco Electronics, Inc.
`Silicon Systems, Inc.
`Digital Equipment Corp. (2 sites)
`Taiwan Semiconductor Mfg.
`Intel Corporation
`Texas Instruments, Inc.
`Intemational Business Machines, Inc.
`ITT Intermetall
`Toshiba Corp.
`LSI Logic. Corp
`
`The Berkeley team signs nondisclosure agreements with all
`participating firms.
`As the first step, participants complete a 70-page mail-out
`questionnaire (MOQ), reporting data concerning clean room
`size and class, staffing levels, equipment counts, wafer starts,
`die yields, line yields, cycle times, manufacturing systems,
`etc. over the last four years. From the completed MOQ’s, we
`calculate technical metrics of manufacturing performance for
`each participant. We then rank the participants for each of the
`metrics.
`We observed a great variation in the scores. In an attempt
`to understand the factors that account for performance dif-
`ferences, we conduct a two-day visit at each participating
`site. We tour the manufacturing line, interview a cross-section
`of the staff, and hold a series of sessions to determine the
`fab’s strategies for improving manufacturing performance.
`We assess each fab’s resources for improvement including
`computer integrated manufacturing (CIM) and information
`systems, human resources development, deployment of work
`groups and teams, etc. These more qualitative evaluations of
`participants’ operational practices are then correlated with the
`performance metrics to identify those practices that underlie
`top performance.
`
`Iv. METRICS OF MANUFACTURING PERFORMANCE
`The technical metrics we use to measure manufacturing
`performance of the participants are defined as follows:
`1) Cycle time per wafer layer measures the duration, ex-
`pressed in fractional working days, consumed by pro-
`duction lots of wafers from the time of release into the
`fab until time of exit from the fab, divided by the number
`of masking layers. The participants report cycle times
`for each of several process flows they may operate; we
`compute a weighted average cycle time per layer for the
`fab, where the weights are the number of wafer starts in
`each process flow.
`2) Line yield measures the fraction of wafers started that
`emerge from the fab as completed wafers ready for
`electrical testing of the individual circuits on the wafer.
`In monthly periods, the participants report line yield for
`each of their process flows, calculated as
`
`where WO is the number of wafers completed during
`the month and SC is the number of wafers scrapped
`during the month. We normalize the reported line yields
`
`into scores expressing the line yield per ten wafer layers
`using the formula
`Lyle = L y ( l O / M L )
`where LY is the reported line yield, ML is the number
`of masking layers, and LY 10 is the calculated line yield
`per ten layers. We then compute a weighted average line
`yield per ten layers for the fab, where the weight for each
`process flow is the number of wafer starts of the flow.
`Die yield expresses the fraction of the total whole die on
`a completed wafer that pass the electrical probe test. The
`participants report their die yields for the highest volume
`product in each of their process flows. For memory
`products, the reported die yield is that after laser repair.
`We convert the reported die yield into a defect density
`using the Murphy model
`Y = ((1 - e-AD)/AD}2
`where Y is the reported die yield, A is the die area
`in square centimeters, and D is the calculated defect
`density, expressed as defects per square centimeter. The
`calculated defect densities account for all yield losses
`remaining after repair, including spot defects, parametric
`problems, and any other losses. We compare defect den-
`sity scores of the participants only after sorting process
`flows into memory and logic groups that are further
`categorized by the minimum geometry achievable with
`the flow.
`Stepper productivity expresses the number of wafer
`layers completed per 5X stepper per calendar day (con-
`sidering only layers exposed using 5X steppers). We
`estimate the number of wafer operations in a process
`flow performed per calendar day by 5X steppers using
`the formula
`
`SL = (WS/7)(NL)(LY’)
`where SL is the calculated number of 5X stepper oper-
`ations per day, WS is the reported average number of
`wafer starts per week in the process flow, NL is the num-
`ber of masking layers in the process flow performed on
`5X steppers, and LY’ is an inflated line yield computed
`as
`LY’ = (1.0 + LY)/2
`where LY is the reported line yield for the process flow.
`(This inflated line yield allows for half of the total line
`yield loss to load 5X steppers, or equivalently, it assumes
`the average wafer that is scrapped makes it through half
`the 5X layers before being discarded.) The calculated
`5X stepper operations per day for all process flows are
`summed, then divided by the number of 5X steppers
`present in the fab to obtain the value of the metric.
`While participants processing a wide variety of prod-
`ucts must change reticles more frequently than those
`producing only a few products, we observed that some
`participants have automated reticle changes to the point
`that there is almost no lost time on their 5X steppers
`when they change reticles. We therefore make no al-
`
`Applied Materials, Inc. Ex. 1011
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 2 of 12
`
`

`

`IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO. 2, MAY 1996
`
`I
`1988
`
`I
`1989
`
`I
`I990
`
`1
`1991
`
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`1992
`
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`
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`1993
`
`I
`1994
`
`I
`1995
`
`1
`1996
`
`Fig. 1. Cycle time per layer.
`
`lowance for product mix in computing this metric. We
`also did not make any allowances for differences in
`average die sizes among the participants.
`5 ) Direct labor productivity expresses the total number of
`wafer layers completed per operator per working day. To
`compute this metric, we first estimate for each process
`flow the total number of wafer layers completed per
`working day using the formula
`WL = (WS/WD)(TL)(LY’)
`
`where WS is the average number of wafer starts per
`week, WD is the number of working days per week, TL.
`is the total number of wafer layers in the process flow,
`and LY’ is the inflated line yield defined as above. We
`then compute the metric by summing the WL figures for
`each process flow and dividing by the reported number
`of production operators.
`6) Total labor productivity expresses the total number of
`wafer layers completed per working day divided by the
`total head count. This metric is computed similarly,
`except the divisor is the reported total number of fab
`employees, including dedicated staff from equipment
`vendors.
`7 ) On-time delivery measures the ability of the participants
`to meet production schedules. It expresses the percentage
`of items scheduled for output in a week whose actual
`output quantity by the end of the week is greater than or
`equal to the scheduled quantity. Some participants report
`on-time delivery at the die level, some at the finished
`
`goods level, some at both levels, while others declined
`to state their performance or simply did not know.
`We encountered a wide range in scores for each metric, even
`though the basic process technology and the major manufactur-
`ing equipment in use at the participants were generally similar.
`Table I1 summarizes the best, average, and worst scores for
`each metric, considering the latest data points we received
`from each of the sixteen participants, and provides an estimate
`of the relative ranking of Japanese and US firms in each metric.
`These data points represent measurements of manufacturing
`performance in some quarter between the middle of 1992 and
`the end of 1993, depending upon the participant.
`Rates of improvement also are studied for each participant.
`Figs. 1-6 graph the first six metric scores over time for the
`participants. To protect confidentiality, a coding scheme is
`used whereby the participating fabs are labeled F1-F16. The
`scheme is uniform across the graphs, e.g., F1 refers to the
`same fab on all graphs. Scores for each technical metric are
`computed for each quarter over a period of three to four years.
`In graphs of defect densities, multiple curves are sometimes
`displayed for the same fab, indicating the fab operated more
`than one process flow in the category of flow that is graphed.
`For most metrics, the ranking of participants does not change
`quickly. We did not find many cases where a last-place
`participant overtook the leader for a particular metric, although
`a few participants improved their rankings considerably over
`the period.
`Perhaps the most striking phenomenon observed in our
`measurements concerns the initial defect densities for process
`
`Applied Materials, Inc. Ex. 1011
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 3 of 12
`
`

`

`LEACHMAN AND HODGES: BENCHMARKING SEMICONDUCTOR MANUFACTURING
`
`161
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`
`TABLE I1
`SUMMARY OF TECHNICAL METRIC SCORES, COMPETITIVE
`SURVEY (FIRST 18 MONTHS)
`SEMICONDUCTOR MANUFACTURING
`
`2.6
`92.8
`
`0.74
`0.79
`0.47
`0.61
`382
`29.6
`17.6
`89%
`
`3.3
`88.2
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`1.52
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`76%
`
`-
`*
`O d l :
`++
`
`+
`+
`*
`-
`
`Cycle time per layer (days)
`Line yield per ten layers (%)
`Murphy defect density.
`0.7 - 0.9 micron CMOS mmory
`(defecWc“)
`0.7 - 0.9 micron CMOS logic
`1.0 - 1.25 micron CMOS logic
`1.3 - 1 .5 micron CMOS logic
`5X stepper throughput (5X layers
`completed per machineda )
`Diwt labor productivity ( w d r
`layers completed/opemtorday)
`Total labor productivity (wafer
`layers completeahotal staff4ay)
`On-time Delivery (% of b e items
`with 95% of die output on time)
`Average and worst scores are calculated after discarding the worst data sample for each
`metric. Legend
`++ Japanese fabs are almost unifonnly superior
`+ Japanese fabs are genetally superior
`0 Superiorhferior fabs are not distinguished by region
`- US fabs are geuerally superior
`- US fabs are almost uniformly superior
`
`Fig. 2. Line yield.
`
`flows, that is, the defect densities realized in the first quarter
`after transfer of the process flow into manufacturing. We
`recorded a factor-of-ten range in initial defect densities. Those
`fabs with poor starting points tend to have faster rates of
`improvement, but not nearly fast enough to overtake those
`with good starting points, at least not for several years, as
`those with good starting points also make steady if somewhat
`slower progress reducing defect densities.
`
`v. ANALYSIS OF PRACTICES UNDERLYING
`MANUFACTURING PERFORMANCE
`Our main objective in the CSM survey is to identify those
`operational practices that underlie leading-edge manufacturing
`performance. Summarized below are the operational practices
`that distinguish those fabs achieving best or near-best scores
`in one or several of the metrics described above. (For the sake
`of brevity, we refer to such fabs as the “leading” fabs.) But
`before summarizing our findings in that regard, it is only fair
`to acknowledge that our analysis does not account for several
`strategic factors concerning product design and fab design that
`may strongly influence manufacturing performance.
`First, the restrictiveness of product design rules can have
`a strong influence on observed die yields and hence on
`our calculated defect densities. Issues of overall business
`strategy influence the choice of design rules and affect the
`priority attached to the different metrics of manufacturing
`performance. We made no attempt to normalize defect density
`scores for differences in design rules and/or overall business
`strategy among the participants.
`Second, the range of sizes of fabs in our survey, in terms of
`wafer starts, spans a factor of almost fifty. Small fabs generally
`have inferior labor and equipment productivity scores, because
`
`1.2
`98.9
`
`0.28
`0.28
`0.23
`0.21
`724
`63.0
`37.7
`100%
`
`of the indivisibility of machines and operators, and because of
`the tendency to install extra equipment to avoid situations in
`which a particular process step must be performed by a one-
`of-a-kind equipment type. We made no attempt to normalize
`productivity scores to account for fab size.
`Third, the assignment of older-generation of processing
`equipment to newer-generation process flows may result in
`lower values for several metrics than would be possible with
`newer equipment. While yields may be lower for the strategy
`to employ older processing equipment, capital costs are lower
`
`Applied Materials, Inc. Ex. 1011
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 4 of 12
`
`

`

`IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO. 2, MAY 1996
`
`162
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`(b)
`(a) Memory defect density 0.7-0.9~ CMOS process flows. (b) Memory defect density 0.7-0.9~ CMOS process flows. (c) Logic defect density
`Fig. 3.
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`
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`as well, and so the strategy might turn out to be economically
`competitive or even superior to the strategy that employs solely
`new processing equipment. We made no attempt to normalize
`metric scores for the generations of equipment applied.
`With these strategic factors aside, we now turn to the various
`operational practices we found to be correlated with good
`
`manufacturing performance (in terms of the manufacturing
`metrics we have defined). These practices may be categorized
`into four basic types of practices at which a fab must excel in
`order to realize excellent manufacturing performance.
`First, a fab must have computer systems providing strong
`process control, excellent data collection and excellent data
`
`Applied Materials, Inc. Ex. 1011
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 5 of 12
`
`

`

`LEACHMAN AND HODGES: BENCHMARKING SEMICONDUCTOR MANUFACTURING
`
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`Applied Materials, Inc. Ex. 1011
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 6 of 12
`
`

`

`164
`
`IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO. 2, MAY 1996
`
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`Fig. 4. 5X stepper productivity.
`
`analysis capabilities. The fab must be able to expeditiously
`pinpoint the causes of yield loss and the sources for losses of
`wafer throughput. The fab must be able to promptly recognize
`when processing is being done incorrectly, or better yet,
`prevent misprocessing entirely with equipment and system
`controls and procedural checks.
`Second, a fab must have an organization that not only exe-
`cutes the manufacturing processes well, but also is very good
`at problem recognition and at problem solving. Semiconductor
`manufacturing is characterized by immature processes and
`immature processing equipment with relatively short lives,
`and by continuing increases in complexity. Opportunities to
`improve yields and/or wafer throughput are always present.
`Thus manufacturing has a major engineering element as well
`as an operational character. This means a fab must continually
`improve the technical competence of its organization and
`continually foster a teamwork approach to recognize prob-
`lems, devise innovative solutions, and implement them quickly
`and successfully. Not only engineers but also operators and
`technicians must participate in problem recognition, process
`improvement and problem solving, and they therefore must
`possess basic engineering skills as well as technical knowledge
`of the manufacturing processes and equipment.
`Third, and closely related to the second area, the fab must
`have the internal technical talent as well as the requisite
`support from vendors to expeditiously make modifications
`to product, process, and equipment in order to implement
`changes that have been identified by problem-solving efforts as
`desirable or necessary to improve manufacturing performance.
`
`Fourth, and finally, a fab must have effective procedures
`for managing the introduction of new process flows. The
`economic life of many process flows is three to four years,
`with unit prices for products of the flow declining rapidly
`over this period. Thus it is economically important to realize
`high throughput of the process flow early in its life, and to
`fairly frequently introduce new process flows into the fab. This
`means the fab must become expert in each new process flow
`and its required equipment as soon as possible, ideally before
`it transfers to production, so as to realize good yields and good
`wafer throughput early in its life and to quickly ramp to better
`yields and higher wafer throughput thereafter. Even if a fab
`is proficient in the above three types of practices, a poor start
`with a new flow may leave the fab too far behind to catch up
`before the market value of the output has mostly drained away.
`Table III provides a tabulation of particular operational
`practices of these types, the impacted metrics, and comparisons
`of the overall rankings for Japanese vs. US. manufacturers.
`These rankings include some weight added in recognition of
`the intensity or effectiveness of practice. As can be seen,
`the practices are organized into categories titled CIM and
`Information Systems, Organizational Practices, Formal Proce-
`dures, Process and Technology Improvements, and Production
`Control.
`
`VI. CIM AND INFORMATION SYSTEMS
`In the area of CIM and Information Systems, the leading
`fabs collect and analyze large amounts of data, enabling them
`to trouble-shoot their manufacturing processes and equipment
`
`Applied Materials, Inc. Ex. 1011
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 7 of 12
`
`

`

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`165
`
`TABLE 111
`SUMMARY OF EFFECTIVE MANUFACTURING PRACTICES
`
`TABLE 111 (CONTINUED)
`
`Metrics Influenced
`
`Japan vs. US
`
`hactice
`Process and Technology
`Improvements:
`Line yield, cycle time, labor
`Machine modifications to
`productivity, equipment
`automate loadlunload or wafer
`throughput
`handling mechanisms
`Machine modificatons to d u c e Defect density, cycle time,
`particle counts
`labor productivity, equipment
`throughput
`Defect density, cycle time, line
`yield, equipment throughput
`Product re-design
`Defect density
`Machine lights and audio alarms Cycle time, equipment
`throughput, labor productivity
`Defect density, cycle time,
`equipment throughput
`Cycle time, labor productivity
`
`F%!xiGs
`CZM and
`information
`systems
`SPC
`Equipment efficiency
`measurement
`Visual displays of SPC charts,
`equipment tracking, etc.
`
`Automation of data logging
`
`Auto recipe download and/or
`display
`
`Automated feedback control
`at photolithography
`Yield correlation analysis
`In-line electrical measurements
`In-line particle measwments
`Automated trouble messaging
`and automated assistance for
`trouble-shooting
`
`Mevics
`
`Jauan vs. US
`
`Defect Density, Line Yield
`quipment throughput, cycle
`ume, labor productivity
`Line yield, defect density, labor
`productivity, equipment
`throughput
`Cycle time, defect density, labor
`productivity, equipment
`throughput
`Line yield, cycle time, defect
`density, labor productivity,
`equipment throughput
`Defect density
`
`Defect density
`Defect density
`Defect density
`Cycle time, line yield, equipment
`throughput, labor productivity
`
`++
`++
`
`+
`
`++
`
`0
`
`0
`
`+t
`+
`+
`-
`
`€Bak.G
`Formal Procedures
`Formal procedures for new
`process intrvductions
`
`TABLE 111 (CONTINUED)
`
`Metrics Influenced
`
`, & # n vs. us
`
`Defect density, line yield,
`equipment throughput
`Equipment throughpuf cycle
`time, line yield, defect density,
`labm productivity
`
`++
`
`++
`
`Organizational Practices
`Exchange. of engineers with
`Defect density, line yield,
`development fab
`equipment throughput
`Integration of engineering groups Defect density
`Quipment throughput,
`Integration of enginwring and
`line yield, defect density
`manufacturing staff
`Opaator and technician
`Equipment throughput, cycle
`improvement teams
`time, lime yield
`Mentoring by senior engineers
`Defect density, line yield, +i
`and supervisors
`equipment throughput
`Mentoring by senior operators
`Line yield, cycle time,
`equipment throughput
`Defect density, line yield,
`equipment throughput
`Defect density, line yield,
`equipment throughput, labor
`producuvity
`
`Extensive leadership training
`
`“Stretch” goals
`
`++
`
`++
`++
`
`++
`
`++
`
`++
`
`++
`
`quickly and comprehensively. All participants in our study
`have embraced statistical process control (SPC) as a means
`of detecting manufacturing problems and improving process
`performance. Almost all provide automated notification of out-
`of-control conditions. The leading fabs rigorously manage their
`SPC programs, retiring unneeded control charts and adding
`
`++
`
`++
`
`+
`++
`++
`
`0
`++
`
`--
`--
`--
`
`Process flow re-design
`
`Linked photolithography cells
`
`Automated interbay
`lot movement
`Production Control
`Kanban
`Computerized dispatching
`
`Cycle time, labor productivity
`Cycle time, labor productivity,
`on-time delivery
`On-time delivery
`
`Production planning based on
`measured equipment capacity
`Legend: ++ Japanese fabs are almost uniformly more effective
`+ Japanese fabs are generally more effective
`0 The most effective practitioners are not distinguished by region
`- United States fabs are almost uniformly more effective
`- United States fabs are generally more effective
`
`new ones recognized as desirable, adjusting control limits as
`appropriate, adjusting frequencies of measurements to focus
`efforts on the most critical areas, and maintaining an effective
`training program.
`SPC measurements are made both of product wafers and
`of machine conditions, such as particle counts of machine
`exhaust flows or of blank wafers passed through the machine.
`The leading fabs have information systems that automatically
`provide assistance for responding to out-of-control situations,
`such as auto-display of corrective action guidelines, automatic
`disabling of equipment or process, automatic notification of
`the responsible engineers, etc. SPC measurements also are
`used to trigger preventive maintenance and tool or material
`replacements.
`All of our participants have engineering databases to which
`they upload some amount of metrology data, SPC measure-
`ments, and production tracking data (such as which machine
`was used to process a lot, which operator attended to it, which
`batch of chemicals was used, etc.). The leading fabs upload
`more data, and they have automated the upload of much of
`these data using bar codes or magnetic cards and sensors.
`The top fabs efficiently perform end-of-line yield analyzes
`by integrating their engineering database with the database
`of die yields and parametric measurements taken at the end
`of the manufacturing line. Automated statistical correlations
`are made between die yield results and the data uploaded
`to the engineering database described above, in order to
`ascertain what characteristics are common to low-yielding
`
`Applied Materials, Inc. Ex. 1011
`Applied v. Ocean, IPR Patent No. 6,836,691
`Page 8 of 12
`
`

`

`EEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO. 2, MAY 1996
`
`I
`1988
`
`I
`1989
`
`I
`1990
`
`I
`1991
`
`I
`1992
`
`Time
`
`I
`1993
`
`I
`1994
`
`I
`1995
`
`1
`1996
`
`Fig. 5. Direct labor productivity
`
`wafers. Leading fabs feature yield improvement groups that
`build yield models specifically for their fab, perform extensive
`wafer map analysis of yield patterns to find clues to the types
`of processing equipment where losses were incurred, as well
`as carry out statistical correlation analyzes as described above.
`The leading fabs document their findings for each major event
`of yield loss, and save these findings in a database for future
`reference.
`Leading fabs also are increasing their efforts for in-line yield
`analysis using digital image processing and laser scanning
`machines to conduct particle inspections of partially-processed
`wafers. Wafer maps showing the distribution of particles are
`classified so as to obtain clues concerning the equipment
`source of the particles; SPC procedures are instituted for
`particle inspections, for which out-of-control incidents trigger
`partitioning analyzes to pinpoint the source of particles; and
`end-of-line die yields are statistically correlated with in-line
`particle measurements of the product wafers.
`The leading fabs make effective use of computers to prevent
`processing errors. Automated recipe download is installed
`at most or even all processing equipment in leading fabs.
`“Smart” lot-machine interfaces have been installed by some
`leading fabs, whereby the computer system prevents one
`from tendering the wrong lot or the wrong recipe to the
`machine. In addition, “smart” lot and reticle racks also are
`used at one participant to highlight the correct lot and reticle
`to be used. A couple of leading fabs also have automated
`the feedback control of photolithography exposures based on
`critical dimension measurements.
`
`VII. ORGANIZATIONAL PRACTICES
`In the area of organizational practices, the leading fabs
`practice considerable integration of sustaining engineering
`staff with development engineering staff in order to make
`the introduction of new process flows more successful. The
`top fabs exchange engineers with the development fab that
`is the source for their new process flows, sendi