IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________
`
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`APPLIED MATERIALS, INC.
`
`Petitioner
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`v.
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`OCEAN SEMICONDUCTOR LLC,
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`Patent Owner.
`
`_____________________
`
`Case IPR: Unassigned
`U.S. Patent No. 6,836,691
`_____________________
`
`DECLARATION OF MILTIADIS HATALIS, Ph.D., IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,836,691
`
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`
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`Applied Materials, Inc. Ex. 1002
`Applied v. Ocean, IPR Patent No. 6,836,691
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`Inter Partes Review of U.S. Patent No. 6,836,691
`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`Table of Contents
`Overview .......................................................................................................... 1
`Experience and Qualifications ......................................................................... 3
` List of Documents Considered in Formulating My Opinion ........................ 10
` Person of Ordinary Skill in the Art (“POSA”) .............................................. 13
`State of the Art Before the May 31, 2003 Filing Date .................................. 14
`Background on the Field of Semiconductor Manufacturing Before
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`May 31, 2003 ....................................................................................... 14
`Semiconductor Processing is Complex and Costly, and There is
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`a Constant Need to Maximize Yield ......................................... 14
`Advanced Process Control and In Situ Data Maximize Chip
`Yield .......................................................................................... 16
`Adjusting Process Recipes Using Metrology Data ................... 17
`Analyzing Faults Using Metrology Data .................................. 18
`
` Summary of the ’691 Patent .......................................................................... 18
`Brief Description of Subject Matter .................................................... 18
`
`Independent Claim 1 ................................................................. 21
`
`Independent Claim 10 ............................................................... 21
`Dependent Claims 2-9, 11-19 ................................................... 22
`
` The Basis of My Analysis with Respect to Obviousness .............................. 22
`Summary of U.S. Patent No. 7,123,980 (“Funk”) .............................. 24
`
`A Claim of Funk is Supported by its Provisional and PCT
`
`Publication ................................................................................ 29
`Funk’s Provisional Application Contains Sufficient Written
`Description to Enable a POSA to Practice the Invention
`Disclosed in Funk ..................................................................... 31
`Summary of U.S. Patent No. 6,587,744 (“Stoddard”) ........................ 36
`Analysis of Claims 1-19 of the ’691 Patent ........................................ 39
`A POSA Would Have Been Motivated To Combine the APC
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`System of Funk With the Metrology Teachings of Stoddard ... 39
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`Inter Partes Review of U.S. Patent No. 6,836,691
`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`A POSA Would Have Had a Reasonable Expectation of
`Success in Combining the Teachings of Stoddard with Funk .. 48
`Claims 1 and 10 ......................................................................... 49
`Claims 2 and 11 ......................................................................... 60
`Claims 3 and 12 ......................................................................... 62
`Claims 4 and 13 ......................................................................... 64
`Claims 5 and 14 ......................................................................... 67
`Claims 6 and 15 ......................................................................... 69
`Claims 7 and 16 ......................................................................... 70
` Claims 8 and 17 ......................................................................... 71
` Claims 9 and 18 ......................................................................... 72
` Claim 19 .................................................................................... 73
` Objective Indicia of Nonobviousness ....................................... 75
` Conclusion ..................................................................................................... 76
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`Inter Partes Review of U.S. Patent No. 6,836,691
`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`I, Miltiadis Hatalis, Ph.D., hereby declare as follows:
`OVERVIEW
`I make this declaration in support of Petitioner Applied Materials,
`
`
`Inc.’s petition for inter partes review of U.S. Patent No. 6,836,691 (Ex. 1001),
`
`which I refer to in my declaration as “the ’691 patent.” I have been asked to
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`address claims 1-19 of the ’691 patent.
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`
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`I am over 18 years of age and otherwise competent to make this
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`declaration.
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`
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`I am being compensated for my time spent on this matter at my
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`standard consulting rate of $450 per hour. My compensation is not dependent on
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`the substance of my opinions, my testimony, or the outcome of the inter partes
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`review proceeding.
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`
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`I am not an employee of Petitioner or any affiliate or subsidiary
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`thereof.
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`
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`This declaration summarizes the opinions I have formed to date. I
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`reserve the right to modify my opinions, if necessary, based on further review and
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`analysis of information that I receive subsequent to the filings of this report,
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`including in response to positions that parties to the inter parties review
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`proceeding, or their experts, may take that I have not yet seen.
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`1
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`Inter Partes Review of U.S. Patent No. 6,836,691
`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`
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`I understand that the ’691 patent issued on December 28, 2004, and
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`
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`resulted from U.S. Application No. 10/427,620, filed on May 1, 2003.
`
`I understand that, based on that date, the earliest possible date to which the ’691
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`patent may claim priority is May 1, 2003. I have been asked to provide my
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`analysis of the ’691 patent based on prior art and the knowledge in the art before
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`May 1, 2003. I also understand that the ’691 patent is currently assigned to Ocean
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`Semiconductor LLC (“Ocean”).
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`
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`In preparing this declaration, I have reviewed the ’691 patent
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`(Ex. 1001) and considered each of the documents cited in this petition, in light of
`
`the general knowledge in the art before May 1, 2003. I have also relied upon my
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`experience in the relevant art and considered the viewpoint of a person of ordinary
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`skill in the art (“POSA”; defined in Section IV) before May 1, 2003.
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`
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`The claims of the ’691 patent are generally directed to methods and
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`systems for collecting metrology data relating to processing workpieces,
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`generating context data (including collection purpose data) for that metrology data,
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`filtering the metrology data based on the collection purpose data, and conducting a
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`process control activity based on the filtered metrology data.
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`
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`Broadly, this declaration sets forth my opinion that claims 1-19 of the
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`’691 patent would have been obvious over the prior art.
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`Inter Partes Review of U.S. Patent No. 6,836,691
`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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` First, this declaration sets forth my opinion that a POSA would have
`
`had a reason to arrive at the subject matter recited in claims 1-19 of the
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`’691 patent, with a reasonable expectation of success, by combining Funk
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`(Ex. 1005) with the teachings of Stoddard (Ex. 1008), and a POSA’s knowledge of
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`the prior state of the art, as discussed in this declaration below.
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` Second, this declaration describes how, in reaching my conclusions
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`regarding obviousness, I have considered potential objective indicia of
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`nonobviousness and concluded that there are none that I am aware of that would
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`support a claim of nonobviousness.
`
` EXPERIENCE AND QUALIFICATIONS
`I have been a Professor in the Department of Electrical and Computer
`
`
`Engineering at Lehigh University since 1987. My professional qualifications,
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`experience, publications and presentations, and a listing of previous cases in which
`
`I have provided expert testimony are set forth in my curriculum vitae, attached as
`
`Ex. 1003.
`
` As set forth in my curriculum vitae, I received a Doctor of Philosophy
`
`degree in Electrical and Computer Engineering from Carnegie Mellon University
`
`in 1987. The topic of my Ph.D. dissertation research was “Crystallization of
`
`Amorphous Silicon Films and its Application in Bipolar and Thin Film
`
`Transistors.” I received a Master of Science degree in Electrical and Computer
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`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`
`Engineering from State University of New York at Buffalo in 1984 and I received
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`a Bachelor of Science degree in Physics from Aristotle University of Thessaloniki
`
`in Greece in 1982.
`
` Upon receiving my Ph.D., I joined the faculty of Lehigh University in
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`the Department of Electrical and Computer Engineering as an Assistant Professor.
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`I was promoted to Associate Professor with tenure in 1991 and to Professor in
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`1995. From 2003 to 2008, I concurrently served as professor in the Department of
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`Computer Science at Aristotle University, Greece. From 2010 to 2013, I served as
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`interim director of the Sherman Fairchild Center for Solid State Studies at Lehigh
`
`University. From 1987-1992, I served as Associate Director of Lehigh’s
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`Microelectronics Research Laboratory.
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`
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`In 1992, I founded, and became Director of Lehigh’s “Display
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`Research Laboratory,” which was the first academic clean room microfabrication
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`facility in the United States dedicated to research and development of electronic
`
`thin film materials and devices, for novel large area microelectronic system
`
`applications including flexible electronics, flat panel displays, and large area
`
`sensor arrays. As Director of Lehigh’s Display Research Laboratory, I have raised
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`over $13 million through research contracts and grants to support the laboratory’s
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`research activities. These contracts and grants were funded by the Defense
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`Advanced Research Program Agency (“DARPA”), the Army Research Laboratory
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`(“ARL”), the National Science Foundation (“NSF”), the National Aeronautics and
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`Space Administration (“NASA”), the State of Pennsylvania, and a variety of
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`industrial companies including IBM, Kodak, Sharp, Northrop Grumman, and
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`others.
`
` From 1987 to present I have conducted research in microelectronics,
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`including semiconductors, electronic materials, devices and circuits for integrated
`
`circuits and integrated microsystems. My research mainly focuses on electronic
`
`thin film materials and devices, microelectronic fabrication processes, novel
`
`electronic circuits and integrated microsystems. My research group pioneered the
`
`development of electronic thin film materials, devices and circuits on flexible
`
`substrates, active matrix organic light emitting diode displays, and addressable
`
`arrays for integrated sensor applications such as fingerprint sensors for biometrics
`
`and multichannel gas sensors.
`
` As a faculty member, I supervised the research of twenty Ph.D.
`
`dissertations in the technical field of semiconductors/microelectronics. Upon
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`graduating, all twenty of my Ph.D. graduate students moved either to industrial
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`positions in the electronic industry including Apple, IBM, Intel, TSMC, and
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`Motorola or into academic positions in the U.S. or abroad. I have also supervised
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`the research of several post-doctoral researchers and research associates at Lehigh.
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`Moreover, I have supervised a large number of graduate student Master’s theses
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`and numerous undergraduate research projects. I have been an invited lecturer at
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`numerous universities, industrial laboratories and conferences in the United States
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`and overseas.
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`
`
`I have been an author or co-author of 180 technical publications
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`which include two book chapters, 78 peer-reviewed publications in peer-reviewed
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`journals, and 97 papers published in conference proceedings. My publications
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`received over 4358 citations and I have an H-index of 29. The list of peer-
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`reviewed journals in which my papers were published include: Solid State
`
`Electronics, Journal of Applied Physics, Journal of the Society for Information
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`Display, Journal of Materials Science, and multiple Institute of Electrical and
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`Electronics Engineers (“IEEE”) journals including the IEEE Transactions on
`
`Electronic Devices, IEEE Solid State Circuits, IEEE Journal of Display
`
`Technology and IEEE Electron Device Letters. The technical conference where
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`my papers were presented have been organized by scientific societies including:
`
`the IEEE, Society of Information Display (“SID”), Materials Research Society
`
`(“MRS”), and Electrochemical Society (“ECS”).
`
`
`
`I am also a named inventor on U.S. Patent No. 8,390,536, directed at
`
`controlling current to pixels in an active matrix display by adjusting voltage on the
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`data lines, and two international patents associated with the above invention, one
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`issued in Korea and one in Japan.
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`Inter Partes Review of U.S. Patent No. 6,836,691
`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`I have taught a number of different undergraduate and graduate level
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`courses in the Electrical and Computer Engineering department at Lehigh
`
`University. These courses have generally centered on physics, technology, and the
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`design and fabrication of solid-state devices and integrated circuits. I have also
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`introduced several new courses relating to semiconductor fabrication and Very
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`Large Scale Integration (“VLSI”) design, including “Introduction to VLSI
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`Design,” “Semiconductor Material and Device Characterization,” and
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`“Introduction to Photovoltaic Energy Systems.” I also regularly teach the
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`introductory course in Electrical Engineering “Principles of Electrical
`
`Engineering” and the courses “Electronic Circuits” and “Introduction to VLSI
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`Circuits;” I have also taught the introductory course in Computer Engineering
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`“Introduction to Computer Engineering”.
`
` As part of my research, I utilize much of the same equipment and
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`many of the same microfabrication processes that are in used by the semiconductor
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`industry including: Plasma-Enhanced Chemical Vapor Deposition (“PECVD”) for
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`the deposition of silicon nitride and silicon dioxide films; Physical Vapor
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`Deposition (PVD) including both DC and RF sputtering, as well as and e-beam
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`evaporation tools for aluminum, tungsten, titanium, gold, tantalum, and other
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`metallic thin films; photolithographic tools for defining photoresist patterns on the
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`substrates; as well as reactive ion etching or wet etching tools for removing various
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`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`thin film materials from the substrates. I have also designed and constructed
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`advanced semiconductor processing tools including an Ultra-High-Vacuum
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`Chemical Vapor Deposition (UHV-CVD) reactor for depositing thin silicon films.
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`I also utilize several tools, including metrology tools, for the characterization of the
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`materials and structures used in microelectronic devices including: optical
`
`microscopes, surface profilometers, ellipsometry, Scanning Electron Microscopy
`
`(“SEM”), Transmission Electron Microscopy (“TEM”), and Atomic Force
`
`Microscopy (“AFM”). I further utilize a variety of electrical characterization
`
`techniques and instruments for testing the electrical performance of completed
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`electronic devices, circuits and systems.
`
` As part of my research, I pioneered a technique for crystallizing
`
`amorphous silicon. Similar techniques have been used in the manufacture of
`
`integrated circuits and flat panel displays. In addition, my research group at
`
`Lehigh pioneered the fabrication of electronic devices and circuits on novel
`
`flexible substrates and the development of integrated microsystems on flexible
`
`substrates, including active matrix organic light emitting diode displays, and
`
`addressable arrays for integrated sensor applications such as fingerprint sensors for
`
`biometrics and multichannel gas sensors. Many industrial and academic
`
`laboratories currently pursue similar research activities while certain aspects of my
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`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`prior research have transitioned to manufacturing. Such activities are the result
`
`from the accomplishments of my research group in this technical field.
`
` My industrial experience includes work at the XEROX Palo Alto
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`Research Laboratory and various consulting projects with semiconductor
`
`companies including Intevac Corporation, a semiconductor equipment maker. All
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`of these projects were related to electronic materials, semiconductor devices, and
`
`their application to the manufacturing of microelectronic systems. The project
`
`with Intevac Corp. utilized designed of experiment (DOE) approaches for
`
`optimizing the process conditions of a novel large area rapid thermal processing
`
`(RTP) tool.
`
`
`
`I am a member of several professional organizations including the
`
`Electron Device Society of the IEEE and the Society for Information Display
`
`(“SID”). I have also been the chaired or co-chaired numerous national and
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`international conferences and symposiums, including several SID-sponsored
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`Workshops on Active Matrix Liquid Crystal Displays and a Materials Research
`
`Society Symposium on Flat Panel Displays. I have co-authored two book chapters,
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`one dealing with the “Polysilicon TFT Technology” and another on the application
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`of “Polysilicon TFTs in AMOLED Displays.” I have served as a reviewer for
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`technical papers submitted to several scientific journals and have also served as a
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`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`reviewer for several years for the National Science Foundation Small Business
`
`Innovative Research (“SBIR”) program.
`
` Accordingly, I am an expert in semiconductor fabrication
`
`processes, including the fabrication of integrated circuits (ICs), and have been
`
`since 1987. For that reason, I am qualified to provide an opinion as to what a
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`POSA would have understood, known, or concluded as of May 1, 2003.
`
` A detailed list of my publications, education and professional
`
`experience, research grants, Ph.D. dissertations for which I served as advisor,
`
`publications and litigation cases in which I served as a technical expert, can be
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`found in my curriculum vitae attached and submitted as Ex. 1003.
`
`LIST OF DOCUMENTS CONSIDERED IN FORMULATING MY
`OPINION
`In forming my opinions, I read and considered the ’691 patent and its
`
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`prosecution history, the exhibits listed below, as well as any other material
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`referenced herein. The exhibits I have analyzed include:
`
`Exhibit
`No.
`1001
`
`1004
`
`1005
`
`1006
`
`Description
`Stirton, U.S. Patent No. 6,836,691 (filed May 1, 2003; issued Dec. 28,
`2004) (“the ’691 patent”)
`File Wrapper for the ’691 patent
`
`Funk et al., U.S. Patent No. 7,123,980 (filed Mar. 23, 2005; issued Oct.
`17, 2006) (“Funk”)
`Funk et al., U.S. Provisional Application No. 60/414,425 (filed Sept.
`30, 2002; expired July 19, 2004)
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`
`
`Exhibit
`No.
`1007
`
`1008
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1009
`1010
`
`Description
`Funk et al., International Publication No. WO 2004/031875 (filed Sept.
`25, 2003; published Apr. 15, 2004)
`Stoddard et al., U.S. Patent No. 6,587,744 (filed June 20, 2000; issued
`July 1, 2003)
`File Wrapper for Funk
`Roger E. Bohn and Christian Terwiesch, The Economics of Yield-
`Driven Processes, J. Operations Management, 18: 41-59 (1999)
`Robert C. Leachman and David A. Hodges, Benchmarking
`Semiconductor Manufacturing, IEEE Transactions on Semiconductor
`Manufacturing, 9: 158-69 (1996)
`Gardner, et al., Equipment Fault Detection Using Spatial Signatures,
`IEEE Transactions on Components, Packaging, and Manufacturing
`Technology—Part C, 20: 295-304 (1997)
`John McGehee, The MMST Computer-Integrated Manufacturing
`System Framework, IEEE Transactions on Semiconductor
`Manufacturing, 7: 107-16 (1994)
`Jula, P. et al., Comparing the Economic Impact of Alternative
`Metrology Methods in Semiconductor Manufacturing, IEEE
`Transactions on Semiconductor Manufacturing, Vol. 15, No. 4
`(November 2002)
`Richard J. Markle, and Elfido Coss, Jr., Data requirements and
`communication issues for advanced process control, J. of Vacuum Sci.
`& Tech. A 19, 1241 (2001).
`1016 Musacchio, J., et al., On the Utility of Run to Run Control in
`Semiconductor Manufacturing, IEEE International Symposium on
`Semiconductor Manufacturing Conference Proceedings, D-9–D-12
`(1997)
`Jerry A. Stefani and Mike Anderson, Practical Issues in the
`Deployment of a Run-to-Run Control System in a Semiconductor
`Manufacturing Facility, Proc. SPIE 3742, Process and Equipment
`Control in Microelectronic Manufacturing, 52-64 (April 23, 1999)
`Gabriel G. Barna, APC in the Semiconductor Industry, History and
`Near Term Prognosis, IEEE/SEMI 1996 Advanced Semiconductor
`
`1017
`
`1018
`
`11
`
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`
`
`Exhibit
`No.
`
`1019
`
`1020
`
`Description
`Manufacturing Conference and Workshop. Theme-Innovative
`Approaches to Growth in the Semiconductor Industry. ASMC 96
`Proceedings, 364-69 (1996)
`Limanond, S., et al., Monitoring and Control of Semiconductor
`Manufacturing Processes, IEEE Control Systems Magazine, 18:46-58
`(1998)
`Ison, A.M., et al., Fault Diagnosis of Plasma Etch Equipment, IEEE
`International Symposium on Semiconductor Manufacturing
`Conference Proceedings (1997)
`1021 Mark Melliar-Smith and Alain Diebold, Metrology Needs for the
`Semiconductor Industry Over the Next Decade, AIP Conference
`Proceedings 449, 3 (1998).
`Chris J. McDonald., New tools for yield improvement in integrated
`circuit manufacturing: can they be applied to reliability?,
`Microelectronics Reliability 39 (June 1999)
`Handbook of Thin Film Deposition Process and Technologies (2nd Ed.
`2002); Chapter 6 Keefer, M. et al., “The Role of Metrology and
`Inspection in Semiconductor Processing”
`Tobin, K. et al, Integrated applications of inspection data in the
`semiconductor manufacturing environment, Proc. SPIE 4275,
`Metrology-based Control for Micro-Manufacturing, (5 June 2001)
`Spanos, C., et al., Real-Time Statistical Process Control Using Tool
`Data, IEEE Transactions on Semiconductor Manufacturing, Vol. 5,
`No. 4 (Nov. 1992).
`Sherry F. Lee and Costas J. Spanos, Equipment Analysis and Wafer
`Parameter Prediction Using Real-Time Tool Data, 1994 International
`Symposium on Semiconductor Manufacturing VI-5.
`Lee, S., et al., RTSPC: A Software Utility for Real-Time SPC and Tool
`Data Analysis, IEEE Transactions on Semiconductor Manufacturing,
`Vol. 8, No. 1 (Feb. 1995).
`Sherry F. Lee and Costas J. Spanos,, Prediction of Wafer State After
`Plasma Processing Using Real-Time Tool Data, IEEE Transactions on
`Semiconductor Manufacturing, Vol. 8, No. 3 (Aug. 1995).
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`12
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`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
`
`Exhibit
`No.
`1029
`
`Description
`Byungwhan Kim and Gary S. May, Real-Time Diagnosis of
`Semiconductor Manufacturing Equipment Using a Hybrid Neural
`Network Expert System, IEEE Transactions on Components,
`Packaging, and Manufacturing Technology–Part C, Vol. 20, No. 1
`(Jan. 1997).
`
` For any future testimony I may give in this matter, I may use some or
`
`
`
`
`
`all of the documents and information cited to, referred to, and identified in this
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`declaration, as well as any additional materials that are entered into evidence in
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`this matter.
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` PERSON OF ORDINARY SKILL IN THE ART (“POSA”)
`I understand that a POSA is a hypothetical person who is presumed to
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`be aware of all the pertinent art, thinks along conventional wisdom in the art, and is
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`a person of ordinary creativity. A POSA may work as a part of a multi-
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`disciplinary team and draw upon not only his or her own skill, but also take
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`advantage of certain specialized skills of others in the team, to solve a given
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`problem. In regard to the ’691 patent, a POSA would have had at least a B.S. in
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`mechanical engineering, electrical engineering, materials science engineering, or a
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`related field, and four years of experience working with semiconductor
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`manufacturing processes and measurement techniques.
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`Inter Partes Review of U.S. Patent No. 6,836,691
`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`STATE OF THE ART BEFORE THE MAY 31, 2003 FILING DATE
` Background on the Field of Semiconductor Manufacturing Before
`May 31, 2003
`Semiconductor Processing is Complex and Costly, and
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`There is a Constant Need to Maximize Yield
` Wafer processing takes place in manufacturing plants known as
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`“fabs.” (Ex. 1011, 158.) Prior to 2003, fabs required large capital investments in
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`plant and equipment ranging from several hundred million dollars to $1 billion
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`each. (Ex. 1011, 158; Ex. 1013, 107; Ex. 1024, 31.)
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` Further, wafer processing is “exceeding complex” often requiring 400
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`or more sequential operations on a wafer over a span of 20 to 60 24-hour days,
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`requiring several hundred machines and personnel working around the clock. (Ex.
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`1011, 158; Ex. 1013, 107.) Each of these process steps “must be carried out in a
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`hostile, near particle free environment to exacting tolerances.” (Ex. 1013, 107.) A
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`gross failure at any step can render a wafer worthless. (Ex. 1011, 158.)
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` While the specific sequential operations/processing steps are tailored
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`to the wafers being manufactured, the general types of processes performed during
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`semiconductor processing include: metal preparation, oxidation, coating, baking,
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`lithography, etching, diffusion, deposition, post-exposure bake, development, and
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`polishing. (Ex. 1013, 107; Ex. 1012, 295; Ex. 1014, 454; Ex. 1019, 46-47.) Most
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`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`semiconductors processed will require “multiple steps through the same process at
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`different stages.” (Ex. 1019, 46.)
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` Metrology allows for maximizing yield by reducing defects that affect
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`production yield, which is a key area for process control and indeed “integral” to
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`ensure a high yield and good quality products. (Ex. 1023, 241, 244; Ex. 1021, 4.)
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`This is typically achieved through an iterative process of: detecting faults,
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`classifying faults, identifying the source of the faults, correcting the fault, and the
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`monitoring for yield excursions. (Ex. 1023, 244.)
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` For instance if the metrology data shows that the wafer is “good,”
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`then it can continue being processed at the next operation, but if the data shows a
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`defect, a fab can attempt to rework the wafer, though some wafers must ultimately
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`be scrapped. (Ex. 1010, 41, 43-44; Ex. 1028, 252; Ex. 1027, 17-18; Ex. 1026, 134-
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`35; Ex. 1024, 32-34, 36; Ex. 1015, 1241, 1244-46.)
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`
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`In the 1990s, the Semiconductor Industry Association created a series
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`of “National Technology Roadmap[s] for Semiconductors,” which were designed
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`to “provide a consensus view of the most critical technology requirements for
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`[integrated circuit] manufacture with a 15 year horizon.” (Ex. 1021, 3-4; Ex. 1023,
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`247.) The Semiconductor Industry Association released a 1992, 1994, and 1997
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`Roadmap, and the 1997 Roadmap included a “Metrology Roadmap,” thereby
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`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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`indicating that metrology was “critical” to integrated circuit manufacture for the
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`subsequent 15 years. (Ex. 1021, 3-4; Ex. 1023, 247.)
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`
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`Advanced Process Control and In Situ Data Maximize Chip
`Yield
`In the mid-1980s, Advanced Process Control (APC) began to be used,
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`
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`along with Fault Detection and Classification (FDC). (Ex. 1018, 364-66.) FDC
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`systems cover two tasks: (1) fault detection, i.e., the determination that during the
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`processing of a particular wafer, the sensor signatures indicate a “non-normal”
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`state, and (2) fault classification, i.e., determining the possible causes of a fault and
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`determining the effect of the fault on the wafer state. (Ex. 1018, 366-67.)
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` Beginning in the 1990s, all major semiconductor manufacturers
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`accepted and pursued APC. (Ex. 1018, 365.) APCs were deemed the best way to
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`handle the daunting challenges of maintaining ever more stringent controls for
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`hundreds of manufacturing operations. (Ex. 1015, 1241.)
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` As part of these APCs, fabs collected and analyzed large amounts of
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`data in their engineering databases to pinpoint the causes of yield loss and trouble-
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`shoot their manufacturing processes and equipment quickly and comprehensively,
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`including identifying patterns in wafer defect, parametric, and electrical
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`measurement data. (Ex. 1024, 32-34, 36; Ex. 1022, 735-36; Ex. 1015, 1241-42,
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`1245; Ex. 1016, D-9; Ex. 1017, 52-53, 56-57, 62)
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`Inter Partes Review of U.S. Patent No. 6,836,691
`Declaration of Miltiadis Hatalis, Ph.D. (Ex. 1002)
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` As APCs became popular, fabs switched to using product wafers and
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`using in situ inspection, which is now the norm. (Ex. 1023, 247.) In situ
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`metrology systems use highly-proficient sensors to perform diagnosis on a real-
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`time basis and without bothering the process. (Ex. 1018, 364-65; Ex. 1015, 1241-
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`42; Ex. 1017, 56; Ex. 1020, B-49; Ex. 1029, 39; Ex. 1025, 308;) For instance,
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`these real-time sensors could generate real-time alarms in the case of misprocessed
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`wafers while the wafer is still in the processing chamber and before it impacts the
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`product. (Ex. 1027, 17, 23; Ex. 1025, 308-09.)
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`
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` Moreover, related context data was collected by fabs to allow for
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`querying the fabrication process. (Ex. 1024, 36.) For instance, querying based on
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`“product ID, lot number, wafer ID, time/date, process layer, engineer
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`classification, or ADC class,