`
`a Binary Compatible with Large
`Software Base
`— MS-DOS*, OS/2**, Windows
`— UNIX*** System V/386
`— iRMX®@, iRMK™ Kernels
`g High Integration Enables On-Chip
`—8 Kbyte Code and Data Cache
`— Floating Point Unit
`— Paged, Virtual Memory Management
`m Easy To Use
`— Built-In Self Test
`— Hardware Debugging Support
`—- Intel Software Support
`— Extensive Third Party Software
`Support
`
`m High Performance Design
`— FrequentInstructions Execute in One
`Clock
`— 25 MHz and 33 MHz Clock
`Frequencies
`— 106 Mbyte/Sec Burst Bus
`— CHMOSIV Process Technology
`m Complete 32-Bit Architecture
`. — Address and Data Busses
`— Registers
`@ Multiprocessor Support
`— MultiprocessorInstructions
`— Cache Consistency Protocols
`— Support for Second Level Cache
`
`The i486™ CPU offers the highest performance for DOS, OS/2, Windows and UNIX System V/386 applica-
`tions.
`It is 100% binary compatible with the 386™ CPU. One million transistors integrate cache memory,
`floating point hardware and memory management on-chip while retaining binary compatibility with previous
`membersof the 86 architectural family. Frequently used instructions execute in one cycle resulting in RISC
`performancelevels. An 8 Kbyte unified code and data cache combined with a 106 Mbyte/Sec burst bus at
`33.3 MHz ensure high system throughput even with inexpensive DRAMs.
`
`New features enhance multiprocessing systems. Newinstructions speed manipulation of memory based sem-
`aphores. On-chip hardware ensures cache consistency and provides hooksfor multilevel caches.
`
`The built in self test extensively tests on-chip logic, cache memory and the on-chip paging translation cache.
`Debug features include breakpoint traps on code execution and data accesses.
`
`
`
`i486T MicroprocessorPipelined 32-Bit Microarchitecture
`64 Bit Interunit Transfer Bus
`
`
`
`32-bit Dote Bus
`
`
`32-bit Data Bus
`
`BuaInterface
`A2-A31,
`
`BEO#-BES¥
`Se
`tat
` Paging
`
`
`Descriptor
`i _sRegisters
`Physical
`Address
` Lookaside
`Limit and
`Transtation
`
`
`Dota Bus
`
`
`
`ALU
`Attribute
`
`Tronsceivers
`
`D,
` 5;
`Buffer
`PLA
`
`
`
`PLOCK#
`RDY#
`LOCK#
`Widyoes?
` Bus Control
`HOLD HLDA RESET
` Request Sequencer
`INTR NMI
`BOFF# A201 ‘f BREQ
`FERR# IGNNE#
`
`BRDY# BLAST#
`32 Byte Code
`jueue
`
`
`
`Floating Control ond Mooeei—ittitsCd; ee eee ee
`
`
`
`
`Unit
`Decode
`BS164 BSF
`2 x 16 Bytes
`Point
`Protection Test P__—____|_
`"struction
`Mnit
`
`
`
`
`
`
`
`
`fof ENE FLUSH
`Decoded
`F.P. Register
`
`AHOLD, EADSS
`Instruction
`File
`Path
`
`Parity Generation
`oPO-bp3
`and Control
`
`
`
`240440-1
`
`ae
`ontrs
`
`
`
`iIRMX, iRMK, 386, 387, 486, i486 are trademarksof Intel Corporation.
`*MS-DOS®is a registered trademark of Microsoft Corporation.
`**QS/2Tis a trademark of Microsoft Corporation.
`***UNIXTis a trademark of AT&T.
`
`tnte! Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
`licenses are implied. Information contained herein supersedes previously published specifications on these devicesfrom Intel.
`April 1989
`© Intel Corporation, 1989
`Order Number: 240440-001
`
`Petitioner Samsung Ex-1009, 0001
`
`Petitioner Samsung Ex-1009, 0001
`
`