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`Tianma Exhibit 1013
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`Page 1 of 5
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`Tianma Exhibit 1013
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`21.3: Fault Identification on TFT-LCD Substrates Using Transfer Admittance
`Measurement
`
`H. Hall
`
`GenRad, Inc., Concord, MA
`
`Abstract
`Identifying faults as to type on TFT-LCD
`substrates is necessary to determine if they can
`be repaired and to provide information to
`improve product quality. Fast fault detection and
`determining fault type require different test
`strategies. Transfer admittance measuring
`techniques can be used effectively for both
`purposes.
`
`The primary reason manufacturers needto test
`TFI-LCD panels at the substrate level is to
`avoid putting more value into bad substrates
`which eventually will have to be scrapped after
`final visual tests. A second reason is to find
`faults so that bad panels can be repaired, thus
`saving the value already put into them. Many
`types of faults can be repaired, but notall.
`Moreover, of those that can be repaired,
`different types of faults are repaired by different
`processes. Thus identification of faults is
`necessary for repair and for the savingsthatit
`can provide. Still another importantreason for
`testing is
`to improve the manufacturing
`processes. This also requires fault identification
`in order to determine whatthe problem is. This
`could give the biggest savingsofall.
`
`This paper examines the capability of an
`electrical test procedure for identifying faults as
`well as detecting and locating them.
`
`Vi
`The method discussed is the so-called
`"Transfer Admittance Method"[1] that applies
`voltages to the gate (or control) lines, and to the
`storage capacitor network, "Cs Bus", (if there is
`one), and detects currents on drain (data) lines
`(see figure 1).
`
`In the preferred configuration, all gate
`and drain lines are probed to allow good
`guarding and many detectors are used
`simultaneously to get good test throughput.
`The system measures the complex admittance,
`output current divided by input voltage, and
`separates this into conductance and capacitance.
`A dc voltage is also applied to the active gate
`line to turn the TFTsin that row both on andoff
`and measurements are made under both
`conditions. The differences between these two
`capacitance and two conductance
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`Page 2 of 5
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` Detectors
`
`n
`
`jout/Ein= ¥ = G +[wo
`
`m+
`
`I
`
`M Gate Lines
`N Drain Lines
`
` Coff = Cgd +MCedi
`itEgi=Ecs:
`£sC=Cgs+Cs
`and
`G=Gate, O=Drain, S=Source
`
`Figure 1
`
`Test Method
`
`measurements, A C and A G,are calculated
`because they provide the most sensitive means
`of detection and identification of most fault
`types.
`
`If a protective guard ring is present, this
`method requiresthatthe resistances between the
`line test pads and the guard ring be high enough
`to allow the application of the dc voltage
`necessary to turn the TFTs on andto allow the
`detection of the output currents without
`excessive attenuation and noise.
`If this
`requirementis considered at the designstage,
`these resistances can be made high enoughfor
`good "testability" without impairing the ability
`of the guardring to protect the substrate from
`damage from electrostatic voltages. The method
`puts norestrictions on the active area ofthe
`substrate and makes no contactto this area.
`
`There are a wide variety of possible faults as
`shown in figure 2. Any line can be open and
`any two points can be shorted together. The
`circuit in this diagram has a separate Cs bus.
`There are fewer types of faults on substratesin
`which the storage capacitors are connected to
`the adjacent gate line (m+1) or which have no
`added Cs capacitor at all. This figure also
`shows the shorthand nomenclature used to
`namethe faults. Note that we call the TFT
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`
`
`S=Shoi @—*
`O = Open *
`GL « Gate Line, DL = Drain Une,
`CB -Cs Bus
`T«TFT, P= Pixel, N= Next, V= Vertical, H = Horzontal
`
`Possible Faults
`Figure 2
`connection to the data line the drain, while some
`callit the source. (The advantageofcallingit the
`drain is that the "D" can represent both data and
`drain).
`
`Most "hard"faults, true opens or shorts, are
`easily detected andlocated. All of the hard faults
`have "soft" versions; opensthat are not quite
`open, and, more common, high resistance
`shorts due to leakage resistance. The most
`important of these is leakage across the storage
`capacitor and from thepixelto gate line because
`these affect the ability of Cs to hold a charge.
`Other soft faults are low TFT "on" conductance
`(or a "weak" TFT) and high TFT "off"
`conductance (a “leaky" TFT). The ability to
`detect soft faults depends on how small their
`effect is and on the sensitivity of the system.
`The latter is limited by noise and can be
`improved by taking more time to make the
`measurements.
`
`and assign limits which we wantto be as tight
`as possible to help catch soft faults. Even
`though the A C and A G values are quite
`constant over the panel area, they can vary
`because ofattenuation and phase shift along the
`gate and drain lines. Thus a local normal value
`must be determined if tight limits are to be set.
`One way to do this is to measure a block of
`pixels, exclude bad pixels that exceed broad
`limits and average the values of the remaining
`ones.
`
`Detection requires good precision, but not
`high accuracy because, for testing, we are
`looking for differences between pixels, not
`actual pixel parameter values. The detectors
`must have equal sensitivities so that equal pixels
`on different drain lines will not give different
`measurements. Each detector has a precision
`conductance standard and these are used for
`calibration before each substrate is measured.
`Moreover, these standards can be calibrated
`easily with an external testfixture.
`
`Detection is optimized by choosing the test
`conditions. For
`sensitive detection of
`capacitance values we wanta high frequencyto
`increase the output current because the
`capacitive currentis proportional to frequency
`(lout = Ein2nfC). However,
`too high a
`frequency will result in large phase shifts that
`will give conductance errors proportional to
`capacitance and visa versa. Generally testing is
`done at a higher frequency than that used for
`measurements which require absolute accuracy.
`
`The ac level should be as high as possible to
`improvethe signal to noise ratio. However, if it
`is large, the dc bias voltages, both positive and
`negative, must be large enoughto preventthe
`large ac from turning the TFTs on oroff or from
`causing excessdistortion. The dc bias should be
`high enoughto turn the TFTson, but not so full
`on that even weak TFTs conduct so well that
`they can't be detected. Ac and dc voltages and
`frequency are programmableso thattheir values
`may be optimized for a specific substrate type.
`
`for
`Many substrates use parallel TFTs
`redundancy. A short in either TFT is a hard
`fault, but an open in one has a small effect and
`perhaps should not be called a fault at all.
`However, wecan usually detect an open in one
`TFT and can often determine whetherthe open
`is in the gate, drain or source by measuring the
`
`MethodsofFaultIdentification
`effective Cgs (gate-source) capacitance.
`The system stores the location of faults that
`are detected bythe foot screening test discussed
`Meansofdetection
`above, but it does not store the test date.
`All faults affect either A C or AG so that
`Therefore,the first step of fault identification is
`these measured valuesare tested againstlimits.
`to repeat the measurements of eachfailed pixel.
`To do this we have to know the normal values
`
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`averaged can be chosen to optimize the trade-off
`Nopass/fail test is made, instead the new data
`between accuracy and speed. This improved
`for each pixel are subjected toaseriesof tests
`data is then used totest for the final categories
`that categorize those hard faults whose
`of faults.
`characteristics are easily detected. This is very
`fast because these tests are just numerical
`comparisons. Their order is important (see
`categories 1 to 5 in Table 1). The first tests are
`for gross shorts (large Goff and A G) because
`these can overload the detector giving
`meaningless A C values which would cause
`erroneous diagnostic decisions. These are
`followed by several tests of A C with the most
`easily detected faults first
`to reduce the
`possibility of erroneousclassification.
`Tabla 1
`Simplified Identification Program (Preliminary)
`whan have Cs Bus and Redundant TFTs
`
`Once categorized to a group of faults with
`similar data, more electrical tests are made to
`determine the specific fault type (see Table 1).
`In some cases only one more measurementis
`necessary to determinethe specific fault type but
`usually more than one is needed. Often, an
`additional test is made after identification to
`verify the decision. These measurements take
`added time. We expect that it will usually take
`less than 100 msto identify a fault in thefirst
`five categories and somewhatlongerfor the last
`categories depending on the number of
`measurements averaged (about 10 ms per
`measurement). If there are thousandsoffaults,
`this would add appreciablyto the test time, but
`it would not be practical to repair such a poor
`substrate. The test program allows a maximum
`numberoffaults to be set and testing is aborted
`if this numberis exceeded.
`
`1,
`
`2
`
`3.
`
`4,
`
`5.
`
`6
`
`7.
`
`8.
`
`IF Gott Very High MEASURE Gott with Ecs = 0
`IF Goff high: GLDS or TGDS(in parallel)
`IF NOT: CBOLS
`IF AG Very High MEASURE 4 G with Ecs = 0
`IF 4G high: TGSS or PGLS(in parallel)
`IF NOT: PCBS (Cs shored)
`IF AC-OMEASUREAC of pixel to night
`IF AG =0: Possible GLO
`VERIFY by testing more pixzals.
`IF NOT MEASURE AC ol adjacent up or down
`IF AC = 0: Possibla DLO
`VERIFY by measuring more pixels.
`IF NOT MEASURE with ac on Next Gale Line
`IF AG high: PNGL
`IF NOT MEASURE Cott above and below
`IF Cott high: TOSS of PDLS (parallel)
`IF NOT MEASURE Coll right and left.
`IF Golf high: PNDLS.
`IF NOT TDO or TGO (both TFTs open)
`IF AG~CosMEASURE AC let & right.
`IF AC ~ Cgsfor both: CBO
`IF NOT: TSO (both TFTs open)
`IF AC High MEASURE AC above & below
`IF AC either high: PPVS
`[[Measure Pixel N Times and Average]]
`
`IF A Slightly Low Test A C Gs(series value)
`IF ACs Low MEASURE AC with Ecs=0
`IF 4C high: ATDO (A = redundant)
`IF AC Normal: ATSO or WkTFT (Wk = weak)
`IF AC Low: MEASURE Got
`IF Gott high: TOSLK (Lk = leakage)
`IF NOT:RTGO
`F
`IF 4GsNOT low MEASURE AC left & right
`IF AC low: CBGLS
`VERIFY by Measuring 4 C along gate line
`IF NOT: possible PPHS, continue program
`If AGHigh MEASURE AG with Ecs=0
`IF AG low: PCBLk (cs has leakaga)
`IF NOT: TGSLk or PGLLK (parallal leakage)
`IF Golf High MEASURE Goll with Ecs = 0
`IF Golf High: GLUDLLK, TGDLk or TOSLK
`IF NOT: CBDLK
`
`The pixels that pass these first tests are those
`with soft faults, or with hard faults that are
`difficult to detect, and good pixels thatfailed the
`initial pass/fail test because of measurement
`imprecision. More precision is needed to
`separate out the good pixels and to identify the
`faults of the bad. Therefore the next step is to
`tepeat the measurements several
`times and
`average the results, with the number of
`
`Page 4 of 5
`
`The type and location ofall faults is stored
`and can be printed out or sent to a remote
`computer. This is necessary for the repair
`operation. The number of occurrences of each
`fault type is also listed for quality control
`purposes.
`
`Someof the special tests madeare listed below
`and in the test program of Table 1.
`
`Several categories use a test with ac only on
`the gate line becauseit distinguishes between
`shorts or leakage resistances to the gate line and
`those to the Cs bus. Thusthis test is used when
`Goffor A G is high. Testing with ac only on the
`Cs bus would also distinguish between these
`faults and this test could be used for
`verification.
`
`Testing with ac only on the gate line gives a
`better measurement of Cgs because A C = Cgs
`in this case, not Cgs + Cs. Thus, we want to
`use this test when we want to measure Cgs
`accurately to locate an open in a redundant TFT.
`
`' Testing the adjacentpixels, above, below,
`left and right, can distinguish line opens from
`
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`single pixel faults. If A C = 0, the cause could
`be a open gate or drain line (GLO or DLO), but
`if the pixels above and below are normal it can't
`be a DLOandifthose to both sides are normal it
`can't be a GLO. However, if A C for an
`adjacentpixel does equal zero, it does not prove
`that there is an open because that could be the
`result of some other type of fault. A line open
`should be verified by testing more pixels along
`the line in question.
`
`conductance and the normal A C which are
`series [2]. This works well and the abnormal
`series value, A Gs, of a weak TFT is markedly
`lower thanthat for a good pixel particularly if
`the effect is exaggerated by reducingthe de bias
`voltage.
`
`Soft faults due to leakage resistance give
`slightly high Goff or A G values. These high
`resistance values can be measured more
`accurately using a lower frequency to reduce
`
`
`*TestingCoffalongDrainLines,
`hase shift errors. However, absolute accuracy
`The cause of a A C = 0 measurement could
`is not required for identification of these faults if
`also be a TFT D-S short (TDSS or PDLS). This
`the measured values of normal pixels are
`will also make Coff high for this pixel (by A C)
`known,andtesting at the a lower frequency
`and for all pixels along its drain line. Testing
`usually does not improve precision.
`Coff for the pixel measured should identify this
`fault and testing pixels above and below for a
`Summary
`high Coff can verify it. Similarly a short from
`A procedure for identifying faults on TFT-
`the pixel to the next drain line (PNDLS) will
`LCD substrates has been outlined that
`cause a very low ACbutwill cause a high Coff
`determinesthe type of any specific fault froma
`for all measurements on the next drain line
`larger numberofpossible fault types. Thisfirst
`(n+1).
`categorizes the fault into one of several groups
`by testing the measurementdata against various
`
`
`« oelad Signaltothe Next Gate li
`
`
`limits.
`Then, depending on this initial
`A very low A C can be the result of a short
`classification, more measurementsof different
`from the pixel to the next gate line (PNGLS).
`types are made that lead to an exact diagnoses in
`This can be easily found by applying a signal
`most cases. The order of these tests and
`(ac only) to that gate line which will give a iarge
`measurements is important in optimizing the
`A G if that fault is present. This is a test
`accuracyofidentification and reducing the time
`connection normally only used in testing
`required.
`spears that have the Cstied to the next gate
`
`ine.
`
`This fault identification capability should be
`very valuable to substrate manufacturers
`because it allows them to decideif a fault can be
`repaired and aids in improving their fabrication
`process.
`
`Anunusual test is made to find weak TFTs or
`an open TFT in parallel with a good one.In this
`case we want to determine abnormally low TFT
`"on" conductance. The TFT conductanceis in
`series with the capacitance Cs + Cgs whichis
`the normal A C capacitance if the TFT is fully
`1. Hall, H.P. and Pilotte, P.R.
`on. If low, this TFT conductance makes A C
`“Testing TFT-LCD Substrates with a Transfer
`slightly low and AGslightly high. This
`Admittance Method"
`combination can be difficult
`to recognize
`Paper 32.6, S.I.D. '91 Digest of Papers
`because both conditions are caused by other
`typesof faults. Converting to equivalent series
`conductance, A Gs, makesthis fault much more
`apparent.
`
`References:
`
`2. Pilotte, P.R.
`"Modeling and Characterization of TFT-LCDs
`Using a Transfer Admittance
`Method" Paper 21.2, S.LD. '92 Digestof
`Papers
`
`The AG and AC normally measured are
`equivalentparallel quantities being obtained
`from the real and imaginary parts of admittance.
`If we convert them into equivalent series
`quantities we should measure the TFT
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