I 1111111111111111 11111 1111111111 1111111111 11111 1111111111 111111111111111111
`US007599015B2
`
`c12) United States Patent
`Lee et al.
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 7,599,015 B2
`Oct. 6, 2009
`
`(54) THIN FILM TRANSISTOR ARRAY PANEL
`AND A METHOD FOR MANUFACTURING
`THESAME
`
`(75)
`
`Inventors: Young-Wook Lee, Suwon-si (KR);
`Jang-Soo Kim, Suwon-si (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Suwon-Si (KR)
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 476 days.
`
`(21) Appl. No.: 11/487,837
`
`(22) Filed:
`
`Jul. 17, 2006
`
`(65)
`
`Prior Publication Data
`
`US 2007/0046847 Al
`
`Mar. 1, 2007
`
`(30)
`
`Foreign Application Priority Data
`
`Aug. 26, 2005
`
`(KR)
`
`...................... 10-2005-0078742
`
`(51)
`
`Int. Cl.
`G02F 11136
`(2006.01)
`(52) U.S. Cl. ........................................................ 349/43
`( 58) Field of Classification Search . ... ... ... ... .. ... . 349/ 42,
`349/43, 139, 141, 143, 148
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`7,190,419 B2 * 3/2007 Park ............................ 349/43
`
`7,211,827 B2 *
`7,528,917 B2 *
`2004/0070717 Al *
`2004/0105051 Al*
`2009/0079888 Al *
`
`5/2007 Lee et al. ...................... 257 /72
`5/2009 Kim et al .................... 349/141
`4/2004 Hong et al. ................. 349/141
`6/2004 Chuang et al. .............. 349/106
`3/2009 Nakayoshi et al. ............ 349/38
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`KR
`KR
`KR
`
`2000-111957
`2000-292801
`2002-258262
`2003-131240
`1999-0035922
`1020020063498
`1020040084488
`
`* cited by examiner
`
`4/2000
`10/2000
`9/2002
`5/2003
`5/1999
`8/2002
`10/2004
`
`Primary Examiner-Sarah Song
`(7 4) Attorney, Agent, or Firm-F. Chau & Associates, LLC
`
`(57)
`
`ABSTRACT
`
`A thin film transistor array panel includes a substrate; a plu(cid:173)
`rality of gate lines that are formed on the substrate; a plurality
`of data lines that intersect the gate lines; a plurality of thin film
`transistors that are connected to the gate lines and the data
`lines; a plurality of color filters that are formed on upper parts
`of the gate lines, the data lines, and the thin film transistors; a
`common electrode that is formed on the color filters and that
`includes a transparent conductor; a passivation layer that is
`formed on an upper part of the common electrode; and a
`plurality of pixel electrodes that are formed on an upper part
`of the passivation layer and that are connected to a drain
`electrode of each of the thin film transistors.
`
`17 Claims, 14 Drawing Sheets
`
`191
`
`180p 270 110
`
`230 180q
`
`154155124 163
`
`Page 1 of 22
`
`Tianma Exhibit 1005
`
`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 1 of 14
`
`US 7,599,015 B2
`
`FIG.I
`
`III'
`
`III
`
`IV
`
`171
`
`191a}
`191
`191b
`l75
`235,185
`II
`
`Page 2 of 22
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`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 2 of 14
`
`US 7,599,015 B2
`
`FIG.2
`
`180p 270 110
`
`230 180q
`
`175
`
`154165124163
`
`FIG.3
`
`181 81
`
`182 82
`
`180q 180p 140
`
`129
`
`110
`
`179
`
`FIG.4
`
`186 276
`
`86
`
`180p 270
`
`110
`
`1 6
`
`18 q
`
`Page 3 of 22
`
`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 3 of 14
`
`US 7,599,015 B2
`
`FIG.5
`Vlb"
`
`I
`
`Vlb'
`t
`
`__ :t-•j----Y--\ --=--
`
`124
`
`121
`
`V lb~
`
`Vlb
`
`Vic~
`
`Vic
`
`126
`
`Vla
`
`Via
`
`D---......__
`
`121
`
`Page 4 of 22
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`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 4 of 14
`
`US 7,599,015 B2
`
`FIG.6A
`
`110
`
`124
`
`FIG.6B
`
`----+------+----~--------
`
`110
`
`129
`
`FIG.6C
`
`110
`
`126
`
`Page 5 of 22
`
`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 5 of 14
`
`US 7,599,015 B2
`
`FIG.7
`Vlllb"
`t
`
`Vlllb'
`t
`
`]S,---~~--~ -C::J-
`
`Vlllb
`
`154 124
`
`121
`
`VIiie
`
`~ Ville 126
`
`vma
`
`VIiia
`
`121
`
`124
`
`Page 6 of 22
`
`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 6 of 14
`
`US 7,599,015 B2
`
`FIG.8A
`
`(
`)
`110
`
`'
`
`I
`
`I
`I
`
`I
`
`I
`
`'
`
`J
`I
`I
`154 164
`
`\
`
`I
`
`124
`
`FIG.8B
`
`FIG.SC
`
`140 129
`
`110
`
`I
`110
`
`126
`
`Page 7 of 22
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`

`

`U.S. Patent
`US. Patent
`
`Oct. 6, 2009
`Oct. 6, 2009
`
`Sheet 7 of 14
`Sheet 7 0f 14
`
`US 7,599,015 B2
`US 7,599,015 B2
`
`FIG.9
`179 Xb"
`
`Xb'
`
`129
`
`16
`
`Xa
`
`Xb'
`
`Xb
`
`Xe
`Xc
`
`Xe
`Xc
`
`Page 8 of 22
`
`Page 8 of 22
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`

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`U.S. Patent
`
`Oct. 6, 2009
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`Sheet 8 of 14
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`US 7,599,015 B2
`
`FIG.IOA
`
`110
`
`175
`
`154 165 124
`
`173
`163
`
`FIG.10B
`
`140
`
`129
`
`110
`
`179
`
`FIG.lOC
`
`140
`
`110
`
`Page 9 of 22
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`

`

`U.S. Patent
`
`Oct. 6, 2009
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`Sheet 9 of 14
`
`US 7,599,015 B2
`
`FIG.11
`179 Xllb"
`
`XIlb'
`
`Xllc~
`
`Xllc~6
`
`171
`
`175
`235
`
`Page 10 of 22
`
`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 10 of 14
`
`US 7,599,015 B2
`
`FIG.12A
`
`235
`
`180p
`
`110
`
`230 180q
`
`173
`
`163
`
`FIG.12B
`
`180p 140
`
`129
`
`110
`
`179
`
`FIG.12C
`
`180p 140
`
`110
`
`126
`
`Page 11 of 22
`
`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 11 of 14
`
`US 7,599,015 B2
`
`FIG.13
`179
`XlVb"
`
`XlVb'
`
`XlVc
`
`XIVa
`
`175
`235
`
`Page 12 of 22
`
`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 12 of 14
`
`US 7,599,015 B2
`
`FIG.14A
`
`275
`
`235
`
`180p 270 110
`
`175 154155124163 1 3
`
`FIG.14B
`
`180p140
`
`129
`
`110
`
`179
`
`FIG.14C
`276
`
`180p 270
`
`110
`
`126
`
`Page 13 of 22
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`

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`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 13 of 14
`
`US 7,599,015 B2
`
`XVIb'
`
`FIG.15
`
`82
`
`XV1b'1a1
`
`]51...._2_9_"""\...;:=..,"79±:=H-----~~~ry=j:l.=H-(cid:173)
`
`XVlb
`
`XVIa
`
`175
`235,185
`
`XVla
`
`Page 14 of 22
`
`

`

`U.S. Patent
`
`Oct. 6, 2009
`
`Sheet 14 of 14
`
`US 7,599,015 B2
`
`FIG.16A
`
`180p 270 110
`
`230 180q
`
`l 3
`
`FIG.16B
`182
`
`181
`
`129
`
`1 0
`
`179
`
`180q
`
`FIG.16C
`186 276
`
`180q 270
`
`110
`
`1 6
`
`Page 15 of 22
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`

`

`US 7,599,015 B2
`
`1
`THIN FILM TRANSISTOR ARRAY PANEL
`AND A METHOD FOR MANUFACTURING
`THESAME
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This application claims priority to Korean Patent Applica(cid:173)
`tion No. 10-2005-0078742, filed in the Korean Intellectual
`Property Office on Aug. 26, 2005, the disclosure of which is 10
`incorporated by reference herein in its entirety.
`
`BACKGROUND OF THE INVENTION
`
`2
`and a plurality of pixel electrodes that are formed on an upper
`part of the passivation layer and that are connected to a drain
`electrode of each of the thin film transistors.
`Each of the pixel electrodes may include a plurality of
`5 branch electrodes that are inclined at an angle to at least one
`of the gate lines or at least one of the data lines, and a
`connection part for connecting the plurality of branch elec(cid:173)
`trodes.
`Each of the branch electrodes may be arranged symmetri(cid:173)
`cally around a center line of the pixel electrode that is parallel
`to one of the gate lines.
`The color filter has an opening and the passivation layer
`may have a contact hole that exposes the drain electrode
`through the opening.
`The common electrode may have an opening that is smaller
`than the contact hole and that exposes a part of the color filter
`on an upper part of the drain electrode, and the passivation
`layer may completely cover the opening of the common elec(cid:173)
`trode.
`The thin film transistor array panel may further include a
`common signal line that is formed in a same layer as the gate
`lines and that is electrically connected to the common elec(cid:173)
`trode.
`The passivation layer may have a first contact hole and the
`25 common electrode may have a second contact hole that
`exposes the common signal line through the first contact hole,
`and a contact member for connecting the common signal line
`and the common electrode through the first and second con(cid:173)
`tact holes may be formed in a same layer as the pixel elec-
`30 trodes.
`Another exemplary embodiment of the present invention
`provides a method of manufacturing a thin film transistor
`array panel including: forming a gate line on an insulation
`substrate; forming a gate insulating layer covering the gate
`line; forming a semiconductor on an upper part of the gate
`insulating layer; forming a data line and a drain electrode in
`an upper part of the gate insulating layer, the data line having
`a source electrode; forming a color filter on upper parts of the
`data line and the drain electrode; forming a common elec(cid:173)
`trode on an upper part of the color filter; forming a passivation
`layer covering the common electrode; and forming a pixel
`electrode on an upper part of the passivation layer.
`The passivation layer may be made of benzocyclobutene
`(BCB) or acryl.
`A common signal line may be formed when forming the
`gate line.
`The passivation layer may have a first contact hole and the
`common electrode may have a second contact hole that
`exposes a common signal line through the first contact hole.
`In this case, the method may further include forming a contact
`member for connecting the common signal line and the com-
`mon electrode through the first and second contact holes in a
`same layer as the pixel electrode.
`The common electrode may be made of poly-crystalline or
`55 amorphous indium tin oxide (ITO) or indium zinc oxide
`(IZO).
`Yet another exemplary embodiment of the present inven(cid:173)
`tion provides a thin film transistor array panel including: a
`substrate; a plurality of gate lines formed on the substrate; a
`60 plurality of data lines intersecting the gate lines; a plurality of
`thin film transistors connected to the gate lines and the data
`lines; a plurality of color filters formed above of the gate lines,
`the data lines, and the thin film transistors; a common elec(cid:173)
`trode formed on the color filters; a first passivation layer
`65 formed on an upper part of the common electrode; a second
`passivation layer formed on an upper part of a drain electrode
`of each of the thin film transistors; and a plurality of pixel
`
`15
`
`20
`
`1. Technical Field
`The present invention relates to a thin film transistor array
`panel, and more particularly, to a thin film transistor array
`panel that uses one substrate of a liquid crystal display and a
`method of manufacturing the same.
`2. Discussion of the Related Art
`A liquid crystal display is one of the most widely used flat
`panel displays. For example, a liquid crystal display is com(cid:173)
`monly found in a variety of electronic devices such as flat
`screen televisions, laptop computers, cell phones, and digital
`cameras.
`A liquid crystal display includes two display panels that are
`formed with a field generating electrode such as a pixel elec(cid:173)
`trode and a common electrode and a liquid crystal layer
`interposed therebetween. The liquid crystal display displays
`images by applying a voltage to the field generating electrode
`to generate an electric field in the liquid crystal layer. The
`electric field determines alignment of liquid crystal mol(cid:173)
`ecules in the liquid crystal layer to control polarization of
`incident light.
`In general, a gate line for transferring a gate signal or a 35
`scanning signal, a data line for transferring an image signal or
`a data signal, a pixel electrode for receiving the image signal,
`and a thin film transistor for controlling the image signal that
`is transferred to a pixel electrode of each pixel are formed in
`a first display panel. Red, green, and blue color filters that are 40
`arranged in each pixel to represent various color images are
`formed in a second display panel that faces the first display
`panel.
`As a size of such a liquid crystal display increases, the
`display panels can become erroneously aligned during a 45
`manufacturing process. Erroneous aligrnnent can lead to
`deterioration of a contrast ratio and a mixed color phenom(cid:173)
`enon. To compensate for this, a width of a black matrix that is
`formed between the pixels is increased. However, as the width
`of the black matrix increases, an aperture ratio of the pixels 50
`decreases.
`Accordingly, there is a need for a liquid crystal display that
`is capable of preventing erroneous alignment of display pan(cid:173)
`els while maintaining an aperture ratio of the pixels.
`
`SUMMARY OF THE INVENTION
`
`An exemplary embodiment of the present invention pro(cid:173)
`vides a thin film transistor array panel including: a substrate;
`a plurality of gate lines that are formed on the substrate; a
`plurality of data lines that intersect the gate lines; a plurality
`of thin film transistors that are connected to the gate lines and
`the data lines; a plurality of color filters that are formed on
`upper parts of the gate lines, the data lines, and the thin film
`transistors; a common electrode that is formed on the color
`filters and that includes a transparent conductor; a passivation
`layer that is formed on an upper part of the common electrode;
`
`Page 16 of 22
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`

`

`US 7,599,015 B2
`
`3
`electrodes formed on an upper part of the first passivation
`layer and that are electrically connected to the drain electrode
`through an opening.
`The common electrode includes an opening exposing a
`part of the color filter, and a part of the first passivation layer 5
`overlaps the opening exposing the part of the color filter to
`form a side of the opening through which the pixel electrodes
`are electrically connected to the drain electrode.
`Each of the pixel electrodes includes a plurality of branch
`electrodes disposed in first and second directions.
`The first passivation layer has a first contact hole, the
`common electrode has a second contact hole, and the second
`passivation layer has a third contact hole that exposes the
`common signal line through the first and seeond contact
`holes, wherein a contact member for connecting the common 15
`signal line and the common electrode through the first, second
`and third contact holes is formed in a same layer as the pixel
`electrodes.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a layout view of a thin film transistor array panel
`for a liquid crystal display according to an exemplary
`embodiment of the present invention.
`FIGS. 2 to 4 are cross-sectional views of the thin film 25
`transistor array panel taken along lines II-II, III-III, and IV-IV
`of FIG. 1, respectively.
`FIGS. 5, 7, 9, 11, 13, and15 are layout views of the thin film
`transistor array panel of FIGS. 1 to 4 during a manufacturing
`process according to an exemplary embodiment of the present
`invention.
`FIGS. 6A to 6C are cross-sectional views of the thin film
`transistor array panel taken along lines VIa-VIa, VIb-VIb'(cid:173)
`VIb", and VIc-VIc of FIG. 5, respectively.
`FIGS. SA to SC are cross-sectional views of the thin film
`transistor array panel taken along lines VIIIa-VIIIa, VIIIb(cid:173)
`VIIIb'-VIIIb', and VIIIc-VIIIc of FIG. 7, respectively.
`FIGS. l0A to l0C are cross-sectional views of the thin film
`transistor array panel taken along lines Xa-Xa, Xb-Xb'-Xb", 40
`and Xe-Xe of FIG. 9, respectively.
`FIGS.12A to 12C are cross-sectional views of the thin film
`transistor array panel taken along lines XIIa-XIIa, XIIb(cid:173)
`XIIb'-XIIb", and XIIc-XIIc of FIG. 11, respectively.
`FIGS.14A to 14C are cross-sectional views of the thin film 45
`transistor array panel taken along lines XIVa-XIVa, XIVb(cid:173)
`XIVb'-XIVb", andXIVc-XIVc ofFIG.13, respectively.
`FIGS.16A to 16C are cross-sectional views of the thin film
`transistor array panel taken along lines XVIa-XVIa, XVIb-
`XVIb'-XVIb", and XVIc-XVIc of FIG. 15, respectively.
`
`50
`
`20
`
`4
`sectional views of the thin film transistor array panel taken
`along lines II-II, III-III'-III", and IV-IV of FIG. 1, respec(cid:173)
`tively.
`A plurality of gate lines 121 and a common signal line 126
`are formed on an insulating substrate 110 that is made of
`transparent glass, plastic, and so forth.
`Each gate line 121 transfers a gate signal and is extended in
`a horizontal direction. Each gate line 121 includes a plurality
`10 of gate electrodes 124 that are protruded in a vertical direc(cid:173)
`tion, and a wide end part 129 for connecting to other layers or
`an external driving circuit. A gate driving circuit (not shown)
`that generates a gate signal may be mounted on a flexible
`printed circuit film (not shown) that is attached to the sub(cid:173)
`strate 110, directly mounted on the substrate 110, or inte(cid:173)
`grated in the substrate 110. When the gate driving circuit is
`integrated in the substrate 110, the gate line 121 is extended to
`directly connect to the circuit.
`The common signal line 126 transfers a common voltage
`that is input from the outside and is positioned adjacent to the
`end part 129 of the gate line 121. The common signal line 126
`is formed in the same layer as the gate line 121 and may have
`an expanding part, as needed.
`The gate line 121 and the common signal line 126 may be
`made of aluminum metals such as aluminum (Al) or an alu(cid:173)
`minum alloy, silver metals such as silver (Ag) or a silver alloy,
`copper metals such as copper (Cu) or a copper alloy, molyb(cid:173)
`denum metals such as molybdenum (Mo) or a molybdenum
`30 alloy, chromium (Cr), thallium (Ta), titanium (Ti), and so
`forth. However, the gate line 121 and the common signal line
`126 may have a multi-layered structure including two con(cid:173)
`ductive layers (not shown) that have different physical prop(cid:173)
`erties. One conductive layer is made of metals having low
`35 resistivity, for example aluminum metals, silver metals, cop(cid:173)
`per metals, and so forth, to reduce a signal delay or a voltage
`drop. Alternatively, the other conductive layer is made of a
`material such as a molybdenum metal, chromium, thallium,
`titanium, and so forth, that have excellent physical, chemical,
`and electrical contact characteristics with other materials,
`specifically indium tin oxide (ITO) and indium zinc oxide
`(IZO). Exemplary combinations of the multi-layered struc(cid:173)
`ture may include a chromium lower layer and an aluminum
`(alloy) upper layer, and an aluminum (alloy) lower layer and
`a molybdenum (alloy) upper layer. However, the gate line 121
`and the common signal line 126 may made of various metals
`or electrical conductors, in addition to the above-described
`materials.
`Side surfaces of the gate line 121 and the common signal
`line 126 are inclined to a surface of the substrate 110, and an
`inclination angle thereof is preferably about 30° to about 80°.
`A gate insulating layer 140 that is made of silicon nitride
`(SiNx), silicon oxide (SiOx), and so forth is formed on the
`gate line 121 and the common signal line 126.
`A plurality of semiconductor islands 154 that are made of
`hydrogenated amorphous silicon (a-Si), polysilicon, and so
`forth are formed on the gate insulating layer 140. Each semi(cid:173)
`conductor island 154 is positioned on a gate electrode 124 and
`includes an extension that covers a border of the gate line 121.
`A plurality of ohmic contacts 163 and 165 are formed on
`the semiconductor islands 154. The ohmic contacts 163 and
`165 may be made of a material such as n+ hydrogenated
`amorphous silicon in which an n-type impurity such as phos(cid:173)
`phorus is doped with a high concentration or silicide. The
`ohmic contacts 163 and 165 are formed in pairs and are
`disposed on the semiconductor islands 154.
`
`DETAILED DESCRIPTION OF EXEMPLARY
`EMBODIMENTS
`
`55
`
`The present invention will now be described more fully
`hereinafter with reference to the accompanying drawings, in
`which exemplary embodiments of the invention are shown.
`The present invention may, however, be embodied in many
`different forms and should not be construed as limited to the 60
`embodiments set forth herein.
`A thin film transistor array panel according to an exem(cid:173)
`plary embodiment of the present invention will be described
`in detail with reference to FIGS. 1 to 4.
`FIG. 1 is a layout view of a thin film transistor array panel 65
`for a liquid crystal display according to an exemplary
`embodiment of the present invention. FIGS. 2 to 4 are cross-
`
`Page 17 of 22
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`US 7,599,015 B2
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`5
`
`5
`6
`Side surfaces of the semiconductor islands 154 and the
`color filters 230 have an opening 235 for exposing a part of the
`ohmic contacts 163 and 165 are also inclined with respect to
`drain electrode 175. The color filters 230 can be formed in a
`a surface of the substrate 110, and an inclination angle thereof
`band shape by extending them in a vertical direction along a
`column of a pixel electrode 191. The color filters 230 can have
`is about 30° to about 80°.
`A plurality of data lines 171 and a plurality of drain elec-
`a side wall of a tapered structure on an upper part of the data
`trodes 175 are formed on the ohmic contacts 163 and 165 and
`line 171, and neighboring edges thereof can become flat by
`the gate insulating layer 140.
`overlapping each other or can be used as a light blocking
`Each data line 171 transfers a data signal and is extended in
`member for blocking light. Each color filter 230 can display
`a vertical direction to intersect the gate lines 121. Each data
`one of three primary colors consisting of red, green, and blue.
`line 171 includes a plurality of source electrodes 173 that are 10
`The lower passivation layer 180p may be omitted.
`extended toward the gate electrode 124, and a wide end part
`A common electrode 270 for receiving a common signal is
`179 for connecting to other layers or an external driving
`formed on upper parts of the lower passivation layer 180p and
`the color filters 230. As shown in FIG. 4, the common elec(cid:173)
`circuit. A data driving circuit (not shown) that generates a data
`trode 270 has a contact hole 276 for exposing the common
`signal may be mounted on a flexible printed circuit film (not
`shown) that is attached to the substrate 110, directly mounted 15 signal line 126 through the gate insulating layer 140 and the
`on the substrate 110, or integrated in the substrate 110. When
`lower passivation layer 180p, and as shown in FIG. 2, the
`common electrode 270 has an opening 275 for exposing the
`the data driving circuit is integrated in the substrate 110, the
`color filter 230 on the upper part of the drain electrode 175.
`data line 171 can be extended to directly connect to the circuit.
`The opening 275 of the common electrode 270 exposes a part
`The drain electrode 17 5 is separated from the data line 171
`20 of the color filter230 for defining the opening 235 of the color
`and faces the source electrode 173 around the gate electrode
`124.
`filter 230. The common electrode 270 is made of a transparent
`One gate electrode 124, one source electrode 173, one
`conductive material such as poly-crystalline, mono-crystal(cid:173)
`drain electrode 175, and the semiconductor island 154 con(cid:173)
`line, or amorphous ITO and IZO. The common electrode 270
`is formed in an area surrounded with the gate line 121 and the
`stitute one thin film transistor (TFT), and a channel of the thin
`film transistor is formed in the semiconductor island 154
`25 data line 171, and is removed in an area in which end parts 129
`between the source electrode 173 and the drain electrode 175.
`and 179 of the gate line 121 and the data line 171 are disposed.
`It is preferable that the data line 171 and the drain electrode
`An upper passivation layer 810q that is made of an organic
`175 are made of a refractory metal such as molybdenum,
`insulating material or an inorganic insulating material such as
`chromium, thallium, and titanium, or their alloys. The data
`silicon oxide or silicon nitride is formed on upper parts of the
`line 171 and the drain electrode 175 can have a multi-layered
`30 common electrode 270, the exposed color filter 230, and the
`lower passivation layer 180p. The organic insulator may pref(cid:173)
`structure including a refractory metal layer (not shown) and a
`low resistance conductive layer (not shown). Examples of the
`erably have a dielectric constant of about 4.0 or less, and may
`multi-layered structures include, for example, a dual layer of
`have photosensitivity, provide a flat surface, and be made of
`a chromium or molybdenum (alloy) lower layer and an alu(cid:173)
`benzocyclobutene (BCB) or an acryl having excellent unifor-
`minum (alloy) upper layer, and a triple layer of a molybde(cid:173)
`35 mity.
`A plurality of contact holes 182 for exposing the end part
`num (alloy) lower layer, an aluminum (alloy) intermediate
`179 of the data line 171 through the lower passivation layer
`layer, and a molybdenum (alloy) upper layer. However, the
`data lines 171 and the drain electrodes 175 may be made of
`180p and a plurality of contact holes 185 for exposing the
`drain electrode 175 through the opening 235 of the color filter
`various metals or electric conductors, in addition to the
`40 230 are formed in the upper passivation layer 180q. A plural(cid:173)
`above-described materials.
`The ohmic contacts 163 and 165 exist only between the
`ity of contact holes 181 for exposing the end part 129 of the
`underlying semiconductor islands 154 and the overlying data
`gate line 121 are formed in the upper passivation layer 180q,
`line 171 and the drain electrode 17 5 to reduce a contact
`the lower passivation layer 180p, and the gate insulating layer
`140. Furthermore, the upper passivation layer 180q has a
`resistance there between. An extension of the semiconductor
`island 154 that is positioned on the gate line 121 smoothes a
`45 contact hole 186 for exposing a part of the common electrode
`surface profile thereof, thereby preventing the data line 171
`270 that defines the contact hole 276 of the common electrode
`from being disconnected. The semiconductor island 154 has
`270 and for exposing the common signal line 126.
`portions that are exposed between the source electrode 173
`A plurality of pixel electrodes 191 and a plurality of contact
`and the drain electrode 175 that are not covered by the data
`assistants 81, 82, and 86 are formed on the upper passivation
`line 171 and the drain electrode 175.
`50 layer 180q. They may be made of a transparent conductive
`The common signal line 126 is disposed in the same layer
`material such as poly-crystalline or amorphous ITO and IZO.
`as the gate line 121, but it may be disposed in the same layer
`The pixel electrode 191 is extended in a horizontal direc(cid:173)
`as the data line 171.
`tion, and includes a plurality of branch electrodes 191a that
`A lower passivation layer 180p is formed on the data line
`overlap the common electrode 270 and includes a connection
`171, the drain electrode 175, and the exposed portions of the
`55 part 191b around the plurality of branch electrodes 191a that
`semiconductor island 154. The lower passivation layer 180p
`commonly connects the plurality of branch electrodes 191a.
`Each branch electrode 191a is inclined to the gate line 121
`is made of non-organic insulators, and the non-organic insu(cid:173)
`lators include, for example, silicon nitride and silicon oxide.
`or is in a horizontal direction at a predetermined angle, and is
`However, the lower passivation layer 180p can have a dual(cid:173)
`arranged symmetrically around a horizontal center line of the
`60 pixel electrode 191 that is parallel to the gate line 121.
`layer structure of a lower inorganic layer and an upper organic
`An outer border of the connection part 191b that defines a
`layer to prevent the exposed portions of the semiconductor
`island 154 from being damaged while having excellent insu(cid:173)
`border of the pixel electrode 191 has a rectangular shape.
`The pixel electrode 191 is physically and electrically con(cid:173)
`lating characteristics of the organic layer.
`A plurality of color filters 230 are formed on the lower
`nected to the drain electrode 175 through the contact hole 185
`passivation layer 180p.
`65 and the opening 235 to receive a data voltage from the drain
`Most of the color filters 230 exist in an area that is sur(cid:173)
`electrode 175. Because the upper passivation layer 180q that
`rounded with the gate lines 121 and the data lines 171, and the
`defines the contact hole 185 completely covers the opening
`
`Page 18 of 22
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`

`

`US 7,599,015 B2
`
`7
`275 of the common electrode 270, the pixel electrode 191 and
`the common electrode 270 are isolated from each other.
`The pixel electrode 191 to which a data voltage is applied
`and the common electrode 270 to which a common voltage is
`applied generate an electric field, thereby determining a 5
`direction of liquid crystal molecules of a liquid crystal layer
`(not shown) that is positioned between the two electrodes 191
`and 270. Polarization of light that passes through the liquid
`crystal layer changes depending on a direction of the liquid
`crystal molecules.
`The pixel electrode 191 and the common electrode 270
`constitute a liquid crystal capacitor by using the liquid crystal
`layer as a dielectric material, thereby maintaining an applied
`voltage even after a thin film transistor is turned off. The
`electrodes 191 and 270 also constitute a storage capacitor by 15
`using the upper passivation layer 180q as a dielectric material,
`thereby strengthening voltage sustainability of the liquid
`crystal capacitor.
`The contact assistants 81 and 82 are connected to the end
`part 129 of the gate line 121 and the end part 179 of the data 20
`line 171 through the contact holes 181 and 182, respectively.
`The contact assistants 81 and 82 complement adhesion
`between the end part 129 of the gate line 121 and the end part
`179 of the data line 171 and an outside apparatus, and protect
`them.
`Furthermore, the contact assistant 86 comes in contact with
`the common signal line 126 that is exposed through the con(cid:173)
`tact hole 276 and the common electrode 270 that is exposed
`through the contact hole 186, whereby the common signal
`line 126 and the common electrode 270 are electrically con(cid:173)
`nected to each other. The common electrode 270 receives a
`common voltage from the common signal line 126.
`In such a thin film transistor array panel, an electric field
`between the common electrode 270 and the pixel electrode
`191 is formed in both a parallel direction and a vertical direc(cid:173)
`tion of the substrate 110, such that the liquid crystal mol(cid:173)
`ecules are inclined while twisting. Therefore, transmittance
`can be improved while securing a wide viewing angle.
`Furthermore, visibility can be increased by disposing the
`branch electrodes 191a in two directions.
`Since the color filter 230 is disposed on the gate line 121,
`the data line 171, and the thin film transistors, erroneous
`alignment with other display panels can be reduced even
`when a size of the thin film transistor array panel increases. In
`addition, an aperture ratio of the pixels can be improved.
`Furthermore, since the common electrode 270 is posi(cid:173)
`tioned between the pixel electrode 191 and the data line 171,
`a parasitic capacitance generated between the pixel electrode
`191 and the data line 171 can be reduced. Accordingly, a
`phenomenon in which vertical line blurs are generated can be 50
`prevented and an erroneous alignment margin between the
`data line 171 and the pixel electrode 191 can be reduced.
`Furthermore, a sustain capacity formed between the elec(cid:173)
`trodes 191 and 270 can be reduced by adjusting a thickness of
`the upper passivation layer 180q formed between the com- 55
`mon electrode 171 and the pixel electrode 191. Accordingly,
`a size of the thin film transistor can be reduced, whereby an
`aperture ratio of the pixels can be improved.
`Now, a method of manufacturing the thin film transistor
`array panel shown in FIGS. 1 to 4 according to an exemplary 60
`embodiment of the present invention will be described in
`detail with reference to FIGS. 5 to 16c.
`FIGS. 5, 7, 9, 11, 13, and15 are layout views of the thin film
`transistor array panel of FIGS. 1 to 4 during a manufacturing
`process according to an exemplary embodiment of the present 65
`invention. FIGS. 6A to 6C are cross-sectional views of the
`thin film transistor array panel taken along lines VIa-VIa,
`
`8
`VIb-VIb'-VIb', andVIc-VIc ofFIG. 5, respectively. FIGS. SA
`to SC are cross-sectional views of the thin film transistor array
`panel taken along lines VIIIa-VIIIa, VIIIb-VIIIb'-VIIIb", and
`VIIIc-VIIIc of FIG. 7, respectively. FIGS. lOA to l0C are
`cross-sectional views of the thin film transistor array panel
`taken along lines Xa-Xa, Xb-Xb'-Xb", and Xe-Xe of FIG. 9,
`respectively. FIGS. 12A to 12C are cross-sectional views of
`the thin film transistor array panel taken along lines XIIa(cid:173)
`XIIa, XIIb-XIIb'-XIIb", and XIIc-XIIc of FIG. 11, respec-
`10 tively. FIGS.14A to 14C are cross-sectional views of the thin
`film transistor array panel taken along lines XIVa-XIVa,
`XIVb-XIVb'-XIVb", and XIVc-XIVc of FIG. 13, respec(cid:173)
`tively. FIGS.16A to 16C are cross-sectional views of the thin
`film transistor array panel taken along lines XVIa-XVIa,
`XVIb-XVIb'-XVIb", and XVIc-XVIc of FIG. 15, respec(cid:173)
`tively.
`As shown in FIGS. 5 to 6C, the gate line