United States Patent 5
`Dai et al.
`
`US005452239A
`[il] Patent Number:
`
`[45] Date of Patent:
`
`5,452,239
`Sep. 19, 1995
`
`[54] METHOD OF REMOVING GATED CLOCKS
`FROM THE CLOCK NETS OF A NETLIST
`FOR TIMING SENSITIVE
`IMPLEMENTATION OF THE NETLIST IN A
`HARDWARE EMULATION SYSTEM
`
`[58] Field of Search .....cssscsssssssesccccssssess 364/578-580,
`364/232.3, 927.81; 371/16.2, 22.1, 22.2, 23, 27;
`340/825.22, 825.06, 825.88, 825.89, 825.83,
`825.84; 307/465, 468, 219, 303; 357/45;
`395/500; 365/201; 370/13, 14, 17
`
`[75]
`
`Inventors: Wei-Jin Dai, Cupertino; Louis
`Galbiati, 111, Mountain View; Joseph
`Varghese, Sunnyvale; Dam V. Bui,
`Milpitas; Stephen P. Sample,
`Mountain View,all of Calif.
`
`[73] Assignee:
`
`Quickturn Design Systems, Inc.,
`Mountain View,Calif.
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,306,286 12/1981 Cocke et al.
`.esscssesseseseeee 364/200
`
`4,578,761
`3/1986 Gray ....cceccceccersseceesseeseeenes 364/481
`4,656,580 4/1987 Hitchcock, Sr. et al... 364/200
`5,109,353 4/1992 Sample et al. owe 364/578
`
`Primary Examiner—Ellis B. Ramirez
`Assistant Examiner—Craig Steven Miller
`Attorney, Agent, or Firm—Lyon & Lyon
`
`[57]
`
`ABSTRACT
`
`[21] Appl. No.: 844
`
`[22] Filed:
`
`Feb. 26, 1993
`
`An emulation system and method that reducesor elimi-
`nates the number of timing errors such as hold time
`violations when implementing a netlist description of an
`integrated circuit. The emulation system comprises a
`plurality of reprogrammable logic circuits and a plural-
`ity of reprogrammable interconnectcircuits. The netlist
`description is optimized to reduce the numberof timing
`Related U.S. Application Data
`violations by removing the occurences of gated clocks
`[63]|Continuation-in-part of Ser. No. 13,025, Jan. 29, 1993,
`from the netlist, partitioning the netlist description by
`abandoned.
`taking into account the occurence oftiming violations
`and ensuring that retain state nets are implemented
`properly.
`
`Int. Ch6 oe G06G 7/48; GO6F 17/00
`[51]
`[52] U.S. CU, cece cecesccssssesseeseetscneesees 364/578; 364/580;
`371/222
`
`2 Claims, 78 Drawing Sheets
`
`N
`
`\
`
`USER SPECIFICATION
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`1
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`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 1 of 78
`
`5,452,239
`
`INTERCONNECT]|INTERCONNECT
`
`LOGIC _ANALYZER/PATTERN|PROBING LOGIC
`
`CHIP
`
`2
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 2 of 78
`
`5,452,239
`
`CONNECTIONS TO EXTERNAL SIGNALS
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`USS. Patent
`
`Sep. 19, 1995
`
`Sheet 3 of 78
`
`5,452,239
`
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`4
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`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 4 of 78
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`5,452,239
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`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 5 of 78
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`5,452,239
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`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 6 of 78
`
`5,452,239
`
`Liz. 7 MIDPLANE CONNECTING
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`ONE MUX BOARD CUTS ACROSS 88 EM BOARD SIGNAL PINS
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`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 7 of 78
`
`5,452,239
`
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`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 8 of 78
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`5,452,239
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`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 9 of 78
`
`5,452,239
`
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`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 10 of 78
`
`5,452,239
`
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`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 11 of 78
`
`5,452,239
`
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`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 12 of 78
`
`5,452,239
`
`STEP 1:
`PREVENTIVE
`MEASURE
`
`TIMING OPTIMIZATION
`
`104
`
`CLOCK TREE ANALYSIS
`
`TIMIZED NETLI
`STEP 2:
`OPTIMIZE
`UST
`INFLUENCING
`MEASURE
`
`TIMING DRIVEN
`
`CONFIGURATION
`
`ENGINE
`
`
`CONFIGURATION
`CONSTRAINTS
`
`INCREMENTAL CONFIGURATION
`
`PHYSICAL
`IMPLEMENTATION]
`
`120
`
`CONSTRUCTIVE
`MEASURE
`
`STEP 4:
`VERIFICATION
`MEASURE
`
`STEP 5:
`FIXING
`MEASURE
`
`TIMING ANALYSIS
`
`ots
`
`
`AUTO DELAY INSERTION
` ANY HOLD
`
`VIOLATIONS
`
` NO
`
`HOLD VIOLATION
`LOCATIONS
`
`EMULATION
`SPEED
`
`DONE
`
`TIMING IN CONFIGURATION PROCESS
`
`£ra.13
`
`13
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 13 of 78
`
`5,452,239
`
`INITIAL OPEN
`
`INCREMENTAL
`
`PARSE
`
`100
`
`PARSE
`
`100
`
`CHANGE RECORDS
`
`0
`LINK & EXPAND
`NETLIST COMPARE|—118
`2
`1
`
`CHANGE RECORDS
`
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`
`10
`
`4
`
`LINK & EXPAND
`
`[102
`
`CLOCK ANALYSIS
`
`10
`
`6
`
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`
`104
`
`CHANGE RECORDS
`
`CHANGE RECORDS
`
`PARTITION
`
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`
`8
`
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`
`|—106
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`CHANGE RECORDS
`
`CHANGE RECORDS
`
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`
`110
`
`PARTITION
`
`|_-108
`
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`
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`112
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`
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`
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`
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`
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`
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`
`|—1 14
`
`READY FOR EMULATION
`
`—CONFIGURATION CONTROL FLOW
`
`£1.14
`
`14
`
`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 14 of 78
`
`5,452,239
`
`USER
`NETLIST OR
`
`CAE DB
`
`CREATE
`
`|
`
`100
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`
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`
`114]
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`
`ANNOTATE
`
`CONFIGURATION DATABASE INTERACTIONS
`
`£1.15
`
`15
`
`15
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 15 of 78
`
`5,452,239
`
`| SYSTEM
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`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 16 of 78
`
`5,452,239
`
`S1_,[ft
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`CONFIGURATION SERVER
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`PARSER PROGRAM
`
`PARSER INTERFACE
`
`£12.17
`
`17
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 17 of 78
`
`5,452,239
`
`ort
`
`”Wire—AND”
`
`MUX CHIP 4 £2.13
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`STEPS IN AND-—tree
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`

`

`US. Patent
`
`Sep. 19, 1995
`
`Sheet 18 of 78
`
`5,452,239
`
`UNOPTIMIZED
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`OPTIMIZED
`
`BUFFER BLASTING
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`—>—
`
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`£12.19
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`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 19 of 78
`
`5,452,239
`
`GROUND SPLITTING
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`AUTOMATIC DELAY INSERTION
`
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`
`20
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`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 20 of 78
`
`5,452,239
`
`LOW SKEW CLOCK SPLITTING
`
`
`
`
`
`£12z.191
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`COMMON SUBEXPRESSION ELIMINATION
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`
`21
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`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 21 of 78
`
`5,452,239
`
`WIRE AND GENERATION
`
`4H
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`"IREAND
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`WIRE AND REMOVAL Li; 19 R
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`
`£12.19
`
`BIDIRECTIONAL UMBILICAL (MULTIPLE DRIVERS)
`(LOADS)
`
`(LOADS)
`
`
`
`22
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 22 of 78
`
`5,452,239
`
`
`
`CLOCK DRIVER CIRCUITRY
`
`
`
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`PROCESS
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`TIMING ALNALYZER
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`
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`PROCESS
`
`ACROSS NETWORKED HETEROGENOUS
`WORKSTATIONS
`
`TIMING ANALYSIS SUB-SYSTEM PROCESS ARCHITECTURE
`
`£1.24
`
`23
`
`23
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 23 of 78
`
`5,452,239
`
`<DESIGN>.QTD
`
`
`
`TIMING FILE FOR
`THE DESIGN
`
`
`TIMING FILE FOR
`MING FILE FOR
`PARTITION 1
`PARTITIONN °
`
`— DENOTES DIRECTORY
`
`|| — DENOTES FILES
`
`THE FILE DIRECTORY STRUCTURE FOR THE TIMING SUBSYSTEM
`
`fig. 22
`
`INTERMEDIATE
`LEVEL
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`TOP LEVEL
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`
`INTERMEDIATE
`LEVEL
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`LEAF LEVEL
`
`PHYSICAL HIERARCHY
`
`Lua. 24K
`
`24
`
`24
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 24 of 78
`
`5,452,239
`
`FUNCTION GENERATOR
`
`APR DELAY BACK ANNOTATION
`INST_1
`
`Liz 29pR
`
`INST_2
` £12.24
`
`ON-CHIP ROUTINE DELAY BACK ANNOTATION
`
`
`
`(0) — ROUTING DELAYS IN THE PHYSICAL IMPLEMENTATION. £2.25
`
`MISSING RE—CONVERGENCE POINT EXAMPLE
`
`25
`
`25
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 25 of 78
`
`5,452,239
`
`QBIC SERVER (TIMING ANALYSIS)
`
`TA COMPUTE SERVER
`
`TIMING ANALYSIS
`PARTITION
`
`INITIATE SPLATTER RUN
`
`
`
` TA
`COMPUTE
`SERVER
`
`
`
`BROADCASTING TA SERVICE
`NEEDED MESSAGE
`
`
`
` TA
`COMPUTE
`SERVER
`
`
`
`PROCESS TA wes
`
`
`REQUESTS
`
`HALT OR
`DONE?
`
`YES
`
`PROCESSING TA RESULTS
`
`CONTROL FLOW-TIMING ANALYSIS
`
`£12.20
`
`e
`
`°
`
`
`
`
`TA
`COMPUTE
`SERVER
`
`
`
`26
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 26 of 78
`
`5,452,239
`
`YSANSS
`
`SLNdNODVi LSANDIY
`ONIAIOIY YAAYAS
`
`
`SLNdNOOVL(SISATVNYONIWIL)YFAYSSOIGO
`
`ASVWL
`
`
`
`
`
`JOVSSAWLIVHONILSVOOVONS
`
`
`
`SALVISJIWHNYNLaY
`
`
`
`
`
`JOVSSINANOGONILSVOGVONE
`
`
`
`NOIILYVdLXAN139
`
`27
`
`
`
`SALWISANOdNanay
`
`
`
`
`
`LSALINNOILILYVd“N39
`
`LeAF
`
`
`
`LS3NO3YASVLVL—MOT
`
`
`TOULNOD JNLOWOLSLAGNI
`
` SHLNYNLAY SLAdWIJYVdsYd SNOILINISAG
`
`
`
`MOO1D3uVdaud
`
`SDCFIMONY
`
`27
`
`
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 27 of 78
`
`5,452,239
`
`QBIC SERVER
`(TIMING ANALYSIS)
`
`PROCESS
`
`QBIC SERVER 1
`
`
`
`TA COMPUTE SERVER
`
`SEND TA TASK REQUEST
`
`-— RECIEVE TA TASK REQUEST
`
`RECIEVE TA DATA
`
`YES
`
`NO
`
`NO
`
`GENERATE MOTIVE INPUT FILES
`
`INITIALIZE MOTIVE|RETURN CODE
`
`
`
`
`INVOKE MOTIVE PROCESS
`
`COMMANDS
`
`ESTABLISH TO/FROM PIPES]sf (MOTIVE PROCESS
`
`
`
`
`
`
`
` CRITICAL
`NO
`PATH REQUESTED
`
`
`
`CAL. CRITICAL PATHS
`
`CAL. SETUP/HOLD MARGINS
`
`
` CLOCK
`
`SPEED REQUESTED
`
`
`
`NO
`
`CAL. CLOCK SPEED
`
`TERMINATING MOTIVE PROC.
`
`CONTROL FLOW — TIMING ANALYSIS ON A PARTITION
`
`28
`
`28
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 28 of 78
`
`5,452,239
`
`
`
`62AT‘SNOLLWINOTWOGIIdS4010AINOINFON3dIGSNIDUWNdNLAS
`
`
`
`
`
`
`
`VIIdd>SqNISYVNdflds
`
`ISATIWAS139
`
`
`
`NISYWNdAlas
`
`
`
`NIDYVANdALSS
`
`O<
`
`
`
`MOO1DJSVAYONI
`
`d44d$
`
`
`
`MOOTJONGSY
`
`d44d$
`
`29
`
`
`
`FHLNOS0VYLdAlds
`
`
`
`SHIVd‘TWILYO
`
`JASVOYOM
`
`29
`
`
`
`
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 29 of 78
`
`5,452,239
`
`
`
`NOIVYNSIANOODJ34y4
`
`NOLLVIOIAGI0H
`
`
`
`SAVTAGLYASNI
`
`ERE
`
`“NOLLVZINELdO
`NOLLYASNI
`
`JI901
`
`AV150
`
`ONIASIGON/ONIMGIA
`
`INASINdYSLNS
`
`NOLLYASNI
`
`WTA
`
`YALIVANYOs
`
`qld
`
`YOLOVYLXA
`
`ObAF
`
`JINGOWNNOILYASN!AVIAGSHL40MOTdSHL
`
`
`
`SOIA_G10HSNOLLYVIOIA
`daadSNOWWOO
`
`
`dnlG10H
`Cona0)/M
`
`NOISSCGauNIIANOO
`Ga4dSyasn/M
`
`dddd$
`
`SISATVNV
`
`ONIWIL
`
`oD
`
`oO
`
`30
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 30 of 78
`
`5,452,239
`
`
`DESIGN ROOT
`
`
` DESIGN
`PREPROCESSOR
`
`
`
`
`MODULE
`MODULE
`PREPROCESSOR
`
`
`
`LINKER
`
`
`
`DESIGN
`
`
` HARD MODULE
`DUMP &
`
`
`LCAs &
`MUXes
`RESULT
`
`TOP-LEVEL ARCHITECTURE OF MODULE CONFIGURATION
`
`£ra. 91
`
`31
`
`31
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 31 of 78
`
`5,452,239
`
`Ul WITH CALLING BACK
`
`
`' COMMUNICATION
`THE MODULAR QB SERVER
`! CHANNEL
`
`
`CONFIGURATION CONTROLLER
`
`MODULE PREPROCESSOR)
`
`(MODULE PREPROCESSOR
`
`
`
`
`
`MODULE P&R
`
`MODULE P&R
`
`THE PROCESS STRUCTURE OF MODULE CONFIGURATION
`
`4a. 32
`
`32
`
`32
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 32 of 78
`
`5,452,239
`
`A
`7
`
`F
`
`E2
`
`°
`
`52
`
`50
`
`-
`
`A
`E1
`
`F
`E2
`
`SYSTEM IMPLEMENTATION
`USER’S TRI-STATE NET
`
`
`FI
`
`.
`
`F
`
`E2
`
`A
`FI
`TARGET SYSTEM
`OR
`*|COMPONENT ADAPTOR 9
`
`OR
`COMPONENT ADAPTOR
`
`TARGET SYSTEM A-
`
`USER'S. TRI-STATE
`
`SYSTEM_IMPLEMENTATION
`
`
`
`£12.34
`
`33
`
`33
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 33 of 78
`
`5,452,239
`
`IMPLEMENTATION £14.35
`SYSTEM
`TRI-STATE
`USER'S
`
`34
`
`34
`
`

`

`5,452,239
`
`DEAF
`
`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 34 of 78
`
`@ASIYdYsINS
`
`LOANNOOUSLNI
`
`JINGOW
`
`LASWdYsLN4
`
`@NOWWYVd 1NOWLYVd
`
`
`
`
`
`
`
`NOUVINIANTIGN!WALSASJIdlLINW
`
`
`
`AWIS-ILS.YaSN
`
`35
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 35 of 78
`
`5,452,239
`
`CASIdYsIN4
`
`LOANNOOUSINI LASIddYsIN3
`
`JTINGOW
`
`
`
`
`
`NOLVINAWNAIDA]WALSASFIdILINW
`
`LEAF
`
`
`
`@NOILMaVd.bNOILLYVd
`
`a0
`
`Lu
`
`36
`
`
`
`JIVIS—ILS.YaSN
`
`36
`
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 36 of 78
`
`5,452,239
`
`HARDWARE UNDER TIMING ANALYSIS
`
`DATA INPUTS
`
`DATA OUTPUTS
`
`SYSTEM
`
`DATA _JOPUTS
`
`TARGET
`
`CONFIGURATION TECHNOLOGY MAPPING
`
`DATA INPUTS
`
`ULATION
`
`EMULATION
`DULL
`
`DATA IOPUTS
`
`ADAPTOR
`
`(SeeBy \D_OUT
`
`COMPONENT
`
`ADAPTOReCSoar.
`
`ENT
`
`EXTERNAL CONNECTIONS AND CONSIDERATIONS IN TIMING ANALYSIS
`
`£12.38
`
`37
`
`37
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 37 of 78
`
`5,452,239
`
`&‘NIVNOGY3dSNNOLYZINLdO31907Cadd¥WNYNLWOINOCrgoor>
`
`
`
`
`
`
`V6EaESNOLIWNYOSSNVULISIN
`
`
`SLYOddYJ3dSLNdNI‘NIVWOGYSN
`ISIN91907
`C3ZINLLdO‘NIVWOd
`
`
`
`YAZATWNYONINIL
`
`Yadd¥WANVN
`
`
`LSHUIENWOISAHd
`
`SAVT40SLV9
`
`RSAVIA
`
`
`
`LOANNOOUSINI
`
`W130
`
`WALSAS
`
`diHO
`
`CAZINILdO
`LOANNOONSINI
`
`
`
`ALNOYPIOV1d
`
`WALSAS
`
`
`
`ALNON?IOVId
`
`dIHO
`
`38
`
`38
`
`
`
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 38 of 78
`
`5,452,239
`
`TIMING ANALYSIS DATA FLOW
`
`EXTERNAL
`
`YZ SPECIFICATIONS
`
`—___> User
`
`DESIGN DATA)
`
`ynQwLEDGE
`
`
`
`DESIGN
`ANALYZER
`TOPOLOGY
`
`
`
`
`
`KNOWLEDGE INPUTS:
`DESIGN INFO:
`~— NET EXCLUSIONS
`— NETLIST
`
`
`— NET GROUPINGS
`— TIMING MODELS
`
`
`
`~ PATH EXCLUSIONS
`~ CLOCK PATH LOGIC
`
`
`~ MOTIVE ENV.
`~ CLOCK DEFENITIONS
`
`
`1/0 DATA TIMING
`SETTINGS
`
`
`
`
`HIERARCHY
`MANAGER
`
`TA PARTITIONS
`
`CLOCK TREE
`ANALYSIS
`
`
`
` MOTIVE
`TIMING
`
`ANALYZER
`
`
`
`LIMITED PATHS
`SETUP MARGINS)
`CHOLD MARGINS
`=
`DATA SYNC
`CLOCK SPEED eee PATH DELAY
`QUERY RESULTS
`TH|
`(CRITICAL PATHS
`
`CALCULATOR|]iccorign PULSE WIDTH
`
`EMULATION\/FIXED HOLD
`SPEED
`VIOLATIONS
`
`£12. 293
`
`39
`
`39
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 39 of 78
`
`5,452,239
`
`EMULATION
`SYSTEM
`
`
`
`EMULATION
`MODULE
`
`
`
`
`SYSTEM INTERCONNECT TIMING MODELLING
`
`£12.40
`
`SYSTEM
`
`SYSTEM
`
`POD TIMING MODELLING
`
`ADAPTER
`
`COMPONENT
`
`COMPONENT ADAPTER TIMING MODELLING £ia. 42
`
`40
`
`40
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 40 of 78
`
`5,452,239
`
`EMULATIONHARDWARE| DATA PATH DELAY
`
`r
`EMULATION HARDWARE
`
`—[cCOMPONENTADAPTERsid:
`| ]
`
`IIl|t!
`
`CLOCK
`
`
` EXTERNAL
`
`
`
`TIMING
`SPEC
`
`
`
`HIERARCHY OF EXTERNAL TIMING INFORMATION
`
`fa, 45
`
`41
`
`41
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 41 of 78
`
`5,452,239
`
`|
`
`oo
`INPUTS
`
`|
`
`peewee n=
`OUTPUTS
`
` EMULATION
`
`MODULE
`
`INPUT/OUTPUT VERIFICATION
`
`BUFFER A EMULATED
`DESIGN
`
`CLK_IN
`
`
`WHERE THE DELAYS FOR:
`BUFFER: MIN 3NS, MAX 6NS
`AND GATE: MIN 5NS, MAX 7NS
`FF(CLK->Q): MIN 2NS, MAX 5NS
`
`AN EXAMPLE OF EXTERNAL INPUT SIGNALS
`
`£12.47
`
`42
`
`42
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 42 of 78
`
`5,452,239
`
`
` OUT
`
`EMULATED
`DESIGN
`
`
`
`CLK_IN
`
`CONSTRAINING
`COMPONENT
`FLIP—FLOP
`SETUP = 10NS
`HOLD = SNS
`TRIGGER = RISING
`
`CLK
`
`Ie
`
`FRAME OF REFERENCE
`PERIOD = 100NS
`|
`bopoo----
`
`L7
`|
`
`S/H CONSTRAINTS =et
`AT THE HYPOTHETICAL SETUP FOR
`|! HOLD FOR
`SETUP FOR
`| HOLD FOR
`PIN "D”
`THE PREVIOUS | THE CURRENT
`THE CURRENT | THE NEXT
`CYCLE(10NS)
`| CYCLE(5NS)
`CYCLE(10NS)
`| CYCLE(SNS)
`|
`|
`{
`{
`TRANSLATED TO OUTPUT [Lu |
`CwI
`_
`PIN "x"
`SETUP = 30NS
`SETUP = 30NS
`HOLD = 5NS
`HOLD = 5NS
`
`S/H CONSTRAINTS
`
`CALCULATING EXTERNAL SETUP AND HOLD TIME LL d,32.
`
`
`
`NET EXCLUSION EXAMPLES ~ PATH ELIMINATION
`
`£1a. 49
`
`43
`
`43
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 43 of 78
`
`5,452,239
`
`
`
`NET EXCLUSION EXAMPLE — FEEDBACK LOOP BREAKING
`
`£12.50
`
`
`
`TE
`
`A NET GROUPING EXAMPLE
`
`£2.51
`
`44
`
`44
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 44 of 78
`
`5,452,239
`
`
`
`
`ICYCLE 0
`
`| CYCLE 1
`
`ICYCLE 2
`
`DELAYED_CLOCK
`
`CLOCK
`
`CLOCK—
`DELAYED_CLOCK |
`
`Fy
`
`DATA}
`
`ES
`
`=y
`
`ca
`
`T=0NS
`
`T=1000NS
`
`ZERO CYCLE SETUP PATH
`
`£2.52
`
`REG_A
`
`REG_B
`
`
`
`CLOCK<100NS>DELAYED_CLOCK
`‘CYCLE 0
`CYCLE 1
`ICYCLE 2
`Ft
`F3
`55
`
`DELAYED_CLOCK!
`DATA
`
`\p=
`
`T=0NS
`
`|
`
`3
`
`|
`T=1000NS
`
`MULTI-CYCLE SETUP PATH
`
`J
`
`=
`
`!
`T=2000
`
`£12.53
`
`45
`
`45
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 45 of 78
`
`5,452,239
`
`A CIRCUIT WITH A GATED LOCK
`
`COMBINATIONAL
`
`
`
`LOGIC F
`
`
`
`
`FLIPFLOP WITH CLOCK ENABLE
`
`GATED—CLOCK OPTIMIZATION
`
`46
`
`46
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 46 of 78
`
`5,452,239
`
`A. ORIGINAL CIRCUIT CLOCK
`B. TRANSFORMED CIRCUIT CLOCK
`
`424.550?LL
`
`ORIGINAL CIRCUIT
`
`£14.55 (oe
`
`TRANSFORMED CIRCUIT
`
`Le. S55
`
`QABB
`
`EXAMPLE OF CLOCK-—GATING LOGIC
`
`47
`
`47
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 47 of 78
`
`5,452,239
`
`A. ORIGINAL CIRCUIT
`
` CLOCK
`
`£1.500
`
`°
`
`Le
`
`ORIGINAL CIRCUIT:
`
`£u4.500
`
`~
`
`Q_A
`
`CBO XC
`
`TRANSFORMED CIRCUIT:
`
`£42.. 56k 0
`
`EXAMPLE OF CLOCK-—GENERATION LOGIC
`
`48
`
`48
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 48 of 78
`
`5,452,239
`
`A. ORIGINAL CIRCUIT
`
`CLOCK
`
`Q7...QN
`
`£12.57
`
`B. NOMALIZED CIRCUIT
`
`Q1...QN CLOCK
`
`Q71...QN
`
`Q1...QN
`
`LE. S7B
`
`C. TRANSFORMED CIRCUIT
`
`A1...NM
`
`4ia. 5TC Q1...QN
`
`Q1...QN
`
`Q1...QN CLOCK
`
`GATED CLOCK TRANSFORMATION
`
`49
`
`49
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 49 of 78
`
`5,452,239
`
`EN2
`
`ENS
`
`EN4
`
`ENS
`
`CLOCK
`ENS CLOCK
`
`DATA
`
`EN1
`
`EN2
`
`EN4
`
`50
`
`50
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 50 of 78
`
`5,452,239
`
`DETERMINE SET S
`OF CLOCK SOURCES
`
`
`
`Ci = FIRST CLOCK
`SOURCE IN S
`
`
`
`
`
`
`FOR ALL FLIPFLOPS Fk IN
`Ci = NEXT CLOCK
`NETLIST,
`INITIALIZE FLAG Fk
`SOURCE IN S
`
`
`(EQ, 1) = TRUE
`
`
`
`
`
`
`FOR EACH FLIPFLOP WHICH
`CANNOT BE TRANSFORMED WITH
`Ci, SET FLAG Fk(EQ, I) = FALSE
`
`
`
`£ia. OI
`
`51
`
`51
`
`

`

`USS. Patent
`
`Sep. 19, 1995
`
`Sheet 51 of 78
`
`5,452,239
`
`STARTING FROM ALL USER—DESIGNATED CLOCK
`NETS IN U, TRACE FORWARD THROUGH
`COMBINATIONAL LOGIC, MARKING ALL
`FLIPFLOP AND LATCH CLOCK INPUTS REACHED.
`
`STARTING FROM ALL FLIPFLOP AND LATCH CLOCK
`INPUTS NOT MARKED IN PREVIOUS STEP, TRACE
`BACKWARD THROUGH COMBINATIONAL LOGIC,
`MARKING FLIPFLOP AND LATCH OUTPUTS REACHED.
`THE SET D OF NETS MARKED IN THIS STEP ARE
`THE DIVIDED CLOCKS.
`
`THE UNION OF SETS U, D, AND C.
`
`STARTING FROM ALL NETS IN SETS U OR D, TRACE
`FORWARD THROUGH COMBINATIONAL LOGIC,
`MARKING ALL NETS REACHED.
`DURING THIS
`PROCESS ACCUMULATE THE SET C OF COMBINED
`CLOCKS; THOSE NETS WHOSE DRIVER BLOCKS
`HAVE TWO DIFFERENT INPUTS REACHABLE FROM
`NETS IN U OR D.
`
`COMPUTE THE SET S OF CLOCK SOURCES AS
`
`£12. G1
`
`52
`
`52
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 52 of 78
`
`5,452,239
`
`
`
`CLOCK STATE = STATE 1
`
`INITIALIZE ALL NETS IN THE
`NETLIST TO STATE P
`
`
`
`
`ASSIGN CLOCK STATE TO
`CLOCK SOURCE Ci
`
`
`PROPAGATE VALUES
`
`
`
`CLOCK STATE = STATE 0
`
`
`
`
`
`
`
`
`
`
`
`
`FOR EACH FLIPFLOP Fk WITH STATE C
`
`ON ITS CLOCK INPUT, SET
`Fk(EQ, I) = FALSE
`
`
`STATE 0
`
`
`£12. OIC
`
`
`
`IN THIS STATE, THE
`DETERMINE,
`FLIPFLOPS WHOSE CLOCK INPUTS CAN
`
`
`BE REACHED VIA PATHS EITHER FROM
`PRIMARY INPUTS NOT GOING THROUGH
`
`
`Ci, OR VIA PATHS WHICH GO THROUGH
`FLIPFLOPS BETWEEN Ci AND THE GIVEN
`CLOCK PIN.
`ASSIGN STATE C 10 SUCH
`FLIPFLOP CLOCK INPUTS.
`
`
`
`
`
`
`53
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 53 of 78
`
`5,452,239
`
`
` FOR EACH PRIMARY INPUT NET Im
`WHICH IS A DIFFERENT NET FROM
`Ci, ASSIGN STATE C TO Im
`
`
`
`
`
`
`FOR EACH FLIPFLOP Fk WHOSE
`CLOCK INPUT STATE IS EITHER STATE
`C OR THE STATE ENTERED WHEN Fk
`IS TRIGGERED, ASSIGN STATE C TO
`THE Q OUTPUT OF Fk
`
`
`
`
`
`
`
`
`
`PROPAGATE VALUES
`
`
`
`STABLE
`CONDITION
`
`REACHED?
`
`54
`
`

`

`
`
`
`
`FOR EACH FLIPFLOP Fk WHOSE
`CLOCK INPUT STATE !S EITHER STATE
`C OR THE STATE ENTERED WHEN Fk
`IS TRIGGERED, ASSIGN STATE C TO
`THE Q OUTPUT OF Fk
`
`
`
`
`
`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 54 of 78
`
`5,452,239
`
`
` FOR EACH PRIMARY INPUT NET Im
`WHICH IS A DIFFERENT NET FROM
`Ci, ASSIGN STATE C TO Im
`
`
`
`
`
`
`
`
`
`
`
`
`
`FOR EACH LATCH Lk WHOSE GATE
`INPUT STATE IS EITHER STATE C OR
`THE STATE IN WHICH Lk IS
`TRANSPARENT, ASSIGN STATE C TO
`THE Q OUTPUT OF Lk
`
`PROPAGATE VALUES
`
`
`
`STABLE
`CONDITION
`REACHED?
`
`
`
`
`55
`
`

`

`USS. Patent
`
`Sep. 19, 1995
`
`Sheet 55 of 78
`
`5,452,239
`
`THE ORIGINAL DESIGN:
` DIN
`
`THE TRANSFORMED DESIGN:
`
`
`
`S1
`
`SN
`CLK.
`
`TRANSFERRING CLOCK PATH LOGIC TO CLOCK ENABLE
`
`li. G2
`
`56
`
`56
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 56 of 78
`
`5,452,239
`
`CLOCK GATING IMPLEMENTATION:
`
`D_CLOCK
`
`CLOCK
`
`D
`
`
`CLOCK ENABLE TRANSFORMATION:
`
`ENABLE
`
`oe —eroces
`
`CLOCK
`
`|
`
`ENABLE
`
`D
`UNDER CLOCK GATING
`
`A <8xX
`
`Co
`
`D_CLOCK
`
`Q
`
`A
`
`<TB
`
`UNDER CLOCK ENABLE:
`>a:
`Q
`A
`FUNCTIONALLY EQUIVALENT TRANSFORMATION EXAMPLE
`
`fa. OF
`
`o7
`
`57
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 57 of 78
`
`5,452,239
`
`CLOCK GATING IMPLEMENTATION
`
`ENABLE
`
`CLOCK
`
`CLOCK ENABLE TRANSFORMATION:
`ENABLE
`
`
`
`
`CLOCK
`
`CLOCK
`
`ENABLE
`
`
`
`A XBXC¢XxX
`OD
`D
`UNDER CLOCK GATING
`
`D_CLOCK
`
`|
`
`|
`
`|
`
`|
`
`Q
`
`A
`
`cB> C
`
`UNDER CLOCK GATING
`
`Q
`
`A
`
`x<
`
`C
`
`FUNCTIONALLY NON—EQUIVALENT TRANSFORMATION EXAMPLE
`
`fia. OA
`
`58
`
`58
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 58 of 78
`
`5,452,239
`
`
`
`ANDED MULTIPLE CLOCKS
`
`Lia 512.
`
`CLK4
`
`CLK2 MODEMUXED MULTIPLE CLOCKS
`
`£iz. ODOD
`
`CLOCK
`
` D_CLOCK
`SIMPLE CASE OF USING DATA AS CLOCK Lu Ol
`
`IZ.
`
`59
`
`59
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 59 of 78
`
`5,452,239
`
`
`
`
`
`
`CLOCK
`
`GENERAL CASE OF USING DATA AS CLOCK
`
`COMBINATIONAL
`LOGIC F
`
`COMBINATIONAL
`LOGIC F
`
`CLOCK
`
`A GENERAL FORM OF CLOCK PATH
`
`Lie° (a9
`
`60
`
`60
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 60 of 78
`
` §,452,239
`
`EN1
`
`EN2
`
`CLOCK
`
`THE TRANSFORMED DESIGN:
`
`THE ORIGINAL DESIGN:
`
`
`EN1
`
`EN2
`
`1
`
`CLOCK ——
`
`PERFORMING LOGIC TRANSFORMATION
`
`£12.70
`
`61
`
`61
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 61 of 78
`
`5,452,239
`
`
`
`
`
`D_CLOCK
`
`ENABLE
`
`EXAMPLE 1 OF SYMBOLIC SIMULATION
`
`£12.71
`
`
`
`
`
`D_CLOCK
`
`ENABLE
`
`EXAMPLE 2 OF SYMBOLIC SIMULATION
`
`£u.72
`
`62
`
`62
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 62 of 78
`
`5,452,239
`
`USER SPECIFICATION
`
`\
`
`/EXTERNAL_
`\_ CLOCKS FS
`~~
`
`\|
`
`
`
`| CLOCK TREE ANALYSIS
`F——.774_
`\/ DMIDED
`‘y-—
`_— i
`\ CLOCKS
`/
`\
`/CLOCKED »\
`oT
`CLOCK NETS;
`(BLOCKS |
`Tt ert
`
` |
`
`!
`
`jf
`|
`!
`|
`
`/
`
`/
`
`/
`
`/
`
`4
`
`“
`
`ye
`
`4
`
`/
`“7
`
`A
`
`“of
`
`uo
`
`aeweesSSLSASSSSASASSYSaLSSSLS SSSyASSASDADY
`
`CONTROL AND DATA FLOW DIAGRAM
`
`£ia.74
`
`63
`
`\
`
`/
`
`it
`i
`|
`|
`!
`|
`I
`!
`
`J
`
`/
`
`/
`
`\\ \
`XN
`‘N \
`slS~
`~.
`\ ooo
`i
`|
`;
`ALL CLOCK ~~
`!
`|
`i
`SOURCES
`|!
`F
`Jot
`INCLUDING
`|
`I
`1 7
`COMBINED
`/
`_-f
`CLOCKS
`7
`“x
`fo
`“TY
`_-——-”
`pe ! fo
`~~
`~
`I ~~7{FUNCT. ‘
`
`
`|
`/\j
`EQUIV.
`j
`/
`GATED CLK !
`(L7|
`REMOVE
`j
`!
`i ~~\capipates
`—hL--—
`2
`_ 7
`/
`=—-—/
`/
`/
`/
`/
`
`63
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 63 of 78
`
`5,452,239
`
`£12.74
`
`DIVIDED_ CLOCK
`
`
`
`
`CLOCK
`
`A DIMDED CLOCK EXAMPLE
`
`CASE 1: GENERATING NEW CLOCKS
`
`
`
`
`CLK_1
`
`CLK_2
`
`COMBINED CLK
`
`
`
`
`CASE 2: SELECTING CLOCKS
`
`COMBINED CLK
`
`
`
`
`CLK_1
`
`CLK_2
`
`SELECT
`
`EXAMPLE OF COMBINED CLOCKS
`64
`
`64
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 64 of 78
`
`5,452,239
`
`EN2
`
`CLOCK
`
`THE ORIGINAL DESIGN: EN1
`THE TRANSFORMED DESIGN:
`
`PERFORMING LOGIC TRANSFORMATION
`
`Lu.70
`
`65
`
`65
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 65 of 78
`
`5,452,239
`
`CLOCK
`
`AFTER GATED CLOCK REMOVE AND
`
`BEFORE GATED CLOCK REMOVE: $2
`CLOCK NET ADJUSTMENTS
`
`AN EXAMPLE OF CLOCK NET ADJUSTMENTS
`
`£12.77
`
`66
`
`66
`
`

`

`
`
`67
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 67 of 78
`
`5,452,239
`
`OPTIMIZER
`
`OPTIMIZED
`NETLIST
`
`
`
`
`
`
`
`CLUSTER STEP 1:
`GATES TO CLUSTERS
`
`
`CLUSTER STEP 2:
`CLUSTERS TO CHIPS
`
`
`
`CLUSTER STEP 3:
`
`CHIPS TO BOARDS
`
`
`IMPROVEMENT
`ITERATIONS
`
`
`
`BOARD IMPROVEMENTS
`
`
`SYSTEM IMPROVEMENTS
`
`
`68
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 68 of 78
`
`5,452,239
`
`OPTIMIZER
`
`
`
`
` _
`
`PATH TIMING
`ESTIMATOR/CALCULATOR
`
`PATH CONSTRAINTS
`GENERATOR
`
`TIMING
`CONSTRAINTS
`
`OPTIMIZED
`
`NETLIST
`GATES TO CLUSTERS
`
`CLUSTER STEP 1:
`CONE PARTITIONING
`AND PATH CLUSTERING
`
`CLUSTER STEP 2:
`
`CLUSTERS TO CHIPS _
`
`CLUSTER STEP 3:
`CHIPS TO BOARDS
`
`IMPROVEMENT
`
`ITERATIONS BOARD IMPROVEMENTS |_|
`
`69
`
`69
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 69 of 78
`
`5,452,239
`
` a”
`
`a“
`
`| !b
`
`7
`
`e“CONE OF INFLUENCE FOR A FLIP-FLOP INPUT
`
`Li 3 d
`IZ.
`
`C
`
`BEFORE PATH—BASED CLUSTERING: PATH LENGTH =
`NEWLY FORMED CLUSTER
`
`Lia° 3 1 D
`
`Leeeee—_7
`AFTER PATH-BASED CLUSTERING: PATH LENGTH = 2
`
`£14.82
`
`STEPS IN FIRST LEVEL CLUSTERING
`
`70
`
`70
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 70 of 78
`
`5,452,239
`
`REGISTER READ/WRITE_ CYCLE
`
`nck LILIWUULULU
`PSYNC-
`LJ
`VALID
`PA[O:15]
`
`PDI INPUT DATA.=X7X6X5X4X3X2X1XO)
`
`PTDO ouTpuT DATAOXZK6XSX4X3KX2X1XO)
`
`ous WATEEWSEXWX
`
`£12.83
`
`LCA _PROGRAM/READBACK
`
`PTCK LILLELLUUUULuu
`PSYNC— LL
`
`VALID
`PA[O:15]
`
`—_—______—__-j,
`(LSBXXXXXX_>
`INPUT DATA
`PTD|
`
`ooPTDO (LSBXXNXKXXX_>)OUTPUT DATA
`
`
`£2.84
`
`JTAG FORMAT
`
`PTCK
`
`PA[O:15]
`
`PTD!
`
`INPUT DATA
`
`LLL Li uu
`
`VALID
`
`PTDO=QUTPUT DATA
`
`PWSXXXOOKOXOOO
`
`£u.85
`
`71
`
`71
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 71 of 78
`
`5,452,239
`
`
`.BIT AND .PIP FOR INCR.
`
`.LCA AND .SCP FILES, AND
`
`PARENT
`APRERV
`PROCESS
`
`
`
` CBLKs, PINS, AND
`
`CONFIG RECORDS
`
`
`.BIT AND .PIP FILES, AND
`.LCA AND .SCP FOR DEBUG ONLY
`RPT FILE, AND
`CHIP LEVEL DELAY FILE.
`
`
`A CALL TO M2Q.
`
`
`
`roCURRENT7
`| ARCHITECHTURE + SPLATTER
`| CONTROL
`
`| ||||| ||||||
`
`NOTES:
`1. CMS AND Q3A ARE SEPA-
`RATE SUBSYSTEMS.
`2. CMS OUTPUTS ARE CON-
`SUMED BY Q3A, BUT STORED
`IN GLOP FOR INCREMENTAL
`TIME.
`3. CBLKs ARE CONSUMED BY
`M2Q TO RECONCILE DELAYS
`WITH LOGICAL NETLIST.
`4. CHIP PLACE AND ROUTE
`IS INTEGRAL WITH QBS,
`SERVER, AND QBIC.
`
`||J|||I[|I|!I|ji||||
`
`CLBS.MDL : CONTAINS CLB GENERATED DELAYS
`DELAY.DEFAULT : CONTAINS ROUTING DELAYS.
`
`£2.86
`
`|| ||||
`
`1. CLB DELAYS ARE
`
`GENERATED BY
`M2Q FROM CBLKs
`
`2. ROUTING DELAYS ARE
`INSTALLED IN THE
`DELAY.DEFAULT FILE BY
`
`Lo =
`
`72
`
`72
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 72 of 78
`
`5,452,239
`
`F.PARENT/MONITOR
`COMM.
`
`
`
`
`
`D.PARENT/
`PARENT
`SCAVANGER
`
`PROCESS
`
`
`
`PROCESS
`
` RPM
`
`
`A.SCAVANGER
`CONTROL &
`
`SCAVANGER
`PROCESS
`
`E.MONITOR/
`SCAVANGER
`
`MONITOR
`PROCESS
`
`QBs
`PROCESS__)FEEDBACK
`
`
`
`
`
`° G.MONITOR/ENGINE
`B.SCAVANGER
`COMM.
`DISK 10
`
`
`
`H.LICENSE MANAGER
`COMMUNICATION
`“ALS BROPOSED 1
`
`I |
`
`||
`
`||
`
`I| | | ||||
`
`|ARCHITECTURE + SPLATTER
`| CONTROL
`| NOTES:
`it. SEPERATE CP&R PROCESS
`
`1.NETLISTS
`; CALLED SCAVANGER AT QBS
`2.CONSTRAINTS
`| HOST.
`3.CHIPDB
`|
` 12. NOW’CHIP ENGINE” PRO-
`
`4.DELAYS
`
`9.IOB swaps
`
`
`
`; CESS CONTAINS VENDOR
`{SPECIFIC CODE.
`13. NO CHIP CONFIG DATA
`| STORED IN THE GLOP.
`14.
`INTERFACES ARE WELL
`| DEFINED
`
`I :|
`
`| !
`
`I
`
`73
`
`||| |
`
`73
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 73 of 78
`
`5,452,239
`
`E1.5 PROCESS, COMMUNICATIONS, CONTROL, AND DATA
`A. SCAVANGER CONTROL AND FEEDBACK TO QBS.
`THE DIRECT COMMUNICATION TO/FROM QBS WITH SCAVANGER WILL BE
`NAMED PIPES.
`THESE CAN BE FOUND AND OPENED BY THE
`QBS PROCESS ONCE THE SCAVANGER PROCESS IS RUNNING.
`DIRECT COMMUNICATION WILL BE LIMITED TO QBS HANDING OFF CHIP
`NAMES AS THEY BECOME AVAILABLE, OR A CONTROL FILE.
`FEEDBACK. MAYBE THERE SHOULD NOT BE ANY DIRECT FEEDBACK FOR
`SIMPLICITY.
`SCAVANGER CAN WRITE STATUS TO A FILE.
`STATUS
`MAY BE ERRORS,
`!’M—ALIVE, AND CHIP COMPLETION/
`DISCONNECTS
`
`B. SCAVANGER DISK 10.
`EXPECTED INPUTS:=NETLIST, CONSTRAINTS, AND POSSIBLY CONTROL
`OTHER INPUTS:
`SIDE FILES TO DEFINE PACKAGE, AND
`ARCHITECTURE, SPEED INFORMATION
`PHYSICAL DATABASE, BACK—ANNOTATION FILE(S) FOR
`DELAYS, CHIP PIN SWAPS.STATUS.
`
`OUTPUTS:
`
`C. QBS DISK 10
`WILL POLL INFORMATION IN THE CHIPS DIRECTORY TO GAIN ADDITIONAL
`STATUS, AND TO EVALUATE RESULTS AS THEY BECOME AVAILABLE (IF
`NECESSARY).
`
`D. PARENT/SCAVANGER COMM.
`LEVERAGE EXISTING SPLATTER COMMUNICATION BETWEEN APRSERV/QBS BY
`MIMICING CODE RIGHT DOWN TO THE ASV AND Q3A ENTRY POINTS.
`SCAVANGER WILL ASSUME THE ROLE OF QBS WHILE COMMUNICATING WITH
`THE CHIP SERVERS.
`
`E. MONITOR/SCAVANGER COMM.
`SAME AS D ABOVE.
`F. PARENT/MONITOR COMMUNICATION.
`SAME AS D ABOVE.
`LEVERAGE THIS CODE COMPLETELY.
`
`G. MONITOR/ENGINE COMM.
`THE ENGINE PROCESS IS A NEW PROCESS THAT IS EXEC’ED BY THE MONITOR
`PROCESS.
`iT WILL HANDLE A COMPLETE PLACE AND ROUTE TASK AND THEN
`EXIT.(EXIT IS STILL TBD).
`
`H. LICENSE MANAGER CONTROL.
`THE SOLUTION HERE IS TBD.
`
`£12.88
`
`74
`
`74
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 74 of 78
`
`5,452,239
`
`ANOTHER VIEW OF THE DATA
`(FILES) BEING COMMUNICATED.
`
`NETWORK
`
`CP&R
`SERVER
`
`CP&R
`SERVER
`
`CP&R
`SERVER
`
`CP&R
`SERVER
`
`CP&R
`SERVER
`
`SCAVANGER:
`Q3B, Q2B
`
`
`
` CHIP
`
`SPECIFIC
`DATA
`
`
`
`
`
`
`1 .QUTPUT
`NETLISTS AND
`°
`CONSTRAINTS
`2.FEEDBACK
`CHIP COMPLETION,
`AND HANDLE
`ANY BACK—
`ANNOTATION
`
`QBIC
`DATA
`
`
`
`
`
`
`STRUCTURES
` CHIP
`SPECIFIC
`
`DATA
`
`
`
` CHIP
`SPECIFIC
`
`DATA
`
`
`
`
` CHIP
`SPECIFIC
`
`DATA
`
`
`
` CHIP
`SPECIFIC
`
`DATA
`
`
`
`\I{|||||||||I||I|I|jIi|||
`
`|
`
`CHIP SPECIFIC DATA
`1, ALL CHIP SPECIFIC
`DATA WILL BE COMMUNICATED|
`TO _SCAVANGER VIA FILES.
`|
`NETLISTS AND CONSTRAINTS
`|
`ARE CREATED BY
`|
`QBS(Q2C).
`2. SCAVANGER WILL COMMU-
`NICATE THE NETLISTS AND
`CONSTRAINTS TO A CP&R
`SERVER.
`3. CP&R SERVERS WILL RE-
`TURN A PHYSICAL DATA-
`BASE, ROUTING AND GATE
`DELAYS, AND IOB SWAPS.
`4. QBS WILL BACK—ANNO-
`TATE DATA AS NECESSARY.
`LeeLLL a
`
`|!||||||J !||
`
`15
`
`75
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 75 of 78
`
`5,452,239
`
`NETWORK COMMUNICATIONS (SPLATTER)
`CHIP PLACE AND ROUTE FRAMEWORK (ASV)
`
`(NEOCAD)
`
`VENDOR #1
`TRANSLATION
`
`VENDOR #1
`CONTROL
`(e.g. PPR)
`
`VENDOR #2
`TRANSLATION
`
`VENDOR #2
`CONTROL
`(e.g. APR)
`
`VENDOR #3
`TRANSLATION
`
`VENDOR #3
`CONTROL
`
`VENDOR #N
`TRANSLATION
`
`VENDOR #N
`CONTROL
`
`
`
`QT
`
`INTERPRET
`CONTROL
`
`CONTROL
`
`
`
`FILE
`
`VENDOR
`
`
`VENDOR
`ENGINE
`
`NETLIST
`PROCESS
`
`
`
`
`
`QT PRO
`FORMAT
`TRANSLATE
`
`
`
`PRIETARY
`
`
`NETLIST
`
`NETLIST
`
`
`
`
`
`FILTER
`
`
`
`QT DLY
`
` VENDOR DB
`DELAYS &
`
`FORMAT
`
`PIN SWAPS
`
`
`76
`
`76
`
`

`

`USS. Patent
`
`Sep. 19, 1995
`
`Sheet 76 of 78
`
`5,452,239
`
`
`
`
`CUSTOMER
`NETLIST(S)
`
`
` VENDOR
`LIBRARY
`PARSE &
`LINK
`
`THE VENDOR LIBRARIES AND CUSTOM LI-
`BRARIES WILL DESCRIBE THE FUNCTIONAL
`LEAF LEVEL OF THE CUSTOMER’S TARGET
`TECHNOLOGY.
`THE QT LIBRARY MAPS LOG-
`IC INTO PIECES WHICH CAN BE TREATED IN
`AS TECHNOLOGY INDEPENDENT, AND
`BEARS ATTRIBUTES TO ASSIST IN PACKING.
`
`& CHIP
`SCHEDULING
`
`
`
`
`
`WT
`FUNCTIONS
`
`LIBRARY
`
`LEAF LEVEL FUNCTIONS IN THE
`QT LIBRARY WILL BE GENERIC.
`THE QT LEAF LEVEL DOES NOT
`DEPEND ON ANY VENDOR’S
`FUNCIONALITY.
` NET LISTING
`
`
`
` CHIP LEVEL
`
`QT MACRO
`LIBRARY
`
`TIMING
`MODEL
`SYNTHESIS
`
`LEAF LEVEL FUNCTIONS IN THE
`QT LIBRARY ARE LINKED WITH
`PRIMITIVES AND MACROS IN
`THE VENDOR’S MODELING
`LANGUAGE.
`
`IN THE QT
`MACROS (NON—PRIMITIVES)
`MACRO LIBRARY NEED TO HAVE A TIMING
`MODEL CREATED THAT DESCRIBES THE
`TIMING BEHAVIOR OF THE MACROS TO
`.
`
`TIMING QT TIMING
`(MOTIVE)
`
`MODELS
`
`ANALYSIS
`
`,
`ALL TIMING MODELS WHICH
`|
`| TECHNOLOGY LIBRARIES AND WHERE THEY ARE CON-
`ARE FIXED IN STRUCTURE ARE
`!
`| SUMED
`CONTAINED HERE.
`THESE
`MODELS MAY BE PARAME— ee 4
`
`£2.94
`
`(7
`
`77
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 77 of 78
`
`5,452,239
`
`CLK_NETNAME>>S
`
`INTERNAL CLK SOURCE
`
`CLK_NETNAME
`
`INTERNAL
`
`BACKPLANE
`"BEEFY"
`BUFFER
`
`Le ——_— oo77
`
`BEAFY BUFFER INSERTION
`
`CHIP SOFTWARE DOES NOT ALLOW A
`NET TO RE-ENTER A CHIP.
`HOWEVER,
`SOURCING LOW SKEW NETS IN THE
`SYSTEM REQUIRES THIS BEHAVIOR.
`
`NOTE: "BEEFY BUFFER IS NOT
`PART OF THE LOGICAL NETLIST.
`
`||| | { || | | |||;
`
`78
`
`|i | || | | |
`
`78
`
`

`

`U.S. Patent
`
`Sep. 19, 1995
`
`Sheet 78 of 78
`
`5,452,239
`
`GuvOdXNWJASIYdYSLN3
`
`
`
`
`
`[(42034)00/][(43034)00#}[(3034)001][(43034)00:][(43034)001]
`
`
`
`
`
`EO2F
`
`
`
`d04u)009d03Y)009
`
`GO)
`
`79
`
`79
`
`
`

`

`1
`
`5,452,239
`
`2
`present invention, and showing an architecture having
`two levels, one of a level as depicted in FIG. 2, and a
`second, higherlevel.
`FIG.4 is an illustration of chip connectivity on the
`emulation board of an emulation system in accordance
`with the present invention.
`FIG.5 is an illustration of the lay-out of LCA orlogic
`chips and mux chips (also commonly referred to as
`interconnect chips) on an emulation board of an emula-
`tion system in accordance with the present invention.
`FIG.6 is an illustration of a backplane mux intercon-
`nect.
`FI