`
`
`
`I
`
`D Functionally Equivalent to QS3253
`D 5-W
` Switch Connection Between Two Ports
`D TTL-Compatible Input Levels
`D Package Options Include Plastic
`Small-Outline (D), Shrink Small-Outline
`(DB, DBQ), Thin Very Small-Outline (DGV),
`and Thin Shrink Small-Outline (PW)
`Packages
`
`description
`
`The SN74CBT3253 is a dual 1-of-4 high-speed
`TTL-compatible FET multiplexer/demultiplexer.
`The low on-state resistance of the switch allows
`connections to be made with minimal propagation
`delay.
`
`1OE, 2OE, S0, and S1 select the appropriate
`B output for the A-input data.
`
`The SN74CBT3253 is characterized for operation
`from –40°C to 85°C.
`
`SN74CBT3253
`DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
`
`
`SCDS018I – MAY 1995 – REVISED MAY 1998
`
`D, DB, DBQ, DGV, OR PW PACKAGE
`(TOP VIEW)
`L.)
`16
`15
`14
`13
`12
`11
`10
`9
`
`1 2 3 4 5 6 7 8
`
`1OE
`S1
`1B4
`1B3
`1B2
`1B1
`1A
`GND
`
`VCC
`2OE
`S0
`2B4
`2B3
`2B2
`2B1
`2A
`
`FUNCTION TABLE
`(each multiplexer/demultiplexer)
`INPUTS
`S1
`L
`L
`H
`H
`X
`
`S0
`L
`H
`L
`H
`X
`
`FUNCTION
`FUNCTION
`
`A port = B1 port
`A port = B2 port
`A port = B3 port
`A port = B4 port
`Disconnect
`
`OE
`L
`L
`L
`L
`H
`
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
`Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`
`PRODUCTION DATA information is current as of publication date.
`Products conform to specifications per the terms of Texas Instruments
`standard warranty. Production processing does not necessarily include
`testing of all parameters.
`
`Alp
`
`TEXAS
`I
`INS
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`Copyright 1998, Texas Instruments Incorporated
`
`TCL & Hisense
`Ex. 1005
`Page 1
`
`
`
`
`
`1B1
`
`1B2
`
`1B3
`
`1B4
`
`2B1
`
`2B2
`
`2B3
`
`2B4
`
`6 5 4 3
`
`10
`
`11
`
`12
`
`13
`
`SN74CBT3253
`DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
`
`
`SCDS018I – MAY 1995 – REVISED MAY 1998
`
`logic diagram (positive logic)
`
`7
`
`1A
`
`9
`
`2A
`
`L
`
`00000000
`-1.-•-1>
`
`14
`
`2
`
`1
`
`S0
`
`S1
`
`1OE
`
`15
`
`2OE
`
`absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
`
`–0.5 V to 7 V
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Supply voltage range, VCC
`Input voltage range, VI (see Note 1)
`–0.5 V to 7 V
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Continuous channel current
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`128 mA
`Input clamp current, IK (VI/O < 0)
`–50 mA
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Package thermal impedance, q JA (see Note 2): D package
`113°C/W
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`131°C/W
`DB package
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`139°C/W
`DBQ package
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`180°C/W
`DGV package
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`149°C/W
`PW package
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`–65°C to 150°C
`Storage temperature range, Tstg
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
`functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
`implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
`NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
`2. The package thermal impedance is calculated in accordance with JESD 51.
`
`TEXAS
`INSTRUMENTS
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`TCL & Hisense
`Ex. 1005
`Page 2
`
`
`
`
`
`SN74CBT3253
`DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
`
`
`SCDS018I – MAY 1995 – REVISED MAY 1998
`
`recommended operating conditions (see Note 3)
`
`UNIT
`V
`Supply voltage
`VCC
`V
`High-level control input voltage
`VIH
`V
`0.8
`Low-level control input voltage
`VIL
`°C
`85
`–40
`Operating free-air temperature
`TA
`NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
`Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
`
`MIN MAX
`4
`5.5
`2
`
`electrical characteristics over recommended operating free-air temperature range (unless
`otherwise noted)
`PARAMETER
`
`VCC = 4.5 V,
`VCC = 5 V,
`VCC = 5.5 V,
`Control inputs VCC = 5.5 V,
`Control inputs VI = 3 V or 0
`A port
`B port
`
`
`
`VO = 3 V or 0VO = 3 V or 0,
`
`TEST CONDITIONS
`II = –18 mA
`VI = 5.5 V or GND
`VI = VCC or GND
`IO = 0,
`One input at 3.4 V, Other inputs at VCC or GND
`
`MIN TYP† MAX
`–1.2
`±1
`3
`2.5
`
`
`
`OE VOE = VCC
`
`3.5
`10
`4
`
`UNIT
`V
`m A
`m A
`mA
`pF
`
`
`
`pFpF
`
`VCC = 4 V,
`TYP at VCC = 4 V
`
`VI = 2.4 V,
`
`II = 15 mA
`
`VCC = 4.5 V
`
`VI = 0
`VI = 0
`
`II = 64 mA
`II = 30 mA
`II = 15 mA
`
`5
`5
`10
`
`7
`7
`15
`
`VI = 2.4 V,
`† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
`‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
`§ Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
`by the lower voltage of the two (A or B) terminals.
`
`VIK
`II
`ICC
`ICC‡
`Ci
`
`
`
`Ci (OFF)Cio(OFF)
`
`
`ron§on
`§
`
`switching characteristics over recommended operating free-air temperature range, CL = 50 pF
`(unless otherwise noted) (see Figure 1)
`
`PARAMETER
`
`tpd¶
`tpd
`
`t
`ten
`
`
`
`tditdis
`
`FROM
`
`(INPUT)(INPUT)
`
`A or B
`
`S
`
`S
`
`OE
`
`S
`
`TO
`
`(OUTPUT)(OUTPUT)
`
`B or A
`
`A or B
`
`A or B
`A or B
`
`
`
`A or BA or B
`
`VCC = 4 V
`
`MIN MAX
`0.35
`
`VCC = 5 V
`± 0.5 V
`MIN MAX
`0.25
`
`6.6
`
`7.1
`
`7.3
`
`7.9
`
`1.6
`
`1.3
`
`1.4
`
`1.1
`
`6.2
`
`6.3
`
`6.4
`
`7.4
`
`UNIT
`
`ns
`
`ns
`
`ns
`ns
`
`
`
`nsns
`
`7
`2.3
`7.3
`OE
`¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
`driven by an ideal voltage source (zero output impedance).
`
`Alp
`
`TEXAS
`I
`INS
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`TCL & Hisense
`Ex. 1005
`Page 3
`
`D
`W
`
`
`SN74CBT3253
`DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
`
`
`SCDS018I – MAY 1995 – REVISED MAY 1998
`
`PARAMETER MEASUREMENT INFORMATION
`
`From Output
`Under Test
`CL = 50 pF
`(see Note A)
`
`500 W
`
`S1
`
`7 V
`Open
`
`GND
`
`500 W
`
`LOAD CIRCUIT
`
`Input
`
`1.5 V
`
`1.5 V
`
`tPLH
`
`tPHL
`
`Output
`
`1.5 V
`
`1.5 V
`
`3 V
`
`0 V
`
`VOH
`
`VOL
`
`Output
`Control
`(low-level
`enabling)
`
`Output
`Waveform 1
`S1 at 7 V
`(see Note B)
`
`Output
`Waveform 2
`S1 at Open
`(see Note B)
`
`tPZL
`
`tPZH
`
`TEST
`tpd
`tPLZ/tPZL
`tPHZ/tPZH
`
`S1
`Open
`7 V
`Open
`
`1.5 V
`
`1.5 V
`
`
`
`3 V
`
`0 V
`
`3.5 V
`
`tPLZ
`
`1.5 V
`
`1.5 V
`
`VOL + 0.3 V
`VOL
`
`tPHZ
`
`VOH
`VOH – 0.3 V
`
`0 V
`
`VOLTAGE WAVEFORMS
`PROPAGATION DELAY TIMES
`
`VOLTAGE WAVEFORMS
`ENABLE AND DISABLE TIMES
`
`NOTES: A. CL includes probe and jig capacitance.
`B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
`Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
`C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W
`, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
`D. The outputs are measured one at a time with one transition per measurement.
`E.
`tPLZ and tPHZ are the same as tdis.
`F.
`tPZL and tPZH are the same as ten.
`G.
`tPLH and tPHL are the same as tpd.
`
`Figure 1. Load Circuit and Voltage Waveforms
`
`TEXAS
`INSTRUMENTS
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`TCL & Hisense
`Ex. 1005
`Page 4
`
`
`
`IMPORTANT NOTICE
`
`Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
`any product or service without notice, and advise customers to obtain the latest version of relevant information
`to verify, before placing orders, that information being relied on is current and complete. All products are sold
`subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
`pertaining to warranty, patent infringement, and limitation of liability.
`
`TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
`accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
`TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
`performed, except those mandated by government requirements.
`
`CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
`DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
`APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
`WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
`CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
`BE FULLY AT THE CUSTOMER’S RISK.
`
`In order to minimize risks associated with the customer’s applications, adequate design and operating
`safeguards must be provided by the customer to minimize inherent or procedural hazards.
`
`TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
`that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
`intellectual property right of TI covering or relating to any combination, machine, or process in which such
`semiconductor products or services might be or are used. TI’s publication of information regarding any third
`party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
`
`Copyright 1998, Texas Instruments Incorporated
`
`TCL & Hisense
`Ex. 1005
`Page 5
`
`