(12) United States Patent
`Benyamin et al.
`
`USOO6531931B1
`US 6,531,931 B1
`Mar. 11, 2003
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) CIRCUIT AND METHOD FOR
`EQUALIZATION OF SIGNALS RECEIVED
`OVER A COMMUNICATION SYSTEM
`TRANSMISSION LINE
`
`(75) Inventors: Saied Benyamin, San Jose, CA (US);
`Michael Arthur Brown, San Jose, CA
`(US); Ramin Shirani, Morgan Hill, CA
`(US)
`(73) Assignee: Agere Systems Inc., Allentown, PA
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/321,901
`(22) Filed:
`May 28, 1999
`Related U.S. Application Data
`(60) Provisional application No. 60/087.605, filed on Jun. 1,
`1998.
`(51) Int. Cl. ........................... H03H 11/06; H03G 5/16
`(52) U.S. Cl. ....................... 333/18; 333/28 R; 375/230;
`330/304
`(58) Field of Search ................... 33/28 R, 18; 375/229,
`375/230; 330/304, 124 R
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`5,115.213 A * 5/1992 Eguchi ........................ 333/18
`5,337,025 A * 8/1994 Polhemus ................. 333/28 R
`* cited by examiner
`
`Primary Examiner Benny Lee
`Assistant Examiner Stephen E. Jones
`(74) Attorney, Agent, or Firm-Steve Mendelsohn, Ian M.
`Hughes
`(57)
`
`ABSTRACT
`
`A circuit and method for equalization of a communication
`Signal received over a communication System transmission
`line using Switched filter characteristics. Equalization for
`frequency-independent and frequency-dependent attenua
`tion of the communication signal is accomplished with a
`linear equalization channel which includes an input biasing
`circuit which provides a common input Signal to two parallel
`amplifier paths. One path includes a wideband, fixed-gain,
`frequency-independent amplifier Stage. The other path is a
`wideband multiplier amplifier Stage in Series with a
`wideband, frequency-dependent amplifier Stage having a
`Switchable high-pass characteristic. The outputs of the
`fixed-gain wideband frequency-independent amplifier Stage
`and wideband, frequency-dependent amplifier Stage having
`a Switchable high-pass characteristic are both tied in com
`mon to the input of a wideband gain buffer amplifier Stage,
`which has a Switchable high-frequency boost frequency
`response characteristic. Filter characteristic for the
`frequency-dependent amplifier Stages are Selected to accom
`modate predetermined ranges of cable lengths. The amplifier
`Stages are formed as Simple n-MOS transconductance dif
`ferential amplifiers with restive loads and with Switchable
`filter components connected between the legs of the differ
`ential amplifiers.
`
`20 Claims, 20 Drawing Sheets
`
`Inb
`
`317
`
`INPUT
`BASING
`STAGE
`
`
`
`
`
`Equalizer
`DAC 410)
`
`
`
`261 Attenuotor
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`SECOND
`DC GAIN
`
`
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 1 of 20
`
`US 6,531,931 B1
`
`
`
`WèJO-BAWM
`
`XJENZATWNW
`
`LOW Peak Hit
`Low Peak Hit
`Slicer Low
`Slicer High
`High Peck Hit LF
`High Peak Hit HF
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 2 of 20
`
`US 6,531,931 B1
`
`
`
`
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`

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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 3 of 20
`
`US 6,531,931 B1
`
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`
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`
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`U.S. Patent
`
`Mar. 11, 2003.
`
`Sheet 4 of 20
`
`US 6,531,931 B1
`
`
`
`
`
`FIG. 4
`
`260 Goin Control-p
`
`Gain Controln
`
`C301
`
`
`
`115-N
`
`Vod
`
`Output shared
`with AC/DC
`Gain Stage 125
`
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`U.S. Patent
`
`
`
`ppA
`
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 6 of 20
`
`US 6,531,931 B1
`
`
`
`ppA
`
`
`
`9 ºf)I, H.
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 7 of 20
`
`US 6,531,931 B1
`
`125
`
`N
`
`Vdd
`
`Output shared
`with second DC
`Gain Stage 115
`
`------------------------ -----
`RSum
`RSum
`17O \sump
`
`Vsumn- 171
`
`------------------------ --- - m ---
`
`mul-p
`212
`
`Q1
`
`4 13
`
`
`
`C1
`
`Q3
`
`Q2
`
`muln
`213
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`C2
`
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`
`Q4
`
`R4
`
`415
`
`R5
`
`4 16
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`R5 C4
`
`R7
`
`Q12
`
`R8 C5
`
`R9
`
`4 16
`
`R1O C6 R11
`
`Q8
`
`415
`
`Filter
`Select
`
`415
`
`Vbios
`4OO
`
`Q9
`
`V
`
`415
`
`Q10
`
`Vbids
`4OO
`
`FIG. 8
`
`V
`
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`U.S. Patent
`
`Mar. 11, 2003
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`Sheet 8 of 20
`
`US 6,531,931 B1
`
`135 N
`
`Wodd
`
`R500
`
`Vsump
`17O
`
`172
`
`eq Outp
`
`325
`
`VSumn
`171
`
`173
`
`Q504
`
`C500
`
`Q505
`
`
`
`
`
`Q502
`
`R503
`
`R505
`
`
`
`C501
`BOOST
`SELECT
`
`4OO
`
`Q503 H
`4OO
`
`FIG. 9
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 9 of 20
`
`US 6,531,931 B1
`
`
`
`1, Y
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 10 of 20
`
`US 6,531,931 B1
`
`
`
`1-10'
`
`FIG 1 1
`
`1-10
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 11 of 20
`
`US 6,531,931 B1
`
`15
`
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`
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`U.S. Patent
`
`Mar. 11, 2003
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`Sheet 12 of 20
`
`US 6,531,931 B1
`
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 13 of 20
`
`US 6,531,931 B1
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 14 of 20
`
`US 6,531,931 B1
`
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`|| || || ||
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 15 of 20
`
`US 6,531,931 B1
`
`Mode 2
`
`
`
`|_| \\ \ \ | NOEINT
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`FIG. 16
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`1-10
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 16 of 20
`
`US 6,531,931 B1
`
`Mode 2
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 17 of 20
`
`US 6,531,931 B1
`
`
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`|
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`
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`U.S. Patent
`
`Mar. 11, 2003
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`Sheet 18 of 20
`
`US 6,531,931 B1
`
`Mode 3
`
`35
`
`30
`
`|
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`
`FIG. 19
`
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 19 of 20
`
`US 6,531,931 B1
`
`
`
`| M.
`| CW1
`21 / 21||
`U-1 3.
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`U.S. Patent
`
`Mar. 11, 2003
`
`Sheet 20 of 20
`
`US 6,531,931 B1
`
`
`
`
`
`GAIN ALTENUATOR(ON LINE 411)
`GAIN MAX FACTOR
`
`
`
`GAIN MAX N db
`FILTER SELECT(ON LINE 415
`)
`DC GAIN
`| OF POLES/ZEROES IN FILTER
`ON LINE 409)
`BOOST SELECT (
`GAN BUFFER DC GAIN
`OF POLES/ZEROES IN GAIN BUFFER
`DRAWING FIG.
`LOW ALPHA
`DRAWING FIG.
`CABLE LENGTHS
`
`#
`
`1
`
`||
`
`0 ||
`
`0 ||
`
`1.51
`
`26
`
`3
`
`7 6
`
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`
`15
`
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`
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`
`2
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`
`1
`
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`2
`
`2
`
`1
`
`
`
`7 .6
`
`2
`
`
`
`
`
`V CONTROL STARTS AT
`
`MAX CABLE LENGTH IN METER
`
`
`
`70
`
`OW
`L
`
`MA
`X
`
`FI G. 2 1
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`US 6,531,931 B1
`
`1
`CIRCUIT AND METHOD FOR
`EQUALIZATION OF SIGNALS RECEIVED
`OVER A COMMUNICATION SYSTEM
`TRANSMISSION LINE
`
`CROSS-REFERENCES TO RELATED
`APPLICATIONS
`This application claims the benefit of U.S. Provisional
`Patent Application Ser. No. 60/087,605, filed Jun. 1, 1998.
`This application incorporates by reference the following
`U.S. patent applications that have been assigned to Enable
`Semiconductor, Inc., a California corporation: Ser. No.
`09/061937, filed Apr. 17, 1998, now U.S. Pat. No. 6,188,
`721, titled “System and Method for Adaptive Equalization
`of a Waveform Independent of Absolute Waveform Peak
`Value,” by Shirani et al.; and Ser. No. 09/062,342, now U.S.
`Pat. No. 6,148,025, filed Apr. 17, 1998, titled “System and
`Method for Compensating for Baseline Wander,’” by Shirani
`et al.
`
`15
`
`2
`Stage are magnified by the Second Stage, resulting in non
`optimal performance for a long cable. Also, each equaliza
`tion Stage consists of Several amplifierS SO coupling equal
`ization Stages in Series puts numerous amplifier Stages in
`Series. Each amplifier Stage loses. Some of the Signal
`bandwidth, particularly at high frequencies, which reduces
`the bandwidth of the entire linear channel, thereby reducing
`the Signal-to-noise ratio and the optimization for long cable
`equalization.
`The problem of amplifier bandwidth loSS is aggravated in
`amplifiers built using commercially available
`Complementary-Metal Oxide Semiconductor (CMOS) pro
`ceSSes due to the lower tranconductances and higher offsets
`of Metal Oxide Semiconductor (MOS) devices compared to
`bipolar devices. The gain bandwidth product of CMOS
`amplifier Structures is typically lower than that of bipolar
`amplifier Structures.
`A transmission cable typically has a frequency indepen
`dent (or DC) loss which is a linear function of the cable
`length. An equalization architecture should restore the DC
`component lost in the cable and output a signal having an
`amplitude close to that of the originally transmitted Signal.
`An adaptive equalization algorithm which is peak
`dependent demands that the equalized output signal peak be
`very close to that of the originally transmitted Signal before
`cable attenuation. Algorithms which are peak-independent
`are preferable but it remains important to restore as much as
`possible of the lost DC component to maximize the Signal
`to-noise ratio.
`Conventional adaptive equalization Systems also Suffer
`from a problem known as “baseline wander” which occurs
`when using differential signal transmission (i.e., MLT-3
`coding) over a twisted pair medium. MLT-3 coding Systems
`use three voltage levels (i.e., +1V, OV, and -1V) relative to
`a return voltage, referred to as the baseline or baseline
`reference which is typically Set to ground. In practice, the
`baseline does not remain at ground, but instead wanders up
`and down, which is referred to as “baseline wander.”
`What is needed is an equalization linear channel archi
`tecture which can be implemented in a commercially avail
`able CMOS process, which can provide optimum filter
`transfer characteristics over a wide range of cable lengths
`and which has sufficient bandwidth over a wide frequency
`range even when operating with a low (3 volt) Supply
`Voltage. This architecture should also restore most of the
`originally transmitted Signal amplitude in order to maximize
`the Signal-to-noise ratio.
`SUMMARY OF THE INVENTION
`The present invention provides equalization of Signals
`received over a communication System transmission line.
`The invention includes an equalization linear channel having
`an input biasing Stage, a linearity amplifier Stage, a first DC
`gain stage, a Second DC gain stage, a DC multiplier Stage,
`an AC/DC gain Stage, and a gain buffer Stage.
`The present invention is advantageous in that it provides
`an equalization linear channel which, Over an exceptionally
`wide range of cable lengths, can optimally equalize wave
`forms to provide equalized waveforms close in amplitude to
`the transmitted waveforms independent of DC cable loss,
`thus maintaining a good Signal-to-noise ratio. The circuit
`architecture comprises only a few amplifier Stages in Series
`and can be fabricated using well-known CMOS processes.
`The Stages are transconductance amplifiers which are simple
`in construction, leading to a high bandwidth in each Stage
`and improved immunity to both offset and power Supply
`
`25
`
`35
`
`40
`
`BACKGROUND OF THE INVENTION
`1. Technical Field
`The present invention relates generally to receivers con
`nected to transmission lines and more Specifically to a
`receiver circuit for compensating for Signal loSS caused by a
`transmission line.
`2. Prior Art
`Coaxial cables exhibit a skin effect which attenuates
`transmitted Signals based on their frequency. The amount of
`attenuation in decibels (db) increases in proportion to the
`Square root of the frequency f of the transmitted Signal.
`Additionally, the coaxial cable length and diameter, the
`ambient temperature, and other factors affect attenuation of
`Signals.
`Equalization amplifiers are used to compensate for Signal
`attenuation. Ideally, the equalization amplifier transfer func
`tion is the inverse of the transfer function representing the
`degree of Signal attenuation in the transmission line. This
`enables recovery of data Signal components (e.g., high
`frequency components) which have been attenuated by the
`transmission line.
`Conventional equalization circuits are described in U.S.
`Pat. No. 5,115,213 to T. Eguchi; U.S. Pat. No. 4,187,479 to
`K. Ishizuka; U.S. Pat. No. 4,689,805 to S. Pyhalammi et al.;
`U.S. Pat. No. 5,036.525 to H. Wong; U.S. Pat. No. 4,275,358
`to W. A. Winget; U.S. Pat. No. 4,378,535 to R. F. Chiu et al.;
`U.S. Pat. No. 4,768,205 to K. Nakayama; U.S. Pat. No.
`5,337,025 to G. D. Polhemus; U.S. Pat. No. 5,293,405 to J.
`E. Gersbach et al.; U.S. Pat. No. 4,459,698 to O. Yumoto et
`al.; U.S. Pat. No. 4,583,235 to J. Domer et al., U.S. Pat. No.
`4,243,956 to M. Lemoussu et al.; U.S. Pat. No. 4,961,057 to
`S. Ibukuro; and in Giacoletto, L. J. (editor), Electronics
`Designersi Handbook (2nd ed.), McGraw-Hill Book
`Company, New York, N.Y. (1977).
`A conventional equalization linear channel provides a
`Single filter having a fixed transfer function which provides
`optimal equalization for a limited range of cable lengths. A
`filter whose transfer function is optimized for shorter cables
`60
`will not be as optimal for longer cables. Similarly, a filter
`whose transfer function is optimized for long cables will not
`be as optimal for Shorter cables.
`Typically, an equalization linear channel, for Short cables
`can be coupled in Series with another short cable equaliza
`tion linear channel to provide equalization for a longer cable.
`However, equalization imperfections occurring in the first
`
`45
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`50
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`55
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`US 6,531,931 B1
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`3
`noise effects. The circuit architecture performs consistently
`over wide variations in temperature, power Supply, and
`process, and can be implemented readily with either 3 volt
`or 5 volt power supplies. The 3 volt power supply architec
`ture provides recognized power and System advantages over
`a 5 volt power Supply.
`These and other aspects of the invention will be appre
`ciated by those skilled in the art upon review of the detailed
`description, drawings and claims Set forth below.
`
`1O
`
`15
`
`4
`FIG. 19 shows the summation of the gains of the gain
`curves from FIG. 18 multiplied by 7.6 db for several values
`of the Vcontrol/Vcontrol (Max) ratio and the cable attenua
`tion curves for 80 meters and 140 meters (in mode 3);
`FIG. 20 shows the total gain through equalization linear
`channel for the maximum value of Vcontrol/Vcontrol
`(max)=1 for the two cases of boost select 409-0 and boost
`select 409=1; and
`FIG. 21 is a table of values for the 4 modes of operation.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 is a block diagram of an adaptive equalization
`system 150 used in a larger system 115. Within adaptive
`equalization system 150, equalization linear channel 310
`receives differential data signals on input lines 315 and 317
`and transmits an equalized differential data Signal on output
`lines 325 and 330. Digital logic control stage 405 receives
`a control input signal on line 422 from management port
`420, a delay line bias signal on line 382 from delay line
`calibration circuit 380, and High Peak Hit HF signal on line
`362, High Peak Hit LF signal on line 364, Slicer High signal
`on line 366, Slicer Low 368, Low Peak Hit signal on line
`370, and Low Peak Hit signal on line 372 from waveform
`analyzer stage 350. Digital logic control stage 405 provides
`input signals Boost Select on line 409, Gain Attenuator on
`line 411, Filter Select online 415, an input signal on line 408
`to equalizer DAC 410, an input signal on line 413 to Base
`Line Wander (BLW) DAC 417, and provides a High Peak
`Offset Control signal on line 340, High Peak Digital Control
`signal on line 342, Low Peak Digital Control signal on line
`344 and Low Peak Offset Control signal on line 346 to
`waveform analyzer stage 350.
`Equalization linear channel circuit 310 selectively ampli
`fies the input signal 105 received over and attenuated by
`transmission line 110 from signal source 102. Transmission
`line 110 ranges in length typically from a few meters to over
`140 meters. A signal propagating through transmission line
`110 experiences attenuation or a line loSS which varies in
`proportion to the Square root of the frequency (f) and the
`length (L) of the transmission line, as expressed by equation
`(1):
`
`line-loss=exp-(Af-Bf)/LH-line-lossDC(L)
`(1)
`where A and B are constants and line-lossDC(L) is the DC
`loSS of the Signal propagating through transmission line 110.
`Line-lossDC(L) is Substantially due to resistance in trans
`mission line 110 and increases with L. Equation (1) can be
`approximated by equation (2):
`line-loss=exp-AfL+line-lossDC(L)
`(2)
`When connected to a transmission line of a known length
`and having a particular line-loSS characteristic, equalization
`linear channel 310 generates and applies a gain Versus
`frequency curve which compensates for the DC and fre
`quency dependent attenuation experienced by Signals trav
`eling through the transmission line. Equalization linear
`channel 310 can generate a plurality of gain curves which
`can mirror the line-loSS characteristics of many different
`transmission lines to equalize input Signal 105. The shape of
`these gain curves is determined by various transfer function
`characteristics within equalization linear channel 310. For
`Shorter cables (i.e., less than 80 meters), equalization linear
`channel 310 preferably employs a three-pole/Zero transfer
`function filter. For longer cables (i.e., 80 to 140 meters)
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of an adaptive equalization
`System;
`FIG. 2 is a block diagram of the equalization linear
`channel of FIG. 1;
`FIG. 3 shows a preferred circuit schematic of input
`biasing Stage of FIG. 2;
`FIG. 4 shows a preferred circuit schematic of a linearizer
`amplifier of FIG. 2;
`FIG. 5 shows a preferred circuit schematic of DC multi
`plier stage of FIG. 2;
`FIG. 6 shows a preferred circuit schematic of first DC
`gain Stage of FIG. 2;
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`FIG. 7 shows a preferred circuit schematic of second DC
`gain Stage of FIG. 2;
`FIG. 8 shows a preferred circuit schematic of AC/DC gain
`stage of FIG. 2;
`FIG. 9 shows a preferred circuit schematic of again buffer
`of FIG. 2;
`FIG. 10 is a graph showing contributions to the gain for
`a short cable;
`FIG. 11 shows the Summed gain from FIG. 10, the
`Summed gain multiplied by a constant factor and the inverse
`of cable attenuation verSuS frequency for a category five
`twisted pair cable 80 meters long;
`FIG. 12 shows contributions to the gain for a long cable;
`FIG. 13 shows the Summed gain from FIG. 12, the
`Summed gain multiplied by a frequency independent con
`Stant factor and the inverse of cable attenuation verSuS
`frequency for a category five twisted pair cable 140 meters
`long;
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`FIG. 14 shows the gain through the first and second DC
`gain Stages and the gain through the DC multiplier Stage and
`the AC/DC gain stage as a function of the ratio Vcontrol/
`Vcontrol(Max) as this ratio goes from 0.1 to 1.0 (in mode 1).
`FIG. 15 shows the summation of the gains of the gain
`curves from FIG. 14 multiplied by 7.6 db for several values
`of the Vcontrol/Vcontrol (Max) ratio and the cable attenua
`tion curves for cable lengths of 9 meters and 75 meters (in
`mode 1);
`FIG. 16 shows the gain through the first and second DC
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`gain Stages and the gain through the DC multiplier Stage and
`the AC/DC gain stage as a function of the Vcontrol/Vcontrol
`(Max) ratio as it goes from 0.1 to 1.0 (in mode 2);
`FIG. 17 shows a plot the summation of the gains of the
`gain curves from FIG. 16 multiplied by 7.6 db for several
`values of the Vcontrol/Vcontrol(Max) ratio and the cable
`attenuation curves for cable lengths of 10 meters and 85
`meters (in mode 2);
`FIG. 18 shows the gain through first and second DC gain
`Stages and the gain through the DC multiplier Stage and the
`AC/DC gain stage as a function of the Vcontrol/Vcontrol
`(Max) ratio as it goes from 0.4 to 1.0 (in mode 3);
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`equalization linear channel 310 preferably employs a two
`pole/Zero transfer function filter. An equalized output signal
`335 is then presented on an output line 325 of the equal
`ization linear channel circuit 310.
`For cables longer than 140 meters, equalization linear
`channel 310 employs the above-mentioned two-pole filter
`and a fixed AC boost filter activated to further boost the
`higher frequency components of the input waveform which
`are heavily attenuated at Such long cable lengths.
`FIG. 2 is a block diagram of equalization linear channel
`310 in accordance with the present invention for equalizing
`signals received through transmission line 110 (FIG. 1).
`Equalization linear channel 310 includes input biasing Stage
`132, linearity amplifier stage 148, first DC gain stage 130,
`second DC gain stage 115, DC multiplier stage 120, AC/DC
`gain Stage 125, and gain buffer Stage 135. Input biasing Stage
`132 receive S equalization gain control Signals
`GainControl p and GainControl n on lines 260 and 261
`respectively from linearity amplifier Stage 148, and provides
`Signals data p on line 200, data in on line 201, data p
`shifted on line 202 and data in shifted on line 203 to first
`DC gain stage 130 and to DC multiplier stage 120. First DC
`gain Stage 130 provides input signals dc p on line 210 and
`dc n on line 211 to second DC gain stage 115. DC multi
`plier Stage 120 provides input signals mul p on line 212 and
`mul n on line 213 to AC/DC gain stage 125. The second
`DC gain stage 115 and the AC/DC gain stage 125 output
`signals Vsump on line 170 and VSumn on line 171 are the
`input signals to gain buffer stage 135. Gain buffer stage 135
`outputs the equalization signals eqoutp on line 330 and
`eqoutn on line 325 which are coupled to waveform analyzer
`stage 350 of FIG. 1.
`Input Biasing Stage 132
`FIG. 3 is a Schematic of preferred input biasing Stage 132,
`which receives the input differential signals. In on line 315
`and Inb on line 317. It also receives two analog signals iblwn
`and iblwp on control bus 419 from baseline wander (BLW)
`digital-to-analog converter (DAC) 410 (FIG. 1). The two
`Signals iblwp and iblwn are Zero current when there is no
`“baseline wander” event. When a baseline wander event is
`detected, one signal on the analog bus will be either a
`positive or a negative current depending on the magnitude
`and direction of the baseline wander event. The other signal
`will be a current equal in amplitude but opposite in polarity
`to that of the first signal.
`Signals GainControl p 260 and GainControl n 261 are
`used to Select the gain curves to be applied to input wave
`form 320. Input biasing stage 132 receives on line 400 a
`band gap-derived biasing Voltage Signal Vbias to establish
`the primary bias current of the input biasing Stage. An Ibias
`signal on line 401 is a band gap-derived current of about 150
`tla which is Sourced acroSS R112, providing a process and
`temperature independent Voltage at the gates of transistors
`Q105 and Q107. Since the gate-to-source voltage drops of
`transistors Q105 and Q107 are both process and temperature
`dependent, the current through Q105, Q107, R109 and R110
`will exhibit both a process and temperature dependency. For
`fast process corners, the currents through Q105 and Q107
`will be higher than for slow process corners. The amount of
`current through Q105 and Q107 and the amount of process
`and temperature skew to this current will be determined by
`the w/l ratios of O105 and O107 and the values of R109 and
`R110. For fast corner circuits produced by an IC fabrication
`process the common mode of the data In on line 315 and Inb
`on line 317 relative to ground is reduced in voltage, and for
`Slow corner circuits produced by an IC fabrication proceSS
`the common mode of the data In on line 315 and Inb on line
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`317 relative to ground is increased. This biasing is important
`in ensuring that the next amplifiers in first DC gain Stage 130
`and in DC multiplier stage 120 (FIG. 1) will always operate
`as linear amplifiers despite variations in fabrication process
`and operating temperature.
`Input biasing Stage 132 outputs two pairs of differential
`signals. The first pair is Data p 200 and Data in 201 and the
`second pair is Data p shifted 202 and Data in shifted
`203. The two differential signal pairs are equal in differential
`peak-to-peak amplitude. With the common mode Voltage of
`Data p and Data in defined as VCM(data), the common
`mode Voltage of Data p shifted and Data in shifted
`defined as VCM(data shifted); and the voltage difference
`between GainControl p and GainContol n define as
`Vcontrol, there is a relationship:
`VCM(data)-VCM(data shifted)=(Vcontrol/Vcontrol (Max))* 0.4
`Volts
`(3)
`where Vcontrol(MAX) is the maximum excursion of Vcon
`trol.
`FIG. 3 shows input biasing stage 132 in a preferred
`embodiment in which transistors Q104 and Q105 set the
`biasing current at approximately 1.5 ma to establish the
`common mode voltage. In on line 315 equal to (VDD-1.5
`ma*(R101 ohms)). Transistor Q104 conducts a fixed current
`of approximately 1.3 ma and transistor Q105 conducts a
`process and temperature dependent current. Transistors
`Q106 and Q107 set the biasing current at approximately 1.5
`ma to establish the common mode voltage Inb on line 317
`equal to (VDD-1.5 ma(R103 ohms)). Transistor Q106
`conducts a fixed current of approximately 1.3 ma and
`transistor Q107 conducts a proceSS and temperature depen
`dent current. Using bias currents which are the Summation
`of a fixed current and a temperature and process dependent
`current, enables Setting the common mode Voltage of the
`differential signals In and Inb optimally for any given
`process and temperature. If no baseline wander event is
`present, the currents through and the Voltage drops acroSS
`resistors R102 and R104 are equal. If a baseline wander
`event occurs, a time varying current of programmable polar
`ity and of amplitude proportional to the magnitude of the
`baseline wander event will be sourced from iblwp line 266
`and a time varying current of equal amplitude but opposite
`polarity will be sourced from iblwn line 267. Since these
`currents are equal in amplitude but opposite in polarity,
`differential Voltage Swings which are equal in amplitude but
`opposite in polarity are developed acroSS resistors R102 and
`R104. Through this process, signals on lines 266 and 267
`can maintain the same common mode Voltage even as the
`baseline wander event generates a DC shift of the common
`mode voltage at In line 315 versus the common mode
`voltage at Inb line 317. A differential voltage Vcontrol equal
`to GainControl p-GainControl n is applied acroSS the
`differential transistor pair Q100 and Q101. This differential
`voltage will lead to a differential current through Q100 and
`Q101, which will lead to a differential voltage drop across
`R105 and R106 and thus a differential voltage (Data p
`Data p shifted) between Data p and Data p shifted.
`The differential Voltage Vcontrol applied acroSS transistors
`Q102 and Q103 will lead to a differential current through
`Q102 and Q103 which will lead to a differential voltage drop
`across R107 and R108 and thus a differential voltage (Data
`n-Data in shifted) between Data in and Data in shifted.
`The common mode voltage VCM(data) will be higher than
`the common mode voltage VCM(data shifted) by the
`amount of equation (3)
`VCM(data)-VCM(data shifted)=(Vcontrol/Vcontrol (Max))* 0.4
`Volts
`(3)
`This linearly varying dependency of the quantity VCM
`(data)-VCM(data shifted) with Vcontrol is used to control
`the DC multiplier stage 120 (FIG. 1).
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`Linearity Amplifier 148
`FIG. 4 is a schematic of a preferred embodiment of
`linearity amplifier 148, which receives the differential cur
`rent information represented by Signals icontrol p and
`icontol n on two bit bus 412 from equalizer DAC 410 (FIG.
`1), and outputs a linear Voltage differential signal Vcontrol
`equal to GainControl p-GainControl n. AS the differential
`current from DAC 410 goes from 0 ma to I(max), Vcontrol
`goes from 0 volts to Vcontrol(MAX).
`The Sum of icontrol in and icontrol p is a constant
`current set by the equalizer DAC 410 (FIG. 1). When
`icontrol p and icontrol n are equal, the currents through
`Q300 and Q301 are equal and thus the voltages
`GainControl p and GainControl n are equal. When
`icontrol n is close to Zero then icontrol p is equal to its
`maximum value. The differential voltage Vcontrol is at its
`maximum value Vcontrol(max). In general Vcontrol=K
`(icontrol p-icontrol n). K is a process and temperature
`dependent coefficient. The approximate linearity and maxi
`mum voltage excursion of the circuit is determined by the
`sum of icontrol p and icontrol in and the w/l ratios of Q300
`and Q301, which are equal. The function of Q302 is to offset
`GainControl p and GainControl n So as to assure the
`linearity of the Input bias stage. R301, C302 and R302,
`C301 and C300 form a low pass filter, so that high frequency
`noise in icontrol p and icontrol n does not get through to
`the input bias Stage.
`DC Multiplier Stage 120
`FIG. 5 is a schematic of a preferred embodiment of DC
`multiplier stage 120. DC multiplier stage 120, linearity
`amplifier 148 and input biasing Stage 132 together perform
`an analog multiplication function on the input data Signal In
`on line 315 and signal Inb on line 317 (FIG. 2). Stage 120
`receives two pairs of differential input Signals: Data p on
`line 200 and Data in on line 201, and Data p shifted on
`line 202 and Data in shifted on line 203; and transmits one
`pair of differential output signals: mul p on line 212 and
`mul n on line 213. Stage 120 receives signal Gain Attenu
`ator on line 411 and receives signal Vbias on line 400 which
`provides a band gap derived biasing Voltage to establish the
`primary bias current of stage 120. If voltage Vin diff is
`equal to Data p-Data n, Voltage Vout diff is equal to
`mulp-muln, VCM(data) is the common mode voltage of the
`differential pair Data p and Data n, and VCM(data
`shifted) is the common mode Voltage of Data p shifted
`and Data in Shifted, then
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`Vout diff=1.4*(Vin diff(VCM(data)-VCM(data shifted))f0.4
`volts
`
`(5)
`The quantity VCM(data)-VCM(data shifted) is related
`to the output of the linearity amplifier 148, Vcontrol=
`(GainControl p-GainControl n), by the equation
`
`VCM(diff)=(Vcontrol/Vcontrol (Max))*0.4 volts
`(6)
`where VCM(diff)=VCM(data)-VCM(data shifted). Thus
`Vout diff=(1.4* Vin diff Vcontrol)/Vcontrol (Max)
`(7)
`which shows that Vout diff is proportional to the product of
`Vin diff times Vcontrol and varies from a minimum value
`of Vout diff=0 when Vcontrol=0 to a maximum value of
`Vout diff=1.4* Vin diff when Vcontrol=Vcontrol (Max). In
`decibels, the gain is 20*Log(1.4*(Vcontrol/Vcontrol
`(Max))).
`DC multiplier circuit 120 is implemented as a cross
`coupled transconductance amplifier. When VCM(data) is
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`equal to VCM(data shifted) the currents through transistors
`Q401 and Q403 are equal and the currents through transis
`tors Q404 and Q402 are equal. Thus, due to the cross
`coupled arrangement of these transistors, no differential
`current flows through resistors R402 and R403 and thus no
`differential Voltage builds up between mul p and mul n.
`When VCM(data) is higher than VCM(data shifted) by the
`maximum of 0.4 Volts, t