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`Ronald A. Oliver etal.
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`conformance and not considered. Include copy of this form with next communication to applicant(s).
`HAIP\Clients\Impinj, Inc\190131\190131US PTO-1449.doc
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 1
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 1
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`

`

`a
`Dacrener
`worm Grae
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark (Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`WWW ISplO,g0V
`
` APPLICATION NO.
`
`12/042,117
`
`FILING DATE
`
`03/04/2008
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`Ronald A Oliver
`
`5088.0181USU1/IMPJ-0290
`
`2746
`
`Turk IP Law, LLC [eee|
`
`1770 Highlands View
`OBINIYI, PAUL
`Smyrna, GA 30082 2612
`
`EXAMINER
`
`as
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`04/12/2011
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period forreply, if any,is set in the attached communication,
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`
`docketing @turkiplaw.com
`carlt@turkiplaw.com
`kathyk @turkiplaw.com
`
`PTOL-90A (Rev. 04/07)
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 2
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`

`

`
`Application No.
`Applicant(s)
`
`Office Action Summary
`
`12/042,117
`Exaniiner
`
`OLIVER ET AL.
`Art Unit
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`- Extensions of time may be available under the provisions of 37 CFR 1.136(a)}.
`In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C, § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s)filed on
`2a)(_] This action is FINAL.
`2b) This action is non-final.
`3)L Sincethis application is in condition for allowance exceptfor formal matters, prosecution as to the merits is
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`4)x] Claim(s) 1-25 is/are pending in the application.
`4a) Of the above claim(s)
`is/are withdrawn from consideration.
`5)L] Claim(s)
`is/are allowed.
`6)] Claim(s) 1-25 is/are rejected.
`7)L) Claimis)
`is/are objectedto.
`8)L Claim(s)__ are subjectto restriction and/or election requirement.
`
`Application Papers
`
`9)C] The specification is objected to by the Examiner.
`10) The drawing(s)filed on
`is/are: a)_] accepted or b)[[] objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`11) The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
`
`Priority under 35 U.S.C. § 119
`
`12) Acknowledgmentis madeof a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or(f).
`a)DAll
`bj) Some * c)[] Noneof:
`1.0] Certified copies of the priority documents have beenreceived.
`2..] Certified copies of the priority documents have been received in Application No.
`3.0] Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`“See the attached detailed Office action for a list of the certified copies not received. Attachment(s)
`
`1) i] Notice of References Cited (PTO-892)
`2) _] Notice of Draftsperson’s Patent Drawing Review (PTO-948)
`3) i Information Disclosure Staterment(s) (PTO/SB/08)
`Paper No(s)/Mail Date
`.
`US. Patent and Trademark Office
`PTOL-326 (Rev, 08-06)
`
`4) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date. __
`5) LJ Notice of Informal Patent Application
`6) L] other:
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20110307
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 2
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`DETAILED ACTION
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousnessrejections setforth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 ofthis title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the mannerin which the invention was made.
`
`Claims 1, 2, 12, 13, 14, 15, 16, 17, 18, & 19 are rejected under 35 U.S.C. 103(a) as
`
`being unpatentable over Smith et al (2005/0162145), (herein after, Smith), in view of
`
`Watanabeetal (2004/0061544), (herein after, Watanabe).
`
`As to claim 1, Smith teaches powerrectifier for a Radio Frequency Identification
`
`tag circuit, comprising[0031 shows a RF-DC converter (104/106) that rectifies the RF
`
`signal received at an input node (302), 0008 shows a RF data communication device]: a
`
`first antenna input node configured to receiveafirst phase of a wirelessly received
`
`alternating RF signal[0023 teaches RFID chip having thefirst pad (130) operatively
`
`connectedto the first antenna (100) signal (RF 1). 0034 further teaches positive and
`
`negative RF cycles]; a second antenna input node configured to receive a second
`
`phase ofthe wirelessly received alternating RF signal, and which is substantially
`
`opposite to the first phase;[0023 teaches RFID chip having thefirst pad (130) anda
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`Application/Control Number: 12/042,117
`Art Unit: 2612
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`Page 3
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`second pad (132) operatively connected to the first antenna (100) and a second
`
`antenna (102) for receiving RF signal RF1 and RF2 respectively]a plurality of serially
`
`coupled stages, at least one of the stages[0032 teaches a multiple stages 300(1),
`
`300(2), .....300(N-1)] including a first synchronous element [including synchronous
`
`element such astransistor, see Fig.4] withafirst beginning coupled to receive the
`
`second phase andafirst ending,[Fig. 4 shows the end of (406) connectedwith the
`
`beginning of (408) and the output of 300(1) connected to the input of 300(2) | the first
`
`synchronous elementincluding: a first transistor having an input terminalat the first
`
`beginning, an output terminal, andafirst gate coupled to receivethe first phase;[ Fig. 4
`
`shows a MOStransistor (406) having an input terminal, an output terminal, and a gate
`
`couples to the RF input] and a secondtransistor having an input terminal, an output
`
`terminal at the first ending, and a second gate coupled to receive the second phase,
`
`[Fig. 4 show a MOStransistor (408) having an output terminal connected to the input
`
`terminalof thefirst transistor]in which the input terminal of the second transistor is
`
`connected to the output terminalof thefirst transistor at a first intermediate node [0029
`
`showsa transistor (110) configured with a gate connected to the CRTL node, a drain
`
`tied to the RF1 node, and a source connected to the VSS node, while the n-channel
`
`MOStransistor 112 is configured with a gate connected to the CTRL node,a drain tied
`
`to the RF2 node, and a source connected to the VSS node. 0029 further showsthat
`
`whenasserted, the n-channel MOStransistors 110 and 112 will attenuate the incoming
`
`RF signals RF1 and RF2,] so asto formafirst charge-accumulating path between the
`
`beginning and the ending, and there is no charge-accumulating path between the
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`Application/Control Number: 12/042,117
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`beginning and the ending otherthan thefirst path. [0034 teaches that charge
`
`accumulated on the central terminal (316) during positive circle and also accumulates
`
`on terminal (316) from negative cycle.]
`
`Smith does not explicitly teach alternating RF signal
`
`Watanabeteachesalternating RF signal [0056 further teaches that LO signal and
`
`an inverted LO signal opposite in phase to the LO signal are inputted to the DBM circuit
`
`1. 0060 further teachesa first transistor (15); a second transistor having a base
`
`connectedto the baseofthefirst transistor (15); and an RF signal input port (26)
`
`connected to each of the respective basesof the first and second transistors (15) and
`
`(16).]
`
`It would have been obviousto oneof ordinary skill in the art at the time of
`
`invention to modify Smith with Watanabeto incorporate first and second transistor as
`
`claimed for the purpose of creating an efficient RF signal communication.
`
`Asto claim 2, Smith and Watanabeteachin which at least two of the stages are
`
`made substantially identically. [0032 teaches multiple stages, with each stage (300)
`
`including three diodes (306-310) and two capacitors (312) and (314).]
`
`As to claim 12, Smith teaches in which the stage that includesthefirst
`
`synchronous elementfurther includes a second synchronous element, [Fig. 4 shows
`
`first and second transistors.] the second synchronous element having a second
`
`beginning and a second ending [Fig 4. shows a second transistor having a second
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`Page 5
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`beginning and a second end]including: a first transistor having an input terminal at the
`
`second beginning, an output terminal,
`
`in which the input terminal of the second
`
`transistor is connected to the output terminalof the first transistor at a second
`
`intermediate node [0029 showsa transistor (110) configured with a gate connected to
`
`the CRTL node,a drain tied to the RF1 node, and a source connected to the VSS node,
`
`while the n-channel MOStransistor 112 is configured with a gate connected to the
`
`CTRL node, a drain tied to the RF2 node, and a source connected to the VSS node.
`
`0029 further shows that when asserted, the n-channel MOStransistors 110 and 112 will
`
`attenuate the incoming RF signals RF1 and RF2,] so as to form a second charge-
`
`accumulating path between the second beginning and the second ending, and thereis
`
`no charge-accumulating path between the second beginning and the second ending
`
`other than the second path.[0034 teaches that charge accumulated on the central
`
`terminal (316) during positive circle and also accumulates on terminal (316) from
`
`negative cycle.]
`
`Smith does not explicit show that a first gate coupled to receive the second
`
`phase and a secondtransistor having an input terminal, an output terminal at the
`
`second ending, and a second gate coupled to receive thefirst phase
`
`Watanabe showsfirst gate coupled to receive the second phase and a second
`
`transistor having an input terminal, an output terminal at the second ending, anda
`
`second gate coupled to receive the first phase[0022 teach an RF signal input port for
`
`receiving an RF signal; a first transistor having a control portion for receiving the RF
`
`signal inputted to the RF signal input port; a second transistor having a control portion
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`Mylan Exhibit 1088
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`Application/Control Number: 12/042,117
`Art Unit: 2612
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`Page 6
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`for receiving the inverted RF signal to output an amplified inverted RF signalin
`
`responseto the inverted RF signal. 0029 further teach a first and secondtransistors a
`
`gate, a source, and a drain, 0029 further showsthat thefirst transistor outouts the RF
`
`signal from the drain thereof in responseto the RF signal inputted to the gate thereof,
`
`and the secondtransistor outputs the inverted RF signal. 0056 further teaches that LO
`
`signal and an inverted LO signal opposite in phase to the LO signal are inputted to the
`
`DBMcircuit 1. 0060 further teachesa first transistor (15); a second transistor having a
`
`base connectedto the baseofthe first transistor (15); and an RF signal input port (26)
`
`connected to each of the respective basesof the first and second transistors (15) and
`
`(16). 0063 further teachestransistors (13) and (14) having respective emitters
`
`connected to each other, a first LO signal input port (27), a second LO signal input port
`
`(28), a first IF signal output port (29), and a second IF signal output port (30).]
`
`It would have been obviousto one of ordinary skill in the art at the time of
`
`invention to modify Smith with Watanabeto incorporate first and second transistor as
`
`claimed for the purpose of creating an efficient RF signal communication.
`
`As to claim 13, Smith and Watanabeteachin which the stage begins at input
`
`terminal of thefirst transistor of the first synchronous element and endsat output
`
`terminal of the second transistor of the second synchronous element. [Smith (Fig. 4)
`
`showsa stage beginning with the input of transistor (406) and ending at VOUT of
`
`transistor (304)]
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 7
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`As to claim 14, Smith and Watanabe teach in which the gate ofthe first transistor
`
`is coupled to the output terminal of one of the first and the secondtransistor to receive a
`
`DC bias voltage in addition to being coupled to receive the second phase.[Smith (Fig.
`
`9) teaches the gate of transistor (110) and transistor (112) are coupled together and the
`
`second transistor receives RF input.0045 further shows diode (708) is forward biased by
`
`the charge on the terminal]
`
`As to claims 15 & 18, Smith and Watanabeteach in which an amountof the DC
`
`bias voltage is a function of amplitude of the RF signal. [0034 teaches RF signal applied
`
`to each stage (300), 0034 further teach that the diode (308) is forward biased by the
`
`charge on the terminal. 0038 further teach an amplitude modulation (AM) circuit, with
`
`the incoming RF signal RF1 and RF2 entering the AM circuit, and being demodulated
`
`into signal EOUT]
`
`As to claims 16 & 19, Smith and Watanabe teach in which the amountof the DC
`
`bias voltage is controlled such that an amount of an average current through thefirst
`
`transistor is substantially maximized. [0031 teaches that the RF signal received at an
`
`input node (302), increase the voltage amplitude and generates the output DC Voltage
`
`VOUT]
`
`As to claim 17, Smith and Watanabeteach in which the gate of the second
`
`transistor is coupled to the input terminal of one ofthe first and the secondtransistor to
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`Application/Control Number: 12/042,117
`Art Unit: 2612
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`Page 8
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`receive a DC bias voltage in addition to being coupled to receive the first phase. [0022
`
`teach an RF signal input port for receiving an RF signal; a first transistor having a
`
`control portion for receiving the RF signal inputted to the RF signal input port; a second
`
`transistor having a control portion for receiving the inverted RF signal to output an
`
`amplified inverted RF signal in response to the inverted RF signal. 0029 further teach a
`
`first and second transistors a gate, a source, and a drain, 0029 further showsthat the
`
`first transistor outputs the RF signal from the drain thereof in response to the RF signal
`
`inputted to the gate thereof, and the secondtransistor outputs the inverted RF signal.
`
`0056 further teaches that LO signal and an inverted LO signal opposite in phase to the
`
`LO signal are inputted to the DBM circuit 1. 0060 further teachesa first transistor (15); a
`
`secondtransistor having a base connectedto the baseofthefirst transistor (15); and an
`
`RF signal input port (26) connected to each of the respective basesofthe first and
`
`second transistors (15) and (16). 0063 further teaches transistors (13) and (14) having
`
`respective emitters connected to each other, a first LO signal input port (27), a second
`
`LO signal input port (28), a first IF signal output port (29), and a second IF signal output
`
`port (30).]
`
`Claims 3, 4, 5, 6, 7, & 8 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Smith et al (2005/0162145), (herein after, Smith), in view of Watanabeet al
`
`(2004/0061544), (herein after, Watanabe) and further in view of Joardar (5,936, 454),
`
`(herein after, Joardar).
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
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`Mylan Exhibit 1088
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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 9
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`As to claim 3, Smith and Watanabe teach in which the gate ofthe first transistor
`
`is coupled to receive thefirst phase. [Smith (Fig 4) show the gate of the first
`
`transistor
`
`connected to (320) and (VSS).
`
`Smith and Watanabe do not explicitly teach which the gate of thefirst transistoris
`
`coupled to the output terminal of one ofthe first and the secondtransistor to receive a
`
`DC biasvoltage,
`
`Joardar teaches the gateof thefirst transistor is coupled to the output terminal of
`
`one of the first and the secondtransistor to receive a DC bias voltage, [Fig. 1. shows
`
`the gate ofthe first transistor (10) coupled to the output of transistor (46).
`
`It would have been obviousto one of ordinary skill in the art at the time of
`
`invention to modify Smith and Watanabe with Joardarto incorporatefirst transistor is
`
`coupled to the output terminal of one ofthe first and the second transistor as claimed for
`
`the purpose of creating anefficient gate biasing
`
`As to claim 4 & 7, Smith and Watanabe with Joardar teach in which an amountof
`
`the DC bias voltage is a function of amplitude of the RF signal. [0034 teaches RF signal
`
`applied to each stage (300), 0034 further teach that the diode (308) is forward biased
`
`by the charge on the terminal. 0038 further teach an amplitude modulation (AM) circuit,
`
`with the incoming RF signal RF1 and RF2 entering the AM circuit, and being
`
`demodulated into signal EOUT]
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 11
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`Mylan Exhibit 1088
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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 10
`
`As to claim 5, Smith and Watanabe with Joardar teach in which the amount of
`
`the DC bias voltage is controlled such that an amount of an average current through the
`
`first transistor is substantially maximized for a given RF input power. [0031 teaches that
`
`the RF signal received at an input node (302), increase the voltage amplitude and
`
`generatesthe output DC Voltage VOUT.]
`
`Asto claim 6, Smith and Watanabe with Joardar teach in which the gate of the
`
`secondtransistor is coupled to the input terminal of one ofthe first and the second
`
`transistor to receive a DC bias voltage, in addition to being coupled to receive the
`
`second phase. [Smith teaches a gate of transistor (showsthat the gate of transistor
`
`(408) is coupled to RF (302) (Fig. 4). Joardar showsthat the gate of (46) is couple to the
`
`input of transistor (40).
`
`As to claim 8, Smith and Watanabe with Joardarin which the amountof the DC
`
`bias voltage is controlled such that an amount of an average current through thefirst
`
`transistor is substantially maximized.[ Smith teach that the RF signal RF1 and RF2is
`
`converted into a DC voltage VDD and the Voltage VDD powered the stat machine
`
`controlling the logic signal. 0033 further showsthat the low threshold transistors (406)
`
`and (408) makethe chip of generating sufficient power with low voltage RF inputs.
`
`0037 further shows that when high speed drive modeis required, the transistor (504)
`
`will be simultaneously turned on in respo2nseto the asserted signal so as to provide
`
`higher drive capability]
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 12
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`Mylan Exhibit 1088
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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 11
`
`Claim 9, 10 & 23 are rejected under 35 U.S.C. 103(a) as being unpatentable over Smith
`
`et al (2005/0162145), (herein after, Smith), in view of Watanabeetal (2004/0061544),
`
`(herein after, Watanabe), and further in view of Oka, (20070210776), (herein after,
`
`Oka).
`
`(808).
`
`As to claims 9, 10, & 23, Smith and Watanabe teach MOStransistor (806) and
`
`Smith and Watanabe do not explicitly teach in which thefirst transistor and the
`
`second transistor are a PMOS and a NMOSrespectively.
`
`Oka teachesin whichthefirst transistor and the second transistor are a PMOS
`
`and a NMOSrespectively. [0004 teach a synchronous rectifier circuit that is made up of
`
`PMOStransistor (M1) and NMOStransistor (M2).]
`
`It would have been obviousto one of ordinary skill in the art at the time of
`
`invention to modify Smith and Watanabe with Okato incorporate PMOS and a NMOS
`
`as claimed for the purpose of creating an efficient rectifying unit.
`
`Claim 11 is rejected under 35 U.S.C. 103(a) as being unpatentable over Smith etal
`
`(2005/0162145), (herein after, Smith), in view of Watanabe et al (2004/0061544),
`
`(herein after, Watanabe) and further in view of Yu (6,320,230), (herein after, Yu)
`
`As to claim 11, Smith and Watanabe teach MOStransistor (806) and (808).
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 13
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 13
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`

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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 12
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`Smith and Watanabe do not explicitly teach in which thefirst transistor is the
`
`NMOS and the second transistor is PMOS.
`
`Yu teach in which the first transistor is the NMOS and the secondtransistoris
`
`PMOS.[Yu teach NMOStransistor and PMOStransistor, (col 3, In 35)]
`
`It would have been obviousto one of ordinary skill in the art at the time of
`
`invention to modify Smith and Watanabe with Yu to incorporate NMOStransistor and
`
`PMOStransistor as claimed for the purpose of creating anefficient rectifying unit.
`
`Claim 20 is rejected under 35 U.S.C. 103(a) as being unpatentable over Smith et al
`
`(2005/0162145), (herein after, Smith), in view of Watanabe et al (2004/0061544),
`
`(herein after, Watanabe), and further in view of Hokenmaier, (2008/02672558), (herein
`
`after, Hokenmaier).
`
`As to claim 20, Smith and Watanabeteach the elements of claim 12, above.
`
`Smith and Watanabe do not teach in which the first and second intermediate
`
`nodesarefloating.
`
`Hohenmaier teachesin which the first and second intermediate nodes are
`
`floating. [0029 teaches that second value (e.g., a reference voltage V.sub.REF) to the
`
`intermediate node, and output signals from all of the memory chips are floating, 0029
`
`further show that second value has an opposite logical value from thefirst value (i.e.,
`
`whenthefirst value is logical "high," the second value is logical "low").]
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 14
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 14
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`

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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 13
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`It would have been obviousto one of ordinary skill in the art at the time of
`
`invention to modify Smith and Watanabe with Hohenmaierto incorporatefirst and
`
`second intermediate nodes are floating as claimed for the purpose of creating an
`
`efficient floating voltage of chip.
`
`Claim 21 is rejected under 35 U.S.C. 103(a) as being unpatentable over Smith etal
`
`(2005/0162145), (herein after, Smith), in view of Watanabeet al (2004/0061544),
`
`(herein after, Watanabe), and further in view of Conn etal (7,046,071), (herein after,
`
`Conn)
`
`As to claim 21, Smith and Watanabeteach the elementof claim 12, above.
`
`Smith and Watanabe do not teach in which the first and second intermediate
`
`nodes are coupled together, and are floating together.
`
`Conn teachesin whichthefirst and second intermediate nodes are coupled
`
`together, and arefloating together. [Con teaches that common centerplate is allowed to
`
`float, and the signal transition on the data is coupled from thefirst capacitor (127),
`
`through the common centerplate, and through the second capacitor 128, and onto the
`
`intermediate node (col. 4, In 56)]
`
`It would have been obviousto one of ordinary skill in the art at the time of
`
`invention to modify Smith and Watanabewith Conn to first and second intermediate
`
`nodes are coupled together as claimed for the purposeof creating an efficient data
`
`transmission.
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 15
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 15
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`

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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 14
`
`Claim 22 is rejected under 35 U.S.C. 103(a) as being unpatentable over Smith et al
`
`(2005/0162145), (herein after, Smith), in view of Watanabe et al (2004/0061544),
`
`(herein after, Watanabe), and furtherin view of Sali et al (5,659,502), (herein after, Sali).
`
`As to claim 22, Smith and Watanabeteach the element of claim 12, above.
`
`Smith and Watanabe do not teach in which the first and second intermediate
`
`nodes are coupled together, and are coupled to ground.
`
`Sali teach in which the first and second intermediate nodes are coupled together,
`
`and are coupled to ground. [Sali teaches that the voltage V(5) on node (5) is kept to
`
`ground (node5is a virtual ground). The voltage variation on node (11) necessary to
`
`bring V(5) to ground (col 6, In 5-10), (coupling node to a ground terminalor to a fixed
`
`voltage supply, a second bias meansfor selectively coupling the intermediate node to
`
`the ground terminal or leaving said intermediate nodefloating. Clm 15)]
`
`It would have been obviousto one of ordinary skill in the art at the time of
`
`invention to modify Smith and Watanabe with Sali to incorporate first and second
`
`intermediate nodes are coupled together, and are coupled to ground as claimed for the
`
`purposeof creating an efficient voltage regulation circuit.
`
`Claim 24 is rejected under 35 U.S.C. 103(a) as being unpatentable over Smith et al
`
`(2005/0162145), (herein after, Smith), in view of Watanabe et al (2004/0061544),
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 16
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 16
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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 15
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`(herein after, Watanabe), and further in view of Lee et al (2004/0257899), (herein after,
`
`Lee):
`
`As to claim 24, Smith and Watanabe teach the element of claim 1, above.
`
`Smith and Watanabe teach do notteach in which theinput terminalof the first
`
`transistor of the first element of the first stage is coupled to an output of a zeroth stage.
`
`Lee teachesin whichthe input terminal of the first transistor of the first elementof
`
`the first stage is coupled to an output of a zeroth stage. [0026 teachestransistors GT,
`
`which electrically connect the sensebit lines SBLO and SBLOB tothe zeroth pair of
`
`input/output lines 100].
`
`It would have been obviousto oneof ordinary skill in the art at the time of
`
`invention to modify Smith and Watanabe with Lee to incorporate input terminal of the
`
`first transistor of the first elementof the first stage is coupled to an output of a zeroth as
`
`claimed for the purposeof creating an efficient input and output data movement.
`
`Claim 25 is rejected under 35 U.S.C. 103(a) as being unpatentable over Smith etal
`
`(2005/0162145), (herein after, Smith), in view of Watanabe et al (2004/0061544),
`
`(herein after, Watanabe), and further in view of Lee et al (2004/0257899), (herein after,
`
`Lee).
`
`As to claim 25, Smith and Watanabeteacha transistor having an input terminal,
`
`an output terminal, and a gate, in which its gate is coupled to receivethefirst phase,
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 17
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 17
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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 16
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`and the input terminal is connected to ground. [0023 teaches RFID chip having the first
`
`pad (130) operatively connected to thefirst antenna (100) signal (RF1), having input
`
`terminal, output terminal. Fig. 4 shows the input terminal connected with the reference
`
`point.]
`
`Smith and Watanabe teach do not zeroth stage.
`
`Lee teacheszeroth stage. [0026 teaches transistors GT, which electrically
`
`connect the sensebit lines SBLO and SBLOB to the zeroth pair of input/outputlines 100]
`
`lt would have been obviousto oneofordinary skill in the art at the time of
`
`invention to modify Smith and Watanabewith Lee to incorporate zeroth as claimed for
`
`the purposeof creating anefficient input and output data movement.
`
`Conclusion
`
`The prior art made of record and notrelied upon is considered pertinent to
`
`applicant's disclosure.
`
`See PTO-892
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to PAUL OBINIY! whose telephone numberis (571)270-
`
`5732. The examiner can normally be reached on 7:30 AM - 6:00 PM; Mon-Thurs..
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 18
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 18
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`

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`Application/Control Number: 12/042,117
`Art Unit: 2612
`
`Page 17
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`lf attempts to reach the examiner by telephone are unsuccessful, the examiner's
`
`supervisor, George Bugg can be reached on 571-272-2998. The fax phone numberfor
`
`the organization where this application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval (PAIR) system. Status information for
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
`
`you have questions on access to the Private PAIR system, contact the Electronic
`
`Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a
`
`USPTO Customer Service Representative or access to the automated information
`
`system, call 800-786-9199 (IN USA OR CANADA)or 571-272-1000.
`
`/ Obiniyi Paul/
`Examiner, Art Unit 2612
`
`/George A Bugg/
`Supervisory Patent Examiner, Art Unit 2612
`
`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 19
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`Mylan Exhibit 1088
`Mylan v. Regeneron, IPR2021-00880
`Page 19
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`

`

`a
`Dacrener
`worm Grae
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark (Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`WWW ISplO,g0V
`
` APPLICATION NO.
`
`12/042,117
`
`FILING DATE
`
`03/04/2008
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`Ronald A Oliver
`
`5088.0181USU1/IMPJ-0290
`
`2746
`
`Turk IP Law, LLC [eee|
`
`1770 Highlands View
`OBINIYI, PAUL I
`Smyrna, GA 30082 2612
`
`EXAMINER
`
`as
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`08/18/2011
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period forreply, if any,is set in the attached communication,
`
`Notice of the Office communic