throbber
DECLARATION OF JACK C. LEE, PHD
`
`
`
`1. My name is Jack Lee. I am over the age of twenty-one (21) years,
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`of sound mind, and capable of making the statements set forth in this Declaration. I
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`am competent to testify about the matters set forth herein. All the facts and
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`statements contained herein are within my personal knowledge and they are, in all
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`things, true and correct.
`
`2.
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`I have been asked by Qualcomm Inc. (“Qualcomm”) to submit
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`this declaration in support of its challenge to the validity of certain claims of U.S.
`
`Patent No. 6,534,805 (“the ’805 Patent”).
`
`I.
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`Education and Experience
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`3. My curriculum vitae is attached as Exhibit 1022.
`
`4.
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`I received my Bachelor of Science and Master of Science
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`Degrees in Electrical Engineering from University of California at Los Angeles in
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`1980 and 1981, respectively and my Ph.D. degree in electrical engineering from
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`University of California at Berkeley in 1988.
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`5.
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`I have more than 35 years of experience as an electrical engineer
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`in integrated circuit and semiconductor device design, fabrication, and testing. I
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`began my career at the TRW Microelectronics Center in 1981 and joined the faculty
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`at The University of Texas at Austin in 1988.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 1 of 168
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`

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`6.
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`I have published over 550 journal publications and conference
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`proceedings, 6 book and book chapters, and have 9 issued patents. I have been
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`recognized with many teaching and research awards. I have supervised and
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`graduated more than 40 Ph.D. students. I am a fellow of the Institute of Electrical
`
`and Electronic Engineers (IEEE) and have been a Distinguished Lecturer for the
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`IEEE Electron Devices Society.
`
`7.
`
`At The University of Texas at Austin, I teach undergraduate
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`circuit analysis and design courses, as well as graduate level courses. One graduate
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`course that I developed is entitled “Nanoscale Device Physics and Technologies,”
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`which focuses on the topics of current research on ultra-small high-speed
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`semiconductor devices used in integrated circuits and is designed for graduate
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`students wishing to pursue research in the nanotechnology area.
`
`8.
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`Having the above knowledge and experience, I am well qualified
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`to offer the opinions I express in this declaration.
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`II. Compensation
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`9.
`
`In consideration for my services, my work on this case is being
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`billed to Qualcomm at an hourly rate of $650 per hour, independent of the outcome
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`of this proceeding. I am also being reimbursed for reasonable expenses I incur in
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`relation to my services provided for this proceeding.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 2 of 168
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`III. Legal Considerations
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`10. My understanding of the law is based on information provided
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`by counsel for Qualcomm.
`
`11.
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`I understand that a U.S. Patent document is presumed to have
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`sufficient description to include sufficient detail for a person of ordinary skill in the
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`art to make and use the subject matter that document describes.
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`12.
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`I understand that a claimed invention is obvious and, therefore,
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`not patentable if the subject matter claimed would have been considered obvious to
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`a person of ordinary skill in the art (POSITA) at the time that the invention was
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`made. I understand that a claim can be obvious in view of a single prior art reference
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`(e.g., via modification of that prior art reference) or multiple prior art references
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`(e.g., via a combination of two or more prior art references), if such a modification
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`or combination was within the skill of a POSITA. I understand that there must be
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`some articulated reasoning with some rational underpinning to support a conclusion
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`of obviousness. I further understand that exemplary rationales that may support a
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`conclusion of obviousness include: (1) simply arranging old elements in a way in
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`which each element performs the same function it was known to perform, and the
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`arrangement yields expected results, (2) merely substituting one element for another
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`known element in the field, if the substitution yields no more than a predictable
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`result, (3) combining elements in a way that was “obvious to try” because of a design
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 3 of 168
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`need or market pressure, where there was a finite number of identified, predictable
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`solutions, (4) that design incentives or other market forces in a field would have
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`prompted variations in a work that were predictable to a person of ordinary skill in
`
`the art, and (5) that there was some teaching, suggestion, or motivation in the prior
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`art that would have led a POSITA to modify the prior art reference or to combine
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`prior art references to arrive at the claimed invention, among other rationales.
`
`13.
`
`
`
`I understand that a claim term is interpreted according to
`
`its ordinary and customary meaning as a POSITA would have understood the term
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`in light of the surrounding claim language, other claims, the specification, and the
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`patent’s prosecution history, which are referred to as intrinsic evidence. I also
`
`understand that prior art references cited in the patent’s prosecution history are
`
`considered intrinsic evidence. I further understand that evidence outside the patent
`
`and its prosecution history (e.g., dictionaries and technical articles), may inform the
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`context in which a POSITA would have understood the claims of a patent. I
`
`understand
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`this ordinary and customary meaning applies absent unique
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`circumstances, such as where a patent clearly expresses an intent to set forth a special
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`meaning for a term, or a claim term does not convey any particular structure to a
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`POSITA (e.g., “means”).
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 4 of 168
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`IV. Task Summary
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`14.
`
`I have been asked to review the ’805 Patent. I have been asked
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`to provide my opinions from the perspective of a person of ordinary skill, having
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`knowledge of the relevant art, as of April 9, 2001, and the opinions stated in this
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`declaration are from that perspective. The qualifications and abilities of such a
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`person are described in Section VI below.
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`15.
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`In preparing this declaration, I have considered this patent and its
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`prosecution and reexamination history as well as the general knowledge of those
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`familiar with the field of semiconductor design and manufacturing, and specifically
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`SRAM cells, as of April 9, 2001.
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`16.
`
`I have also reviewed the references that form the basis for
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`Qualcomm’s challenge to the ’805 Patent, including the publications listed in the
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`following table:
`
`1001
`1002
`1003
`1004
`
`1005
`1006
`1007
`
`Exhibit No. Description
`U.S. Patent No. 6,534,805 (with Ex Parte Reexamination
`Certificate Appended)
`Omitted
`Omitted
`U.S. Patent No. 6,417,549 (“Oh”)
`R. Jacob Baker et al., CMOS Circuit Design, Layout And
`Simulation, IEEE Press (1998) (“CMOS Circuit Design”)
`Prosecution History for U.S. Patent Application No. 09/829,510
`Ex Parte Reexamination History for U.S. Patent No. 6,534,805
`Ishida, et al., “A Novel 6T-SRAM Cell Technology Designed with
`Rectangular Patterns Scalable beyond 0.18 μm Generation and
`Desirable for Ultra High Speed Operation,” IEDM 98, IEEE 1998,
`
`1008
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 5 of 168
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`

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`pp. 201-204 (“Ishida IEDM”)
`U.S. Patent No. 6,677,649 (“Osada”)
`Certain Static Random Access Memories and Products Containing
`the Same, USITC Inv. No. 337-TA-792, Order 29 (Feb. 9, 2012)
`Omitted
`Omitted
`Omitted
`Omitted
`Omitted
`Omitted
`Omitted
`Omitted
`Declaration of Dr. Jack Lee
`U.S. Patent No. 5,702,982 (“Lee”)
`U.S. Patent No. 6,347,062 (“Nii”)
`Dr. Jack Lee CV
`U.S. Patent No. 5,930,163 (“Hara”)
`Ben G. Streetman et al., Solid State Electronic Devices, Prentice
`Hall (5th ed. 2000) (“Streetman”)
`U.S. Patent No. 6,399,511 (“Tang”)
`Basic Integrated Circuit Technology Reference Manual (1993)
`(“Bowman”)
`U.S. Pat. No. 4,584,027 (“Metz”)
`Declaration of Dr. Sylvia Hall-Ellis
`U.S. Pat. No. 4,795,716 (“Yilmaz”)
`U.S. Pat. No. 4,574,467 (“Halfacre”)
`Petition, IPR2020-00990 (P.T.A.B.) (“AMD IPR Petition”)
`
`1009
`
`1010
`1011
`1012
`1013
`1014
`1015
`1016
`1017
`1018
`1019
`1020
`1021
`1022
`1023
`
`1024
`1025
`
`1026
`1027
`1028
`1029
`1030
`1031
`
`
`
`V.
`
`Field of Technology
`
`17. The ’805 Patent “relates to semiconductor memory device
`
`fabrication” and, specifically, “Static Random Access Memory (SRAM) cell design
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`and method of manufacture.” Ex. 1001, at 1:7-10.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 6 of 168
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`

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`18.
`
`I provide some background on concepts related to the ’805 Patent
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`below.
`
`A.
`
`Semiconductor Transistors
`
`19. Semiconductor integrated circuits (more simply “integrated
`
`circuits,” “I.C.s,” or “chips”) are the key components in many popular electronic
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`devices such as televisions, computers, cell phones, and digital cameras. Ex. 1024,
`
`at 420-423. Integrated circuits allow a large amount of circuitry to be fabricated on
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`a semiconductor substrate. The development and commercialization of integrated
`
`circuits have impacted virtually all segments of society, and continuing
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`technological advancements promise to extend this impact even further.
`
`20. The transistor is a building block of semiconductor integrated
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`circuits. The transistor acts as a tiny electronic switch that can control or regulate
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`the amount of electric current flow between two points. Because the transistor can
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`be turned on or off by application of a specific electric voltage, it is able to
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`manipulate a single unit of information, often referred to as a “bit.” By connecting
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`many transistors together in a device, integrated circuits can be constructed to
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`manipulate and process many bits of data. In this manner, transistors can be
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`combined to perform complex functions such as mathematical computation and
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`digital image processing.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 7 of 168
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`

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`21. A transistor type commonly used both in the 1990’s and today is
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`the Metal-Oxide-Semiconductor Field Effect Transistor, or “MOSFET.” Ex. 1024,
`
`at 286-306. The MOSFET typically is formed on single-crystal silicon substrate (or
`
`“substrate”) and has three main terminals: a (1) “source”; (2) “drain”; and (3) “gate.”
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`The source and drain are formed by implanting, or “doping,” specific regions of the
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`silicon with atoms of other elements, such as boron or arsenic. The gate normally is
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`a polysilicon or metal electrode formed directly over a thin insulator layer (referred
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`to as a “gate dielectric” layer or a “gate oxide” layer). The gate is positioned between
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`the source and drain, and the region between the source and drain is often referred
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`to as the “channel.” The entire MOSFET is created in a doped region of the silicon
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`substrate referred to as a “well.”
`
`22. The operation of a MOSFET is conceptually simple. The
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`MOSFET acts as a switch that controls the flow of electric current through the
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`channel between the source and drain regions. When a voltage applied to the gate
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`(Vgs) is equal to or above the “turn-on voltage” (VT) commonly referred to as the
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`threshold voltage, e.g., Vgs ≥ VT, and at the same time a voltage is applied to the
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`drain, the MOSFET is “turned on” and current can flow through the channel between
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`the source and drain regions. Alternatively, when the voltage applied to the gate is
`
`less than the threshold voltage, e.g., Vgs < VT, the MOSFET is “turned off” and
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`current flow through the channel is prevented.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 8 of 168
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`

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`23. There are two main types of MOSFETs: n-channel and p-
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`channel, also referred to as NMOS and PMOS. For n-channel MOSFETs, the
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`source/drain are commonly created by doping with arsenic or phosphorous. The
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`source/drain of p-channel MOSFETs are commonly created by doping with boron.
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`The wells in which MOSFETs are formed are similarly characterized as n-type and
`
`p-type. N-type and p-type wells are simply referred to as “n-wells” and “p-wells,”
`
`respectively. Like the source/drain of n-channel and p-channel MOSFETs, n-wells
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`are typically doped with arsenic or phosphorous, and p-wells are typically doped
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`with boron. However, the wells are of opposite doping type from the source/drain,
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`and normally are not as heavily doped as the source/drain themselves. In other
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`words, p-channel MOSFETs are formed in n-wells, and n-channel MOSFETs are
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`formed in p-wells. N-channel and p-channel MOSFETs are complementary, and
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`thus in operation of an inverter, e.g., one is off while the other is on.
`
`24. Transistors are mostly characterized by the size of one of their
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`features. For example in MOSFETs, this feature size is roughly the length of the
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`gate. In 1970, the minimum feature size was approximately eight microns (i.e., 8 x
`
`10-6 meters, or eight millionths of a meter). To put this in perspective, a human hair
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`is typically 50-100 microns in diameter. During the 1990s, the minimum feature
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`size in cutting-edge technology moved well below one micron (1 µm). Devices
`
`where the minimum feature size is less than one micron are called “submicron”
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 9 of 168
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`

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`devices. Today, minimum feature sizes of <0.02 µ m (20 nanometers, or simply
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`20nm) can be found in the state-of-the-art integrated circuits.
`
`B.
`
`Transistor Structures
`
`25. Transistors formed in semiconductor substrates may include
`
`electrical wells. For example, transistors formed in semiconductor substrates, such
`
`as silicon wafers, include a doped source region and a doped drain region. Ex. 1026,
`
`at 2-55. The doped source and drain regions are portions of the silicon wafer that
`
`contain impurities that modify the electrical characteristics of the silicon wafer
`
`regions. Additionally, the transistors are often formed in isolation wells to
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`electrically isolate one transistor from another transistor on the silicon wafer. Id., at
`
`2-74. One common type of integrated circuit (IC) is the complementary metal-oxide
`
`semiconductor (CMOS) IC. A CMOS IC includes transistors constructed in p-wells
`
`and transistors constructed in n-wells to allow construction of NMOS and PMOS
`
`transistors, respectively. Id., at 2-74-2-76.
`
`26. One example CMOS IC structure is shown in U.S. Pat. No.
`
`4,584,027 (“Metz”) (Ex. 1027). Metz’s Figure 6 illustrates the use of p- and n-
`
`electrical wells in a substrate:
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 10 of 168
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`

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`27. CMOS ICs are desirable for many electronic applications
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`because of the ability to form PMOS and NMOS transistors on the same substrate,
`
`thus allowing electronic devices to take advantage of the benefits of PMOS
`
`transistors and the benefits of NMOS transistors. Metz describes some of these
`
`
`
`benefits:
`
`The advantages to CMOS IC of using multiple-well structures are well-
`known. These include the control of substrate conductivity and of
`doping levels, and the potential for accurate dimensional control and
`decreased device size and the resulting increase packing density and
`speed. These and other advantages are discussed, for example, in Chen,
`QUADRUPLE-WELL
`FOR VLSI TECHNOLOGY,
`IEEE
`Transactions on Electron Devices, Vol. ED-31, No. 7, July 1984, pp
`910-919. Accordingly, the advantages need not be discussed at length
`here. It is sufficient to note that among the issues which are of
`paramount importance at present are the need to decrease the latch-up
`phenomenon and the need to increase the relatively low CMOS packing
`density (relative to NMOS technology). Packing density would be
`increased by decreasing the large lay-out space which is required to
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 11 of 168
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`form the opposite conductivity regions for the n-channel and p-channel
`transistors.
`
`Ex. 1027, at 1:24-41.
`
`28. Other advantages of CMOS technology include very low static
`
`power dissipation, reduced circuit complexity, and good noise immunity. Other
`
`types of ICs include NMOS ICs and PMOS ICs, each of which can also include an
`
`electrical well in the substrate. For example, NMOS ICs with electrical wells in the
`
`substrate include the n-MOSFETs described in U.S. Pat. No. 4,574,467 (Ex. 1030)
`
`(having an n-well shown in, e.g., figs. 9-15 and described in the accompanying text).
`
`As another example, PMOS ICs with electrical wells in the substrate include the p-
`
`MOSFETs described in U.S. Pat. No. 4,795,716 (Ex. 1029) (having a p-well shown
`
`in, e.g., fig. 11 and described in the accompanying text).
`
`29. Electrical wells in the substrate are generally formed by adding
`
`n-type or p-type dopants to the substrate. Ex. 1026, at 2-47. One example technique
`
`is implanting the dopants by accelerating them at high energy towards the substrate
`
`surface. Once the electrical wells for NMOS, PMOS, or CMOS devices are formed
`
`in the substrate, subsequent semiconductor manufacturing steps can be performed
`
`on the substrate agnostic of the existence of the electrical wells on the substrate. For
`
`example, the dual damascene process I describe in Section V.F below can be used
`
`to form contacts to a substrate having electrical wells housing n-FET and p-FET
`
`devices that are part of a CMOS device. Indeed, the many benefits of CMOS
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 12 of 168
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`devices, which include electrical wells in the substrate, would motivate a person of
`
`ordinary skill in the art to re-use known semiconductor manufacturing processes on
`
`substrates with electrical wells for building CMOS ICs. Doing so would obtain the
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`benefits of various known semiconductor manufacturing processes to improve the
`
`performance of the IC.
`
`C.
`
`Integrated Circuits
`
`30. By connecting MOSFET transistors and other electronic
`
`components (e.g., capacitors, resistors, and diodes) through metal layers, various
`
`types of integrated circuits can be fabricated, including logic chips and
`
`semiconductor memory chips.
`
`31. Logic chips are semiconductor integrated circuits designed to
`
`perform complex logic functions. Transistors acting as electronic switches are used
`
`to implement logic gates, which in turn can be cascaded in the same way that logic
`
`functions, also known as Boolean functions, can be composed. Logic circuits or
`
`logic chips, including such devices as multiplexers, arithmetic logic units and
`
`registers all the way up through microprocessors, are fabricated and may contain
`
`more than a billion logic gates.
`
`D.
`
`Static Random-Access Memory (SRAM) Circuits
`
`32. Semiconductor memory is a digital data storage device generally
`
`implemented with an
`
`integrated circuit on a semiconductor substrate.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 13 of 168
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`

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`Semiconductor memory can be categorized into two classes – volatile memory, e.g.
`
`SRAM and DRAM, which loses its stored data when the power to the memory chip
`
`is turned off; and non-volatile memory, e.g. flash memory, which preserves the
`
`stored data even when the power to the memory chip is turned off.
`
`33. Memory devices store data in memory cells. Some memory
`
`devices are so-called single-bit per cell. A single-bit per cell memory device stores
`
`one bit of information. In single-bit per cell memory devices, the memory cell can
`
`be “programmed” according to an “on” or “off” state. The “on” or “off” state defines
`
`one “bit” of information. In a device designed for a single-bit per cell, the device
`
`can store as many bits as the device has cells. To increase the storage capacity of
`
`such a device, it is necessary to increase the number of memory cells to
`
`accommodate additional bits of information.
`
`34. A typical SRAM cell is made up of six transistors, with bit in an
`
`SRAM stored on four transistors (e.g., transistors M1, M2, M3, M4 below) that form
`
`two cross-coupled CMOS inverters. As discussed in § 19, CMOS refers to
`
`integrated circuits formed of both n-channel MOSFETs (NMOS) and p-channel
`
`MOSFETs (PMOS). A representative SRAM circuit is shown below:
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 14 of 168
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`

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`M2
`
`M4
`
`M5
`
`M6
`
`M1
`
`M3
`
`
`
`See Ex. 1005, at 332. The input of a first inverter is connected to the output of a
`
`second inverter and vice versa. Such positive feedback configuration is commonly
`
`referred to as a bi-stable latch or a flip-flop because their outputs are locked
`
`or latched onto their input state until there is another change to its input condition.
`
`The four transistors (M1-M4) of the bi-stable latch are often referred to as the latch
`
`transistors. Ex. 1001, at 5:27-28. In the exemplary circuit schematic above,
`
`transistors M1 and M2 form the first inverter, and M3 and M4 form the second
`
`inverter. Transistors M1 and M3, typically n-channel MOSFETs, act as the driver
`
`of the inverters and hence, they are commonly referred to as the drive transistors,
`
`while M2 and M4, typically p-channel MOSFETs, act as the load of the inverters
`
`and hence, they are commonly referred to as the load transistors. Ex. 1004 at 1:43-
`
`67. Two additional access transistors (e.g., transistors M5 and M6 above) operate
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 15 of 168
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`

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`to control access to the SRAM cell during read and write operations; they are also
`
`called pass transistors. Ex. 1001, at 6:53-64.
`
`35. Access to the SRAM cell is provided by a word line that controls
`
`the two access transistors (M5 and M6, above). Memory information is read or
`
`written into the SRAM cell through the bit lines (e.g., Bit and Bit). Word lines
`
`typically correspond to rows of an SRAM circuit (i.e., lateral or horizontal direction),
`
`while bit lines correspond to columns of an SRAM circuit (i.e., longitudinal or
`
`vertical direction). As such, word lines are arranged orthogonal to bit lines.
`
`36. The bit lines are used to transfer data for both read and write
`
`operations. For example, during read operations to the SRAM cell, the bit lines are
`
`actively driven high and low by the inverters in the SRAM cell.
`
`E.
`
`Semiconductor Manufacturing
`
`37. Semiconductor manufacturing refers to techniques used to form
`
`structures for electrical components on and in a semiconductor substrate. Ex. 1026,
`
`at 2-107-2-109. Semiconductor manufacturing techniques are used in the fabrication
`
`of integrated circuits on/in, for example, silicon wafer substrates. Id., at 2-109.
`
`These techniques generally involve four processes: deposition, doping, etching, and
`
`patterning. Id., at 2-109. Deposition involves the formation of materials on a
`
`substrate. Deposition techniques include physical sputter deposition, chemical
`
`vapor deposition, and/or evaporation, among others. Id., at 2-67. Doping is the
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 16 of 168
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`intentional introduction of impurities into the semiconductor for the purposes of
`
`adjusting its electrical, optical, and/or structural properties. Doping techniques
`
`include diffusion and ion implantation. Etching involves the removal of materials
`
`from a substrate or from the layers above the substrate. Etching techniques include
`
`dry plasma etching, wet etching, and reactive ion etching. Id., at 2-40-2-41.
`
`Patterning involves transferring the layout patterns from the mask to the formation
`
`of discrete structures on or in the substrate. Patterning processes can involve
`
`exposing layers of photoresist material to a masked light source and developing the
`
`photoresist material to separate exposed from unexposed regions of the photoresist
`
`material. The patterned photoresist layer can be used to transfer patterns by etching
`
`into lower layers that were previously formed by deposition. Id., at 2-21-2-23.
`
`38. Each of these steps, deposition, doping, etching, and patterning,
`
`involves different tools and different chemistries. The more steps involved in a
`
`manufacturing process, the more complex and higher cost is the process. For
`
`example, some etches are chemically incompatible and should not be performed in
`
`the same chamber. As another example, depositing different materials requires
`
`multiple material sources. In both of these examples, each different process (e.g.,
`
`different etch and different deposition) requires a different recipe that must be
`
`carefully crafted and the execution of each recipe must be carefully monitored. Each
`
`different recipe involved in manufacturing increases the likelihood of failure, such
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 17 of 168
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`as through introduction of defects, in the manufacturing process. The yield of a
`
`manufacturing process refers to the percentage of manufactured ICs that are
`
`operational from the total manufactured ICs. For example, a 75% yield refers to a
`
`manufacturing process in which only three out of every four manufactured ICs are
`
`operational. Supplies and time are consumed in the manufacturing of these non-
`
`operational ICs, thus lower yields result in lower profits. A POSITA is motivated to
`
`reduce complexities in the manufacturing process to reduce costs, increase yield, and
`
`improve profits. One technique such a POSITA would consider is using similar
`
`materials where possible.
`
`39.
`
`I will now describe an example manufacturing process for an
`
`integrated circuit. The process to fabricate integrated circuit chips takes place in a
`
`clean room. This process involves a series of principal steps, including
`
`photolithography (i.e. masking), etching of various layers, doping (i.e., introducing
`
`impurities), the deposition of various layers (e.g., dielectrics, polysilicon, metals)
`
`and planarization (e.g. chemical-mechanical polishing). The following paragraphs
`
`describe some of the basic process steps, which were used in the 1990’s and which
`
`are still used today. The steps described below, however, are only some of the many
`
`steps in the fabrication process.
`
`40. The first step in semiconductor manufacturing begins with a
`
`wafer, which is a thin, round slice of a semiconductor material, usually silicon.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 18 of 168
`
`

`

`Integrated circuits are formed in and on the wafer. There may be millions or even
`
`billions of transistors on a single die, and tens or hundreds of dies on a single wafer.
`
`While there are many layers and types of structures on the die, the fabrication process
`
`begins with the fabrication of the transistors. When the fabrication processing on a
`
`wafer is completed, the wafer would be diced up and each die would typically be
`
`packaged in a suitable package (chip carrier) into a chip.
`
`F. Damascene Processes
`
`41. Copper has several major advantages over aluminum, which was
`
`used in the older generations of semiconductor manufacturing. Copper has much
`
`lower resistance and exhibits less of an electromigration problem. This means that
`
`integrated circuits that use copper as the interconnect wiring can potentially operate
`
`faster, use less power, and are more reliable than those use aluminum. Copper also
`
`has higher thermal conductivity than aluminum. This allows the metallization to
`
`conduct more heat away from the silicon die and thereby reduces the operating
`
`temperature. Lower operating temperature leads to improved performance and
`
`reliability of the integrated circuit chip.
`
`42. However, copper has the disadvantages that it “contaminates”
`
`other materials which gets in contact to it, and copper cannot be easily etched in
`
`typical dry etch processes. Therefore, damascene processes with barrier layers have
`
`been developed to circumvent these problems. A damascene process can be used to
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 19 of 168
`
`

`

`form a metal contact and metal lines from an upper, metal layer to a region of a
`
`substrate, without the use of a dry or wet etch processes. As can be seen below, the
`
`damascene process results in relatively flat surfaces after subsequent metal and inter-
`
`metal dielectric layers. The flat surfaces enable much better resolution of
`
`photolithographic process by reducing the depth of focus, and thereby allow
`
`“printing” smaller device dimensions and spacings. The flat surfaces also enable
`
`multi-level structures. In other words, it allows many more metal interconnect layers
`
`to stack on the substrate. The flat surfaces further improve the step coverage of
`
`subsequent layer deposition. Finally, to remove excess metal, the damascene
`
`process makes use of planarization, i.e. polishing, instead of chemical etching. This
`
`allows the use of metals that are difficult to be etched, e.g. copper.
`
`43. Two variations of the damascene process are a single damascene
`
`process and a dual damascene process. Ex. 1024, at 443-44. A single damascene
`
`process generally involves patterning a via into a lower insulating layer, depositing
`
`conductor in the via, planarizing the conductor, patterning a trench into an upper
`
`insulating layer over the conductor, depositing conductor in the trench, and
`
`planarizing the conductor.
`
`44. A dual damascene process is similar to the single damascene
`
`process described above, but it creates the features (trenches for lines and holes for
`
`vias) by simultaneously metallizing the features. One example of a dual-damascene
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 20 of 168
`
`

`

`process is shown in U.S. Pat. No. 6,399,511 (“Tang”) (Ex. 1025). Tang has a filing
`
`date of December 1, 2000, with a priority date of July 9, 1998, and reflects the
`
`knowledge of a POSITA regarding dual damascene processing. Tang’s Fig. 1
`
`illustrates a trench 22 through a dielectric layer 20 with vias 18 extending through a
`
`dielectric layer 14:
`
`45. The structure involves etch stop layers 12 and 16 that are used in
`
`
`
`forming the trench and via structures. Tang describes that:
`
`Over a substrate 10 is formed a thin lower stop layer 12 having a
`minimal thick of, for example 100 nm, a lower dielectric layer 14,
`having a thickness of, for example, 1 μm or somewhat less, and a thin
`upper stop layer 16. The stop layers 12, 16 have compositions relative
`to the dielectric material such that a carefully chosen etch process that
`is selective to the material of the stop layer etches through the overlying
`dielectric but stops on the stop layer.
`
`Ex. 1025, at 1:66-2:6. During the etching of the trench and via:
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1019, IPR2021-00704
`Page 21 of 168
`
`

`

`The combined etch must not significantly etch the upper stop layer 16
`at the floor 24 of the trench 22, and it must stop at the lower stop layer
`12 at the bottom 26 of the via holes 18. In a further step, not illustrated
`here because it is generally considered to be non-crucial, a further non-
`selective etch removes the portion of the lower stop layer 12 at the
`bottom of the via hole 18 so as to expose the substrate 10 to contacting
`when metal is filled into the trench 22 and via hole 18.
`
`Ex. 1025, at 3:15-22. The trench and via are then filled with conductor to form the
`
`contact to the substrate. Id., at 3:23-26. Tang notes that “[t]he metallization
`
`operation may require that the trench 22 and via hole 18 be coated with barrier layers
`
`and wetting layers, as has become well known in metallization of small features in
`
`advanced integrated circuits.” Id., at 3:26-29. Note that the use of planarization
`
`technique in the damascene process results in extremely flat surfaces after each
`
`subsequent metal interconnect layer.
`
`46. Tang discloses using the same material for two etch stop layers
`
`in a dual damascene process– silicon nitride. Id., at 9:27-30. Use of the same
`
`material in the two etch stop layers would provide benefits, including improved yield
`
`and lower costs.
`
`47. As used by Tang and understood by a POSITA, a barrier layer
`
`refers to a layer that is used to improve metal adhesion and/or prevent inter-diffusion
`
`between layers on opposite sides of the barrier layer.
`
`48. As used by Tang and understood by a POSITA, an etch stop layer
`
`refers to a layer th

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