(12) United States Patent
`Dawson et al.
`
`USOO6348,906B1
`(10) Patent No.:
`US 6,348,906 B1
`(45) Date of Patent:
`Feb. 19, 2002
`
`(54) LINE SCANNING CIRCUIT FOR A
`DUAL-MODE DISPLAY
`
`(75) Inventors: Robin Mark Adrian Dawson,
`Princeton; Zilan. Shen, Lawrenceville;
`Alfred Charles pri, Princeton; Roger
`Green Stewart, Neshanic Station;
`James Harold Atherton, Ringoes;
`Stephen John Connor, Trenton, all of
`NJ (US)
`
`(73) Assignee: Sarnoff Corporation, Princeton, NJ
`(US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`(21) Appl. No.: 09/384,063
`22) Filled:
`Aug. 26, 1999
`(22) Filed:
`lug. 20,
`Related U.S. Application Data
`(60) Provisional application No. 60/099,019, filed on Sep. 3,
`1998.
`(51) Int. Cl." .................................................. G09G 3/32
`(52) U.S. Cl. ............................. 345/82; 345/92; 345/98;
`345/100
`(58) Field of Search .............................. 345/82, 55, 87,
`345/94, 98, 99, 100, 206, 208, 90,92
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`5,600,345 A 2/1997 Dingwall et al. ........... 34.5/100
`
`(VDDP)
`400 I 402
`SDIN S ALSEL
`
`5,648,790 A 7/1997 Lee ............................. 345/58
`5,670,979 A * 9/1997 Huq et al. .................. 34.5/100
`5,686,935 A 11/1997 Weisbrod .................... 34.5/100
`5,739,805. A
`4/1998 Dingwall .................... 34.5/100
`5,859,630 A * 1/1999 Huq ........................... 34.5/100
`5,949,398 A * 9/1999
`im ........................... 34.5/100
`5,952,789 A 9/1999 Stewart et al. ........... 315/169.4
`
`
`
`sk -
`cited by examiner
`
`Primary Examiner Dennis-Doon Chow
`(74) Attorney, Agent, or Firm William J. Burke
`(57)
`ABSTRACT
`0
`-
`A row-select circuit for an organic light emitting diode
`display propagates a gating pulse through a shift register.
`This gating pulse is Synchronized with a System clock signal
`and is used to Selectively apply a plurality of broadcast
`control Signals to a Selected row of pixels on the display. The
`line Scanning circuitry is controlled to clear and autoZero the
`pixels in the display either one line at a time or the entire
`image frame at a time. According to another aspect of the
`invention, the clearing of a row of pixels in the display is
`performed over several line intervals before the row is
`autoZeroed and loaded with new values. According to yet
`another aspect of the invention, the broadcast control Signals
`may be adapted to achieve the best performance for each
`display device.
`
`11 Claims, 6 Drawing Sheets
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`SAMSUNG EX. 1025 - 1/13
`
`

`

`U.S. Patent
`
`Feb. 19, 2002
`
`Sheet 1 of 6
`
`US 6,348,906 B1
`
`
`
`110
`
`
`
`
`
`112
`
`TIMING
`
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`WL
`
`DEMULTIPLEXER
`
`116
`
`SELECT
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`
`
`PXEL ARRAY
`320X240
`
`
`
`DATA ODD
`DATA EVEN
`DATA RESET
`
`
`
`ALL SEL
`ALL SELD
`SELEVEN
`SELODD
`AZEVEN
`AZODD
`AZB EVEN
`AZB ODD
`
`FIG. 1
`
`SAMSUNG EX. 1025 - 2/13
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`

`

`U.S. Patent
`
`Feb. 19, 2002
`
`Sheet 2 of 6
`
`US 6,348,906 B1
`
`DATA
`
`
`
`SELi
`
`AZi
`
`AZBBi
`
`290
`
`265
`
`WBACK
`
`FIG. 2
`
`SAMSUNG EX. 1025 - 3/13
`
`

`

`SDIN
`SCLK1
`SCLK2
`SELODD
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`AZBODD
`AZBBODD
`ALLSEL
`ALLSELD
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`
`
`
`D 802
`
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`ROW_SEL
`SDIN
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`ROW_SEL
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`SAMSUNG EX. 1025 - 4/13
`
`

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`SAMSUNG EX. 1025 - 5/13
`
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`SAMSUNG EX. 1025 - 6/13
`
`

`

`U.S. Patent
`
`Feb. 19, 2002
`
`Sheet 6 of 6
`
`US 6,348,906 B1
`
`
`
`
`LESEHTWIWO
`
`CICIOTWIWO
`
`NEAE
`VIVO
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`TESTTTW
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`CICIOTTES
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`NENETTES
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`CICIOTZW
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`NENETZW.
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`NENET?ZW
`
`SAMSUNG EX. 1025 - 7/13
`
`

`

`US 6,348,906 B1
`
`1
`LINE SCANNING CIRCUIT FOR A
`DUAL-MODE DISPLAY
`
`This applications claims the benefit of U.S. provisional
`application No. 60/099,019 filed Sep. 3, 1998, which is
`incorporated herein by reference.
`This invention was made with Government support
`under Contract No. F33615-96-2-1944 awarded by the
`Department of the Air Force. The Government has certain
`rights in this invention.
`BACKGROUND OF THE INVENTION
`The present invention concerns Video display devices and
`in particular an active matrix organic light-emitting diode
`display which can operate either by clearing the pixels of the
`display device one row at a time or by clearing all of the
`pixels in the pixel array in a Single operation.
`An active matrix display device is one in which image
`data is stored in each picture element (pixel) of the display
`and the image is illuminated for a Substantial part of the
`frame interval. There are two basic active-matrix display
`architectures. The first is a "row at a time' architecture
`where the image is updated one line at a time, as it is being
`displayed. In this architecture, a single row of the pixels is
`cleared and Set-up to receive new data values and then a new
`line of data is written into the cleared pixels. The proceSS
`repeats continually with each line of the image being
`updated at least once in a frame interval.
`The Second type of display architecture clearS and Sets-up
`the entire image in a Single operation and then quickly writes
`new image data into all of the pixels one line at a time. This
`type of display operates in four distinct intervals: clear,
`Set-up, write and illuminate. A display architecture of this
`type is particularly appropriate for use with a color Shutter
`or other device where the entire pixel array is turned off for
`Some fraction of the frame time.
`Organic light emitting diode (OLED) displays are formed
`from a matrix of OLED devices. These devices emit light in
`response to an electric current. The intensity of the light is
`a function of the amplitude of the current. U.S. patent
`application Ser. No. 09/064,696 entitled ACTIVE MATRIX
`ORGANIC LIGHT EMITTING DIODE PIXEL STRUC
`TURES describes an exemplary OLED color matrix display
`device which controls the current through each OLED pixel
`by Storing a Voltage on a capacitor in the pixel cell. AS
`described in this patent, each OLED device is discharged,
`autoZeroed (i.e. Set-up to receive new data) and then loaded
`with the new data.
`AS the number of pixels in a display increases, both the
`horizontal and Vertical Scan rates also increase So that the
`Sequence of imageS can be displayed at a constant frame
`rate. AS the horizontal Scan rate increases, less time is
`available to update each row of pixels in the display.
`Existing row-at-a-time architectures are not well Suited for
`high resolution OLED displays because it is difficult to
`discharge, autoZero and load a row of pixel data in one line
`time at the Scan rate of, for example, a high-definition
`television receiver.
`
`5
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`SUMMARY OF THE INVENTION
`The present invention is embodied in a row Select circuit
`for an organic light emitting diode display. The row Select
`circuit propagates a gating pulse through the shift register.
`This gating pulse is Synchronized with a System clock signal
`and is used to apply a plurality of broadcast control signals,
`to Sequentially Selected rows of pixels on the display.
`
`60
`
`65
`
`2
`According to one aspect of the invention, the line Scan
`ning circuitry is controlled to clear and autoZero the pixels
`in the display either one line at a time or the entire image
`array may be autoZeroed concurrently.
`According to another aspect of the invention, the clearing
`and autoZeroing of a row of pixels in the display may be
`performed over several line intervals before the row is
`loaded with new values. This overcomes the problem of
`reduced Scan time available in high resolution displayS.
`According to yet another aspect of the invention, the
`broadcast control signals may be adapted to achieve the best
`performance for each display device.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a organic light emitting diode
`(OLED) matrix display device which includes an embodi
`ment of the invention;
`FIG. 2 is a schematic diagram of an OLED pixel structure
`suitable for use in the display device shown in FIG. 1;
`FIG. 3 is a block diagram of a Segment of a row Select
`circuit which may be used in the display device shown in
`FIG. 1;
`FIG. 4 is a Schematic diagram of one of the Stages of the
`row select circuit shown in FIG. 3;
`FIG. 5 is a timing diagram which is useful for describing
`the line-at-a-time Scanning mode for the row Select circuit
`shown in FIGS. 3 and 4;
`FIG. 6 is a timing diagram which is useful for describing
`the array autoZero mode for the row select shown in FIGS.
`3 and 4;
`
`DETAILED DESCRIPTION OF THE
`EXEMPLARY EMBODIMENTS
`FIG. 1 is a block diagram of an OLED matrix display
`device which includes an embodiment of the invention.
`Although the exemplary embodiments of the invention are
`described with reference to an OLED display device, it is
`contemplated that they may be practiced with other types of
`display devices, for example liquid crystal device (LCD),
`electroluminescent or plasma panel display devices that are
`operated either in a line-at-a-time mode or an array autoZero
`mode.
`The display shown in FIG. 1 is implemented in a poly
`Silicon technology directly on the active matrix display
`device 116. Exemplary technology for implementing circuits
`Such as the demultiplexing circuitry 112 and row Select
`circuitry in polysilicon is disclosed in U.S. Pat. No. 5,633,
`635 entitled SIMULTANEOUS SAMPLING OF DEMUL
`TIPLEXED DATA AND DRIVING OF AN LCD PIXEL
`ARRAY WITH PING-PONG EFFECT. The present inven
`tion is implemented using a single channel PMOS process.
`It is contemplated, however, that the functions described
`below may be implemented in a single channel NMOS
`process, in a CMOS proceSS or any other transistor technol
`Ogy.
`FIG. 1 shows a display device which includes a plurality
`of pixels arranged in a matrix having, for example, 320
`columns by 240 rows. The display also includes column data
`generators 110 which provide picture data values to a
`demultiplexer 112. The exemplary data generator 110 may,
`for example, include a multiport digital to analog converter
`such as the CL-FP6502 integrated circuit available from
`Cirrus Logic. The demultiplexer 112, responsive to timing
`Signals provided by a timing circuit 114, demultiplexes the
`data values provided by the generators 110 to provide data
`
`SAMSUNG EX. 1025 - 8/13
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`

`US 6,348,906 B1
`
`15
`
`25
`
`3
`for all of the pixels in a row of the display 116. In the
`exemplary embodiment of the invention, the input signals to
`the timing circuit 114 are DATA ODD, DATA EVEN and
`DATA RESET. The signals DATA ODD and DATA
`EVEN are active when data values provided by the demul
`tiplexer 112 are to be written into respective odd and even
`numbered rows of the display 116. When DATA RESET is
`active, null image data (e.g. logic-high values) are applied to
`the column drivers (not shown) of the display 116.
`The image data are updated line-by-line as each row of the
`display device is selected by the row select circuitry 118.
`The row select circuitry 118 may be considered to be a shift
`register which Sequentially Selects each row of the display
`116 and applies a Sequence of control Signals to all of the
`pixels in the row. The Structure and operation of the row
`Select circuit 118 are described below with reference to
`FIGS. 3 and 4. The structure and operation of an individual
`pixel of the display 116 are described below with reference
`to FIG. 2. As described below, when the data to be displayed
`at a particular pixel position changes, the corresponding
`pixel is first reset, then Subject to an autoZero operation, the
`data is written into the pixel and the pixel is illuminated.
`After the new display data is written and until the display
`data in that pixel is to be updated again, the pixel is turned
`on So that it may be illuminated at a level corresponding to
`the display data that was written into the pixel.
`AS described above, the exemplary display device oper
`ates in two modes: line-at-a-time mode in which each row of
`pixels is reset, autoZeroed and rewritten row by row and
`frame at a time mode in which all of the pixels in the pixel
`array 116 are concurrently reset and autoZeroed and then
`display data is written into the reset and autoZeroed pixel
`elements row by row. The input signals to the row Select
`circuit control these operations. These signals include SDIN,
`a pulse Signal which begins the Scanning operation; SCLK,
`the system clock signal; ALL SEL and ALL SELD, which
`control the Selection of the entire display during the reset and
`autoZero operations in array autoZero mode; SEL EVEN
`and SEL ODD which control when respective even and
`odd rows of the pixel array 116 are selected.; and
`40
`AZ EVEN, AZ, ODD, AZB EVEN and AZB ODD
`which control the autoZero and illuminate operations as
`described below with reference to FIG. 2.
`Referring to FIG. 2, the exemplary pixel structure 200
`comprises five PMOS transistors (260,265, 270, and a pair
`of transistors 275), two capacitors 250 and 255 and a LED
`(OLED) 280. The transistors 275 are configured to have
`Series-connected channels and parallel connected gates to
`limit the leakage current which may flow from the pixel
`circuitry into the OLED 280 during the autoZero and data
`load phases. A select (SELi) line 220 is coupled to the gate
`electrode of transistor 260. ADATA signal 210 is coupled to
`the Source electrode of transistor 260. An operational power
`signal 290 which provides a positive potential, VDD (e.g. +5
`V), is coupled to the source electrode of transistor 265 and
`to one terminal of capacitor 255. An auto-Zero (AZi) line
`230 is coupled to the gate electrode of transistor 270 and an
`illuminate (AZBBi) line is coupled to the interconnected
`gate electrodes of transistors 275. The cathode electrode of
`the OLED 280 is coupled to the drain electrode of one of the
`transistors 275 and the anode electrode of the OLED 280 is
`coupled to a Source of negative potential, VBACK (e.g. -15
`V). The OLED 280 has a diode capacitance 281 (shown in
`phantom) which is inherent in the device. The source
`electrode of the other one of the transistors 275 is coupled
`to the connected drain electrodes of transistors 265 and 270.
`The drain electrode of transistor 260 is coupled to one
`
`4
`terminal of capacitor 250. Finally, the gate electrode of
`transistor 265, the Source electrode of transistor 270, one
`terminal of the capacitor 250 and one terminal of the
`capacitor 255 are all coupled together at a node designated
`node A.
`More specifically, FIG. 3 illustrates a pixel structure 200
`that is operated in four phases: 1) a reset phase, 2) an
`auto-Zero phase, 3) a load data phase and 4) an illuminate
`phase.
`In the reset phase, a data value has been Stored at node A,
`the AZi signal 230 is at a logic-high level and the AZBBi
`signal 240 is at a logic-low level. The data signal 210 is
`brought to a logic-high level and the SELi signal 220 is
`pulsed while the data Signal is logic-high. This Step turns on
`transistor 260 causing it to turn off transistor 265 while
`leaving a conductive path from the drain electrode of
`transistor 265 to the cathode electrode of OLED 280. This
`operation allows the OLED 280 to discharge its internal
`capacitance 281, preparing it to be illuminated at a different
`level. In the exemplary embodiment of the invention
`described below with reference to FIG. 5, the reset phase
`occurs in the line interval immediately before the line
`interval in which the autoZero and data load phases occur.
`This is achieved by Selecting each row of pixels for at least
`a portion of two line intervals, resetting the row during the
`first line interval and performing the autoZero and data load
`operations during the Second line interval.
`For Some display types, for example high-definition tele
`Vision displays, more time may be needed to completely
`discharge the capacitance 281 of the OLED 280 than is
`provided in the exemplary embodiment of the invention. For
`these display types, the interval in which an individual row
`of pixels is Selected may be extended to, for example, three
`or ten line intervals and, during each of these line intervals,
`the pixels in the row may be reset by concurrently pulsing
`the DATA RESET signal and the select signals SEL
`EVEN and SEL ODD.
`Returning to FIG. 3, in the auto-Zero phase, the AZiSignal
`220 and the AZBBisignal 240 are set to logic-low, turning
`on the two transistors 275 and the transistor 270. In this
`configuration, the potential at the drain electrode of transis
`tor 265 is coupled to the gate electrode of the transistor. The
`DATA signal 210 is maintained at a logic-high level.
`Next, the AZBBisignal 240 is set to logic-high, so that the
`transistors 275 are turned off. The gate to source potential
`across transistor 265, as stored on capacitor 255, then settles
`to the turn-on threshold voltage of transistor 265. This
`operation Stores the turn-on threshold Voltage acroSS capaci
`tor 255 and stores the difference between the logic-high
`potential and the threshold voltage on capacitor 250. The
`potential Stored on capacitor 255 represents a fixed over
`drive Voltage for transistor 265 regardless of any variation in
`threshold Voltage that may occur due to age or operation.
`The last Step in the auto-Zero operation is to Set the AZi
`Signal to a logic-high value which isolates the gate electrode
`of transistor 265. This operation can be repeated over
`multiple row times in a fashion Similar to the reset operation.
`At the end of the Auto Zero phase, the SELi signal 220 is
`held at a logic-low value and the DATA signal 210 is still at
`the logic-high level. The load data phase begins when a data
`Voltage is applied to the Source electrode of transistor 260
`via the DATA signal 210. This change in the DATA signal is
`coupled through capacitor 250 onto the gate electrode of
`transistor 265 and, So, changes the potential Stored acroSS
`capacitor 255. The change in the charge of capacitor 255 is
`proportional to the change in the DATA signal 210 from the
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`logic-high value to the programmed data Voltage value.
`Because this data Voltage change is made with reference to
`the threshold potential of transistor 265, the change in the
`DATA signal 210 is translated into a gate to Source Voltage
`for the transistor 265 which causes the transistor 265 to
`provide a predetermined current to the OLED 280. Next, the
`SELi signal 220 is set to a logic-high value. Turning off
`transistor 260 but leaving the programmed gate to Source
`current acroSS capacitor 255.
`With the data voltage stored on the capacitor 255, the
`AZBBisignal 240 is set to a logic-low value turning on the
`transistors 275 to allow the predetermined current provided
`by the transistor 265 to flow through the OLED 280. This
`predetermined current causes the OLED 280 to glow at a
`predetermined level of illumination. The illumination phase
`continues for the remainder of the frame interval until it is
`time to Store new image data into the pixel. Then the reset,
`autoZero, load data and illuminate phases are repeated.
`As described above, with reference to FIG. 1, the signals
`SELi, AZi and AZBBi are provided to a particular row i of
`the display 116 by a row select circuit 118. The row select
`circuit includes one Stage for each row in the display 116.
`The row select circuit is controlled in synchronism with a
`four phase clock signal that is derived from the Signal SCLK
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`shown in FIG. 1. The exemplary timing diagram shown in
`FIG. 5 illustrates the relationship among all of the signals
`shown in FIG. 1 and also shows the four phases (SCLK1,
`SCLK2, SCLK3 and SCLK4) of the clock signal SCLK.
`FIG. 3 is a block diagram of a portion of a line-Scanning
`circuit which may be used as the row select circuit 118,
`shown in FIG.1. The portion shown in FIG. 3 includes only
`four Stages. A complete row Select circuit may be formed by
`cascading multiple circuits Such as that shown in FIG.3 until
`the number of Stages equals the number of lines in the
`display 116. An exemplary stage of the row select circuit 118
`is described below with reference to FIG. 4.
`As shown in FIG. 3, the stages of the row select circuit
`118 alternate between odd and even rows with the odd stages
`receiving the odd signals SEL ODD, AZ ODD, AZB
`ODD and AZBB ODD, while the even stages receive the
`corresponding even signals SEL EVEN, AZ EVEN,
`AZB EVEN and AZBB EVEN. All of the stages receive
`the signals ALL SEL, ALL SELD and ALL SELB. Each
`Stage also receives two clock signals. The first Stage 310
`receives the signals SCLK1 and SCLK2, the second stage
`312 receives the signals SCLK2 and SCLK3, the third stage
`314 receives the signals SCLK3 and SCLK4, and the fourth
`stage 316 receives the signals SCLK4 and SCLK1. This
`configuration repeats with each of the cascaded circuits Such
`that, if there were a fifth stage after stage 316, it would
`receive the signals SCLK1 and SCLK2. As described below
`with reference to FIG. 4, the first clock signal is referred to
`as SCLK and the Second clock signal, which is delayed in
`phase by 90 with respect to the first clock signal, is referred
`to as SCLK90.
`The first Stage of the row Select circuit receives a pulse
`Signal SDIN which starts the Scanning operation. Typically,
`the first stage of the row select circuit 116, shown in FIG. 1,
`receives a pulse of the signal SDIN at the start of each frame
`or field. The exemplary display device may display Single
`frames or interlaced fields by virtue of the odd and even
`Select Signals.
`One output signal of each stage is the signal ROW SEL
`which, as described below, controls the gating of the other
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`signals, SELi, AZi and AZBBi to the display row i. The
`signal ROW SEL conforms to a single pulse of the second
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`clock signal applied to the Stage. This pulse occurs once per
`frame interval unless multiple pulses are required for reset
`and autoZero. The ROW SEL output signal of each stage is
`applied to the SDIN input terminal of the next successive
`Stage to propagate the row Selection signal through all of the
`stages of the row select circuit 118.
`The circuit shown in FIG. 4 is a single stage of the row
`Select circuit shown in FIG. 3. At a basic level, the circuit
`shown in FIG. 4 is a shift register which propagates a gating
`Signal (SDIN) from stage to stage. When the Select signal
`propagates to a stage, that Stage applies the broadcast control
`Signals to a particular row. The function of the control
`signals is described above with reference to FIGS. 2 and 3.
`The timing of the control signals is described below with
`reference to the timing diagrams shown in FIGS. 5 and 6.
`As described above, the circuitry shown in FIG. 4 oper
`ates in two modes: a line-at-a-time mode and an array
`autoZero mode. The signals ALL SEL, ALL SELE and
`ALL SELD control the circuit when it is operating in the
`array autoZero mode. When the circuit operates in the
`line-at-a-time mode, the Signals ALL SEL and ALL
`SELD are held at logic-high values while the signal ALL
`SELB (the logical inverse of the signal ALL SEL) is held
`at a logic-low value. The materials that follow describe the
`operation of the circuit first in the line-at-a-time mode and
`then in array autoZero mode.
`The signal SDIN is the gating signal which selects the row
`controlled by the circuitry shown in FIG. 4. The signal SDIN
`may be considered to be a trigger Signal which enables the
`circuit to propagate the control Signals while the Signal
`SCLK90 is in a logic-low state. Until the signal SDIN is
`applied to the stage, both transistors 400 and 402 are turned
`off. Periodic pulses of the signal SCLK turn on transistor
`408 applying a logic-low potential VCCN(e.g. -15V) to the
`gate electrodes of transistors 406, 426 and 430. These
`transistors, in turn, apply a logic-high potential VDDP (e.g.
`+5V) as the output signals of the stage, ROW SEL, SELi
`and AZi.
`As described above, the signal SDIN is the ROW SEL
`Signal from the previous Stage. In the exemplary embodi
`ment of the invention, the signal SDIN is active at the same
`time as the Signal SCLK when the Stage is Selected.
`Consequently, when SDIN is active, both transistors 400 and
`408 are turned on. Transistor 404 is always turned on when
`the display device is operated in line-at-a-time mode
`because the Signal ALL SELB is logic-low in line-at-a-time
`mode. As transistors 408, 404 and 400 are all turned on when
`the Signal SDIN is active, the Signal applied to the gate
`electrodes of the transistors 406, 426 and 430 is brought to
`a logic-high level due to the Voltage divider created by the
`channel resistances of the transistors 406, 426 and 430. The
`logic-high level on the gate electrodes of transistors 406, 426
`and 429 turns these transistors off.
`In addition, when the signal SCLK becomes active, the
`signal SDIN propagates through transistors 412 and 410 to
`the gate electrode of transistor 414. This signal turns on
`transistor 414 allowing the signal SCLK90 to propagate
`through transistor 414 as the row select signal ROW SEL
`for this stage.
`When SCLK90 becomes logic-low, a logic-low signal
`ROW SEL is applied to the source electrodes of transistors
`420 and 424, and to the gate electrodes of transistors 432 and
`436. The transistors 420 and 424 are always turned on
`because their gate electrodes are coupled to the VCCN
`supply. When the signal ROW SEL becomes logic-low,
`transistorS420 and 424 apply the logic-low Signal to the gate
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`electrodes of transistorS 422 and 428, respectively, causing
`these transistors to turn on and pass the broadcast Select
`Signals SEL as the Signal SELi, and the broadcast autoZero
`Signal, AZ, as the autoZero Signal AZi for the display row i
`to which the select stage shown in FIG. 4 is attached.
`Also when the signal ROW SEL becomes logic-low,
`transistors 432 and 436 become conductive. Transistor 432
`then applies the Signal AZB to the gate electrode of transistor
`438 and transistor 436 applies the signal AZBB, through
`transistor 434, which is always turned on because its gate
`electrode is connected to the negative supply VCCN, to the
`gate electrode of transistor 440. As described above, the
`signals AZBB is generated by inverting the signal AZB. The
`output signal, AZBBi of the transistors 438 and 440 is
`logic-high while the Signal AZB is in a logic-low State and
`is logic-low while the Signal AZBB is in a logic-low State.
`This signal is applied to the AZBBi input terminal of each
`pixel in the Selected row, as described above, to allow the
`capacitance 281 inherent in the OLED 280 to discharge, to
`block the OLED while the pixel is being programmed and to
`illuminate the OLED 280 when the row is not selected.
`In array autoZero mode, the circuit shown in FIG. 4 clearS
`and autoZeroS all of the pixels in the display device in a first
`part of the frame interval, Stores data into the pixels on a
`row-by-row basis during a Second part of the frame interval
`and illuminates the display in a third part of the frame
`interval. When the select circuit shown in FIG. 4 operates in
`array autoZero mode, the Signals ALL SEL and ALL
`SELD control the select stage as described below with
`reference to FIG. 6. The signal ALL SELB is the inverse of
`the Signal ALL SEL. In array autoZero mode, the Signal
`SDIN is held at a logic-high value during the reset, autoZero
`and illuminate phases but is used to Select the Successive
`rows of pixels during the data load phase.
`In the circuit shown in FIG. 4, when the signal ALL SEL
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`becomes logic-low, transistor 402 is turned on which applies
`the positive potential VDDP to the gate electrodes of tran
`sistors 406, 426 and 430, turning those transistors off. The
`logic-low ALL SEL Signal is transmitted through transistor
`416 to turn on transistor 418 which applies the signal
`ALL SELD as the signal ROW SEL. As described above,
`the signal ROW SEL allows the signals SEL, AZ, and
`AZBB to be propagated to the row of the display that is
`connected to the Select Stage. Because the Signal ALL SEL
`is applied to all of the Stages of the Select circuit, these
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`Signals are simultaneously applied to all of the rows of the
`display device, clearing and autoZeroing every pixel in the
`display. When the Signal ALL SEL becomes logic-high, the
`reset and autoZero functions have been performed. Next, the
`signals ALL SEL and ALL SELD are deactivated (i.e.
`brought to a logic-high level) and a single pulse signal is
`applied, as the Signal SDIN, to the first stage of the Select
`circuitry. This begins the Scanning the rows of pixels in the
`display device as described above with reference to the
`line-at-a-time mode. In the array autoZero mode, however,
`only the SCLK, SCLK90 and SEL signals are gated through
`the Select Stage when the row is Selected the Signal AZi
`remains at a logic-high level. In this stage, data values are
`written into the pixels. After the data values have been
`written, the signal AZBB is held logic-low to illuminate the
`display. Because only the data load phase is performed in the
`array autoZero mode when an individual line of pixels is
`Selected, the duration of the Select Signal may be much leSS
`than in the line-at-a-time mode.
`The transistor pairs 416, 418; 420, 422; 424, 428 are in a
`bootstrap configuration that allows the respective signals
`ALL SELD, SEL and AZ and AZBB to be provided to the
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`Selected row over their entire range. The operation of this
`bootstrap configuration is described with reference to the
`transistor pair 420 and 422. It is equally applicable to the
`transistor pairs 416, 418; 424, 428 and 434, 430. As
`described above, the gate electrode of transistor 420 is
`coupled to the negative potential VCCN and, So, the tran
`Sistor is turned on as long as the potential applied to the
`Source electrode of the transistor is more than one threshold
`voltage greater than VCCN. In the exemplary embodiment
`of the invention, when the signal ROW SEL first transi
`tions to logic-low, the potential at the drain electrode of
`transistor 420 decreases until it reaches one threshold volt
`age above VCCN. At this point, the transistor 420 is no
`longer conductive and the gate electrode of transistor 422 is
`floating at the potential of VCCN plus one threshold. This
`potential turns transistor 422 on. When the signal SEL
`becomes logic-low, after transistor 420 has turned off, the
`transition from logic-high to logic-low is capacitively
`coupled from the channel of transistor