IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`In re Patent of:
`Daniel Poznanovic, et al.
`
`U.S. Patent No.:
`7,149,867 Attorney Docket No.: 42653-0026IP1
`Issue Date:
`December 12, 2006
`
`Appl. Serial No.: 10/869,200
`
`Filing Date:
`June 16, 2004
`
`Title:
`SYSTEM AND METHOD OF ENHANCING
`EFFICIENCY AND UTILIZATION OF MEMORY
`BANDWIDTH IN RECONFIGURABLE HARDWARE
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 7,149,867 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
`
`
`
`

`

`
`
` 
`
`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`
`TABLE OF CONTENTS
`
`INTRODUCTION.............................................................................................. 1 
`  MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ..................................... 1 
`A.  Real party-in-interest under 37 C.F.R. § 42.8(b)(1) .................................... 1 
`B.  Related matters under 37 C.F.R. § 42.8(b)(2) ............................................. 1 
`C.  Lead and back-up counsel under 37 C.F.R. § 42.8(b)(3) ............................ 2 
`D.  Service information under 37 C.F.R. § 42.8(b)(4) ...................................... 2 
` REQUIREMENTS FOR IPR ............................................................................. 3 
`A.  Payment ........................................................................................................ 3 
`B.  Certification of standing .............................................................................. 3 
`C.  Identification of challenge ........................................................................... 3 
`1.  Challenged claims .................................................................................. 3 
`2.  Specific grounds .................................................................................... 3 
` DISCRETIONARY CONSIDERATIONS ........................................................ 4 
`A.  Relevant Facts .............................................................................................. 5 
`B.  Prior Petitions ............................................................................................... 6 
`C.  Parallel Proceedings ................................................................................... 11 
`D.  Prior Art and Arguments—35 U.S.C. § 325(d) ......................................... 14 
`  TECHNOLOGICAL BACKGROUND ........................................................... 14 
`A.  Conventional computer architecture and data prefetch ............................. 14 
`B.  FPGAs ........................................................................................................ 15 
`C.  Scatter/Gather ............................................................................................ 16 
` THE ’867 PATENT ......................................................................................... 17 
`A.  Summary of the patent ............................................................................... 17 
`B.  Priority date and prosecution history ......................................................... 17 
`C.  Level of ordinary skill in the art ................................................................ 18 
`D.  Claim construction ..................................................................................... 18 
`1.  “reconfigurable processor” in all claims ............................................. 18 
`2.  “data prefetch unit” in all claims ......................................................... 18 
`3.  “data access unit” in claims 11-19 ....................................................... 19 
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`4.  “functional unit” .................................................................................. 19 
`5.  “memory hierarchy” ............................................................................ 19 
`6.  “computational unit” in claims 11-19 .................................................. 19 
`SPECIFIC GROUNDS .............................................................................. 20 
` 
`A.  Overview of the cited prior art references ................................................. 20 
`1.  Zhang (EX1003) .................................................................................. 21 
`2.  Gupta (EX1004) ................................................................................... 22 
`3.  Chien (EX1005) ................................................................................... 24 
`B.  Motivation to combine Zhang, Gupta and Chien ...................................... 25 
`C.  Ground 1: Claims 1-2, 4-8 and 13-19 are obvious over Zhang and Gupta
`
`31 
`1.  Claim 1 ................................................................................................. 31 
`2.  Claim 2 ................................................................................................. 53 
`3.  Claim 4 ................................................................................................. 57 
`4.  Claim 5 ................................................................................................. 58 
`5.  Claim 6 ................................................................................................. 59 
`6.  Claim 7 ................................................................................................. 60 
`7.  Claim 8 ................................................................................................. 60 
`8.  Claim 13 ............................................................................................... 61 
`9.  Claim 14 ............................................................................................... 66 
`10. Claim 15 ............................................................................................... 68 
`11. Claim 16 ............................................................................................... 70 
`12. Claim 17 ............................................................................................... 70 
`13. Claim 18 ............................................................................................... 71 
`14. Claim 19 ............................................................................................... 72 
`D.  Ground 2: Claims 3 and 9-12 are obvious over Zhang, Gupta and Chien 72 
`1.  Claim 3 ................................................................................................. 72 
`2.  Claim 9 ................................................................................................. 77 
`3.  Claim 10 ............................................................................................... 79 
`4.  Claim 11 ............................................................................................... 80 
`5.  Claim 12 ............................................................................................... 80
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`
`TABLE OF EXHIBITS
`
`
`
`Description
`Exhibit No.
`Exhibit 1001 U.S. Patent No. 7,149,867 to Daniel Poznanovic, et al., filed June
`16, 2004, and issued on December 12, 2006 (the “’867 patent”).
`Exhibit 1002 Prosecution history of the ’867 patent.
`Exhibit 1003 X. Zhang et al., Architectural Adaptation for Application-
`Specific Locality Optimizations, IEEE (1997) (“Zhang”).1
`Exhibit 1004 R. Gupta, Architectural Adaptation in AMRM Machines, IEEE
`(2000) (“Gupta”).
`Exhibit 1005 A. Chien and R. Gupta, MORPH: A System Architecture for
`Robust High Performance Using Customization,” IEEE (1996)
`(“Chien”).
`Exhibit 1006 Declaration of Stanley Shanfield, Ph.D.
`Exhibit 1007 RESERVED
`Exhibit 1008 RESERVED
`Exhibit 1009 RESERVED
`Exhibit 1010 Declaration of Rajesh K. Gupta
`Exhibit 1011 Chien et al., Safe and Protected Execution for the Morph/AMRM
`Reconfigurable Processor, IEEE (1999).
`Exhibit 1012 Declaration of Jacob Munford
`Exhibit 1013 RESERVED
`Exhibit 1014 Order Governing Proceedings - Patent Case by Judge Alan D
`Albright, filed on June 30, 2020 in FG SRC LLC v. Intel
`
`1 For ease of reference and citation, Petitioner has added line numbers to Exhibits
`
`1003, 1004, 1005 and 1011. For example, the citation “EX1003-15 C2:4-16” refers
`
`to Exhibit 1003, Page 15, Column 2, Lines 4-16, and the subsequent citation “id.-
`
`12 C1:12-C2:5” refers to Exhibit 1003, Page 12, Column 1, Line 12 through
`
`Column 2, Line 5.
`
`iii
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`Corporation, No. 6:20-cv-00315-ADA (W.D. Tex.)
`Exhibit 1015 Scheduling Order by Judge Alan D Albright, filed on August 1,
`2020 in FG SRC LLC v. Intel Corporation, No. 6:20-cv-00315-
`ADA (W.D. Tex.)
`Exhibit 1016 Plaintiffs SRC Labs, LLC & Saint Regis Mohawk Tribe's
`Opening Claim Construction Brief, filed on November 5, 2018 in
`SRC Labs, LLC et al. v. Amazon Web Services, Inc. et al., No.
`2:18-cv-00317-JLP (W.D. Was.)
`Exhibit 1017 Provisional Patent Application No. 60/479,339
`Exhibit 1018 Plaintiff's Preliminary Infringement Contentions, submitted on
`July 23, 2020 in FG SRC LLC v. Intel Corporation, No. 6:20-cv-
`00315-ADA (W.D. Tex.)
`Exhibit 1019 Plaintiff’s Original Complaint, filed on October 18, 2017 in SRC
`Labs, LLC et al. v. Amazon Web Services, Inc. et al., No. 1:17-
`cv-01227-JD (E.D.V.A.) now No. 2:18-cv-00317-JLP (W.D.
`Was.)
`Exhibit 1020 Plaintiff’s Original Complaint, filed on April 30, 2020 in FG
`SRC LLC v. Xilinx, No. 1:20-cv-00601-UNA (D. Del.)
`Exhibit 1021 Order Continuing Stay, filed on May 3, 2019 in SRC Labs, LLC
`et al. v. Amazon Web Services, Inc. et al., No. 2:18-cv-00317-
`JLP (W.D. Was.)
`Joint Status Report, filed on January 13, 2021 in SRC Labs, LLC
`et al. v. Amazon Web Services, Inc. et al., No. 2:18-cv-00317-
`JLP (W.D. Was.)
`Exhibit 1023 Scheduling Order, filed on February 25, 2021 in FG SRC LLC v.
`Xilinx, No. 1:20-cv-00601-UNA (D. Del.)
`Exhibit 1024 Notice of Subpoena Duces Tecum, dated January 5, 2018, SRC
`Labs, LLC et al. v. Amazon Web Services, Inc. et al., No. 1:17-
`cv-01227-JD (E.D.V.A.) now No. 2:18-cv-00317-JLP (W.D.
`Was.)
`
`Exhibit 1022
`
`
`
`iv
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`
`LISTING OF CHALLENGED CLAIMS
`
`Claim 1
`
`Preamble
`
`A reconfigurable processor that instantiates an algorithm as
`hardware comprising:
`
`Element 1(a)
`
`a first memory having a first characteristic memory bandwidth
`and/or memory utilization
`
`Element 1(b)
`
`a data prefetch unit coupled to the first memory
`
`Element 1(c)
`
`wherein the data prefetch unit retrieves only computational data
`required by the algorithm from a second memory of second
`characteristic memory bandwidth and/or memory utilization
`and places the retrieved computational data in the first memory
`Element 1(d) wherein the data prefetch unit operates independent of and in
`parallel with logic blocks using the computional [sic] data
`Element 1(e) wherein at least the first memory and data prefetch unit are
`configured to conform to needs of the algorithm
`
`Element 1(f)
`
`the data prefetch unit is configured to match format and
`location of data in the second memory
`
`The reconfigurable processor of claim 1, wherein:
`
`Claim 2
`
`Element 2(a)
`
`the data prefetch unit is coupled to a memory controller that
`controls the transfer of data between the second memory and
`the data prefetch unit
`
`Element 2(b)
`
`and [the memory controller] transmits only portions of data
`desired by the data prefetch unit and discards other portions of
`data prior to transmission of the data to the data prefetch unit
`
`v
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`
`Claim 3
`
`The reconfigurable processor of claim 1, wherein the data prefetch unit receives
`processed data from on-processor memory and writes the processed data to an
`external off-processor memory.
`
`Claim 4
`
`The reconfigurable processor of claim 1, wherein the data prefetch unit
`comprises at least one register from the reconfigurable processor.
`
`Claim 5
`
`The reconfigurable processor of claim 1, wherein the data prefetch unit is
`disassembled when another program is executed on the reconfigurable
`processor.
`
`Claim 6
`
`The reconfigurable processor of claim 1 wherein said second memory comprises
`a processor memory and said data prefetch unit is operative to retrieve data from
`the processor memory.
`
`Claim 7
`
`The reconfigurable processor of claim 6 wherein said processor memory is a
`microprocessor memory.
`
`Claim 8
`
`The reconfigurable processor of claim 6 wherein said processor memory is a
`reconfigurable processor memory.
`
`Claim 9
`
`Preamble
`
`A reconfigurable hardware system comprising:
`
`Element 9(a)
`
`a common memory
`
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`Element 9(b) one or more reconfigurable processors that can instantiate an
`algorithm as hardware coupled to the common memory
`
`Element 9(c)
`
`wherein at least one of the reconfigurable processors includes a
`data prefetch unit to read and write only data required for
`computations by the algorithm between the data prefetch unit
`and the common memory
`Element 9(d) wherein the data prefetch unit operates independent of and in
`parallel with logic blocks using the computational data
`Element 9(e) wherein the data prefetch unit is configured to conform to
`needs of the algorithm
`
`Element 9(f)
`
`and [the data prefetch unit is configured to] match format and
`location of data in the common memory
`
`Claim 10
`
`The reconfigurable hardware system of claim 9, comprising a memory controller
`coupled to the common memory and the data prefetch unit that transmits to the
`prefetch unit only data desired by the data prefetch unit as required by the
`algorithm.
`
`Claim 11
`
`The reconfigurable hardware system of claim 9, wherein the at least one of the
`reconfigurable processors also includes a computational unit coupled to a data
`access unit.
`
`Claim 12
`
`The reconfigurable hardware system of claim 11, wherein the computational
`unit is supplied the data by the data access unit.
`
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`
`A method of transferring data comprising:
`
`Claim 13
`
`Element 13(a)
`
`transferring data between a memory and a data prefetch unit
`in a reconfigurable processor
`
`Element 13(b)
`
`transferring the data between a computational unit and a data
`access unit
`
`Element 13(c)
`
`wherein the computational unit and the data access unit, and
`the data prefetch unit are configured to conform to needs of
`an algorithm implemented on the computational unit and
`transfer only data necessary for computations by the
`computational unit
`Element 13(d) wherein the prefetch unit operates independent of and in
`parallel with the computational unit
`
`Claim 14
`Element 14(a) The method of claim 13, wherein the data is written to the
`memory, said method comprising:
`
`Element 14(b)
`
`transferring the data from the computational unit to the data
`access unit
`
`Element 14(c) writing the data to the memory from the prefetch unit
`
`Claim 15
`Element 15(a) The method of claim 13, wherein the data is read from the
`memory, said method comprising:
`
`Element 15(b)
`
`transferring only the data desired by the data prefetch unit as
`required by the computational unit from the memory to the
`data prefetch unit
`
`viii
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`reading the data directly from the data prefetch unit to the
`computational unit through a data access unit
`
`Element 15(c)
`
`Claim 16
`
`The method of claim 15, wherein all the data transferred from the memory to the
`data prefetch unit is processed by the computational unit.
`
`Claim 17
`
`The method of claim 15, wherein the data is selected by the data prefetch unit
`based on an explicit request from the computational unit.
`
`Claim 18
`
`The method of claim 13, wherein the data transferred between the memory and
`the data prefetch unit is not a complete cache line.
`
`Claim 19
`
`The method of claim 13, wherein a memory controller coupled to the memory
`and the data prefetch unit, controls the transfer of the data between the memory
`and the data prefetch unit.
`
`
`
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`
`
`
`
`
`INTRODUCTION
`Xilinx, Inc. requests IPR of claims 1-19 (“Challenged Claims”) of U.S.
`
`Patent 7,149,867. The patentability analysis of this Petition is substantively
`
`equivalent to the petition instituted in IPR2020-01449, and Xilinx concurrently
`
`requests joinder to that proceeding. Section IV, infra, addresses various
`
`discretionary considerations unique to this Petition.
`
` MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`A. Real party-in-interest under 37 C.F.R. § 42.8(b)(1)
`Xilinx certifies that it is the real party-in-interest. As to the related matters
`
`below, Amazon and Xilinx have a customer/supplier relationship. Although Xilinx
`
`Ultrascale+ FPGAs and its Vivado Design Suite are referenced in a pending SRC
`
`Labs complaint against Amazon (identified below), Xilinx has not assumed the
`
`defense of any claim against Amazon in litigation and exercises no control over
`
`Amazon’s litigation defense. Similarly, Amazon does not exercise control over this
`
`Petition, has not funded this Petition, and has not participated in Xilinx’s
`
`preparation and filing of this Petition. The distinction between Xilinx and Amazon
`
`as to the ’867 patent is discussed further in §IV.
`
`B. Related matters under 37 C.F.R. § 42.8(b)(2)
`The ’867 patent is the subject of a number of civil actions including: FG
`
`SRC LLC v. Intel Corp., No. 6:20-cv-00315-ADA (W.D. Texas), filed April 24,
`
`1
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`

`

`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`2020; SRC Labs, LLC et al., v. Amazon Web Services, Inc., et al., No. 2:18-cv-
`
`00317 (W.D. Washington), filed Feb. 26, 2018; and FG SRC LLC v. Xilinx, Inc.,
`
`No. 1:20-cv-00601 (D. Delaware), filed April 30, 2020.
`
`The ’867 patent is the subject of a currently pending IPR: Intel Corporation
`
`v. FG SRC LLC, IPR2020-01449, filed August 10, 2020. The ’867 patent was
`
`previously the subject of another IPR: Amazon.com, Inc., et al., v. St. Regis
`
`Mohawk Tribe et al., IPR2019-00103, filed October 19, 2018.
`
`C. Lead and back-up counsel under 37 C.F.R. § 42.8(b)(3)
`Xilinx provides the following designation of counsel.
`
`Lead Counsel
`David M. Hoffman, Reg. No. 54,174
`Fish & Richardson P.C.
`3200 RBC Plaza
`60 South Sixth Street
`Minneapolis, MN 55402
`Tel: 202-783-5070
`Fax: 877-769-7945
`Email: IPR42653-0026IP1@fr.com
`
`Backup counsel
`Kenneth W. Darby, Reg. No. 65,068
`Fish & Richardson P.C.
`3200 RBC Plaza
`60 South Sixth Street
`Minneapolis, MN 55402
`Tel: 202-783-5070
`Fax: 877-769-7945
`PTABInbound@fr.com
`
`D.
`Service information under 37 C.F.R. § 42.8(b)(4)
`Please address correspondence/service to the above-listed address. Xilinx
`
`consents to email service at IPR42653-0026IP1@fr.com (referencing No. 42653-
`
`0026IP1 and cc’ing PTABInbound@fr.com, hoffman@fr.com, and
`
`kdarby@fr.com).
`
`
`
`2
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`

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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`
` REQUIREMENTS FOR IPR
`A.
`Payment
`Xilinx authorizes the Office to charge Deposit Account No. 06-1050 for the
`
`37 C.F.R. § 42.15(a) fee and further authorizes payment for any additional fees to
`
`be charged to this Deposit Account.
`
`B. Certification of standing
`Petitioner certifies that the ’867 patent is available for IPR and that
`
`Petitioner is not barred or estopped.
`
`C.
`
`Identification of challenge
`1.
`Challenged claims
`Petitioner requests an IPR trial on claims 1-19 of the ’867 patent to cancel
`
`each claim. Petitioner’s proposed constructions are in §VI.D., infra.
`
`2.
`Specific grounds
`The following prior art references render the Challenged Claims obvious
`
`under 35 U.S.C. §103:
`
` X. Zhang et al., Architectural Adaptation of Application-Specific
`
`Locality Optimizations, IEEE (1997) (“Zhang”) (EX1003). Zhang was
`
`published in 1997 and is prior art under at least §102(a) and §102(b).
`
` R. Gupta, Architectural Adaptation in AMRM Machines, IEEE (2000)
`
`(“Gupta”) (EX1004). Gupta was published in 2000 and is prior art
`
`under at least §102(a) and §102(b).
`
`3
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`

`

`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
` A. Chien and R. Gupta, MORPH: A System Architecture for Robust
`
`Higher Performance Using Customization,” IEEE (1996) (“Chien”)
`
`(EX1005). Chien was published in 1996 and is prior art under at least
`
`§102(a) and §102(b).
`
`The specific grounds for challenge below are supported by the Declaration
`
`of Dr. Stanley Shanfield (EX1006).
`
` Ground 1: Claims 1-2, 4-8, 13-19 are obvious over Zhang and Gupta.
`
` Ground 2: Claims 3 and 9-12 are obvious over Zhang, Gupta, and
`
`Chien.
`
` DISCRETIONARY CONSIDERATIONS
`Two IPR petitions addressing the ’867 patent have been filed by other
`
`parties. Amazon.com Inc. filed a petition on October 19, 2018 in IPR2019-00103
`
`(“Amazon Petition”). The Board denied institution of the Amazon Petition on May
`
`10, 2019 and denied Amazon’s request for rehearing on June 9, 2020. See Paper
`
`22, Paper 24. Intel Corporation filed another petition on August 10, 2020 in
`
`IPR2020-01449 (“Intel Petition”), and the Board instituted review on March 3,
`
`2021. See Paper 13.
`
`This Petition advances substantively equivalent prior art and arguments
`
`against the same claims as the Intel Petition, and Xilinx seeks joinder to IPR2020-
`
`01449.
`
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`
`A. Relevant Facts
`Patent Owner filed suit against Amazon alleging infringement of the ’867
`
`patent on October 18, 2017. See EX1019. Patent Owner’s complaint named the
`
`Amazon Web Services (“AWS”) EC2 F1 Instance, a cloud-based hardware
`
`acceleration service, as an accused product. Id. 12-16, 26-27, 34-43. Attendant
`
`claim charts identified Xilinx’s UltraScale+ Field Programmable Gate Array
`
`(“FPGA”) as hardware used by Amazon to deploy the AWS EC2 F1 Instance, but
`
`Xilinx was not accused of infringement. Id. Despite full knowledge of Amazon’s
`
`and Xilinx’s customer-supplier relationship regarding the UltraScale+ FPGA,
`
`Patent Owner waited roughly 2.5 years to file suit against Xilinx on April 30, 2020.
`
`See EX1020. The complaint alleges infringement of the ’867 patent by Xilinx’s
`
`UltraScale+ FPGA, the very same hardware Patent Owner ostensibly found an
`
`unbefitting target back in 2017. Id. 4-7, 12-13.
`
`The suit against Amazon has been transferred to the Western District of
`
`Washington and stayed pending decisions from the Board on a number of IPR
`
`petitions, including the Intel Petition. See EX1021, EX1022. The suit against
`
`Xilinx in the District of Delaware (“the Court”), while active, is currently in its
`
`infancy. The parties and the Court have only recently settled on a March 20, 2023
`
`trial date. See EX1023 at 15. Joinder to the instituted Intel Petition will lead to a
`
`5
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`Final Written Decision binding Xilinx a full year in advance of a jury trial in the
`
`Delaware Litigation.
`
`B.
`Prior Petitions
`This Petition is not a coordinated serial attack that presents the kind of
`
`“undue inequities and prejudices” addressed by the Board’s precedent. See General
`
`Plastic Indus. Co. v. Cannon Kabushiki Kaisha, IPR2016-01357, Paper 19 at 16
`
`(PTAB Sept. 6, 2017)(Paper 19)(§II.B.4.i precedential).
`
`As to the Intel Petition, Xilinx’s filing of a substantively identical petition
`
`and concurrent request for joinder in an understudy role will not unduly prejudice
`
`Patent Owner. The Board routinely permits joinder when a second-in-time
`
`petitioner files a mirror-image petition, and this case is no different. The facts here
`
`stand in stark contrast to the precedential Apple Inc. v. Uniloc 2017 LLC case
`
`where the Board denied institution and joinder based on General Plastic. See
`
`IPR2020-00854, Paper 9 (PTAB Oct. 28, 2020)(precedential). In that case, the
`
`petitioner seeking joinder had previously petitioned for, and been denied, IPR of
`
`the same patent. Id. at 2. Not so here. This is Xilinx’s first challenge against the
`
`’867 patent at the PTAB, and there is no risk of prejudice or abuse.
`
`This Petition also passes muster in view of the Amazon Petition for at least
`
`the reasons that follow.
`
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`Factor 1: Factor 1 favors institution because Xilinx and Amazon are
`
`separate petitioners under the Board’s precedent. See Valve Corp. v. Electronic
`
`Scripting Products, Inc., IPR2019-00062, Paper 11 at 2 (PTAB Apr. 2, 2019)
`
`(precedential)(“Valve I”); Valve Corp. v. Electronic Scripting Products, Inc.,
`
`IPR2019-00064, Paper 10 at 2 (PTAB May 1, 2019)(precedential)(“Valve II”).
`
`Not only are Xilinx and Amazon distinct business entities, Xilinx had no
`
`communications with Amazon relating to this Petition, and Xilinx is in no way
`
`representing Amazon’s interests or subject to control by Amazon. This Petition’s
`
`timing is consistent with Xilinx acting autonomously to protect its own interests
`
`and nothing more. The Delaware Litigation is ripe for a stay while in its early
`
`stages, and joinder to an instituted IPR proceeding will be the keystone of Xilinx’s
`
`motion to the Court. On the other hand, Amazon’s Washington Litigation is
`
`already stayed and has been for the last two years. See EX1021. Amazon is no
`
`different from any other party that generally stands to gain from IPR of an adverse
`
`patent. Indeed, Amazon would benefit from Intel’s initututed IPR irrespective of
`
`whether Xilinx’s Petition and joinder request are granted. And granting Xilinx’s
`
`request to join an instituted proceeding would not confer any particularized benefit
`
`to Amazon because Xilinx is not acting on Amazon’s behalf nor at Amazon’s
`
`behest.
`
`7
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`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`Notwithstanding the known customer-supplier arrangement between Xilinx
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`and Amazon, this case is distinguishable from those where Factor 1 favored denial
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`because of a “significant relationship” between two petitioners. Starting with the
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`Valve I & II cases, Xilinx and Amazon were never co-defendants. See Valve I,
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`p.10; Valve II, p.11. Nor did the parties experience a similar-in-time risk of
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`infringement, specifically because Patent Owner chose to withhold its infringement
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`allegations against Xilinx for 2.5 years. Id.; see also BMW of North America, LLC
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`et al. v. Paice LLC et al., IPR2020-00994, Paper 19 at 15 (PTAB Nov. 19, 2020)
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`(finding the fact that the patent owner separately sued the second-in-time petitioner
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`“some five years” after the first-in-time petitioners to “weigh against finding a
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`signficiant relationship”).
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`Xilinx had no reason to suspect Patent Owner would further extend its
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`already strained allegations against Amazon’s unique deployment of Xilinx’s
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`FPGAs to accuse the FPGAs alone. And Xilinx reasonably relied on Patent
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`Owner’s inaction as confirmation that Xilinx was not at risk. For example, Xilinx
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`grew more assured when Patent Owner did not bring suit in 2018 after Xilinx
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`responded to a third-party subpoena in the Amazon case. See EX1024. As more
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`time passed, it became even more apparent that Xilinx had no material risk of
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`infringement, until Patent Owner sprung its surprise complaint in 2020.
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`8
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`

`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`The facts here are also distinguishable from the precedential RPX case.
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`Unlike the petitioner there, Xilinx has not been “paid…to reduce [Amazon’s]
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`patent litigation exposure” with “no apparent risk of infringement liability itself.”
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`RPX Corp. v. Applications in Internet Time, LLC, IPR2015-01750, Paper 128 at 31
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`(PTAB Oct. 2, 2020)(precedential); see also id., 38-40. As discussed, Xilinx had
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`no incentive to pursue IPR, and did not do so, while Amazon was Patent Owner’s
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`lone target concerning the ’867 patent. Xilinx only sought to challenge the ’867
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`patent when Patent Owner aimed its infringement allegations at Xilinx’s FPGAs
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`2.5 years later.
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`It is indisputable that Xilinx and Amazon are different business entities, and
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`there has been no express, implied, or tacit coordination between them relating to
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`this challenge of the ’867 patent. In raising its respective infringement allegations
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`years apart in different forums, Patent Owner has treated Xilinx and Amazon
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`separately all along. Patent Owner could not credibly change course after all this
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`time for the sole purpose of precluding Xilinx from joinder.
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`Factors 2 & 4: These factors favor institution. Xilinx and Amazon are
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`separate petitioners, and this Petition offers an independent analysis that does not
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`mimic or even resemble the Amazon Petition. Xilinx did not tactically withhold
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`prior art or otherwise leverage Amazon’s work product.
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`9
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`

`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`As to the presently asserted prior art, Xilinx does not recall identifying it
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`until the Intel Petition was filed years after the Amazon Petition. Xilinx had no
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`reason to have discovered the art sooner because there was no legitimate threat of
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`infringement until Patent Owner filed suit in Delaware just four months ahead of
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`the Intel Petition. By requesting joinder in an understudy role, Xilinx has ensured
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`that the time elapsed since Xilinx discovered the prior art via the Intel Petition has
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`not resulted in an unfair advantage.
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`Factor 3: As discussed, this Petition raises grounds that mirror those
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`advanced in the Intel Petition. The Intel Petition was filed long after the Board
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`denied institution of the Amazon Petition, but it does not leverage the Board’s
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`analysis. The Amazon Petition relied on entirely different prior art and was denied
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`because Amazon sought IPR based on Patent Owner’s erroneous district court
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`constructions. The issues at play in the Amazon Petition do not apply to the Intel
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`Petition. Again, there is no prejudice or unfair advantage. This factor favors
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`institution.
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`Factor 5: The fifth General Plastic factor asks whether the petitioner
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`provides an adequate explanation for the time between the filings of multiple
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`petitions. General Plastic at 16. In this case, the explanation is straightforward.
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`The time between the filing of this Petition (Feb. 2021) and the Amazon Petition
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`(Oct. 2018) roughly corresponds to the 2.5-year time gap between Patent Owner’s
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`10
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`

`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`disparate infringement suits. Here again, institution and joinder cause no undue
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`prejudice to Patent Owner. This factor favors institution.
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`Factors 6 and 7: Xilinx fully appreciates that the Board’s resources are
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`finite. To promote efficiency, Xilinx chose to forego a separate petition and instead
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`pursue the understudy role of a joined party. Where, as here, Xilinx has not
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`previously petitioned against the ’867 patent, “a joinder request is [] an efficient
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`mechanism by which to become a petitioner in an IPR.” Apple v. Uniloc at 12. To
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`the extent Intel drops out of IPR2020-01449, the Board’s limited resources are well
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`spent completing an instituted trial on a patent deemed likely obvious. As to the
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`Board’s capacity to issue a Final Written Decision in a year or less, Xilinx aims to
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`accommodate this goal by moving for joinder, which will not impact the schedule
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`of IPR2020-01449. These factors favor institution.
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`C.
`Parallel Proceedings
`Xilinx took affirmative steps to promote the Board’s efficiency and fairness
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`goals addressed in Apple Inc. v. Fintiv, Inc. See IPR2020-00019, Paper 11 at 2-3
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`(PTAB Mar. 20, 2020)(“Fintiv I”). Most notably, Xilinx initiated this proceeding
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`with a mirror-image petition and motion for joinder in an understudy role. Joinder
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`carries no material increase in cost to the Board or the Patent Owner, and yet binds
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`Xilinx to the result of a Final Written Decision before trial in the Delaware
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`Litigation. In pursuit of further efficiency, Xilinx stipulates that:
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`11
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`

`Attorney Docket: 42653-0026IP1
`U.S. Patent 7,149,867
`If the Board joins Petitioner to IPR2020-01449, Petitioner will not
`pursue the grounds identified in this Petition in Case No. 1:20-cv-
`00601 in the District of Delaware.
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`Xilinx’s efforts to support fairness and efficiency, paired with the strong merits of
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`Grounds 1-2, provide compelling reasons to institute.
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`Factor 1—Factor 1 is neutral because neither party in the Delaware
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`Litigation has, as of yet, requested