Trials@uspto.gov
`571-272-7822
`
`Paper 15
`Date: August 2, 2021
`
`
`
`
`
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC.,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`IPR2021-00633
`Patent 7,149,867 B2
`
`Before KALYAN K. DESHPANDE, GREGG I. ANDERSON, and
`KARA L. SZPONDOWSKI, Administrative Patent Judges.
`SZPONDOWSKI, Administrative Patent Judge.
`
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`Granting Motion for Joinder
`35 U.S.C. 315(c), 37 C.F.R. § 42.122(b)
`
`
`
`
`
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`
`I.
`INTRODUCTION
`Xilinx, Inc. (“Petitioner”) filed a Petition requesting inter partes
`review of claims 1–19 of U.S. Patent 7,149,867 B2 (Ex. 1001, “the ’867
`patent”). Paper 2 (“Pet.”). Concurrently, Petitioner filed a Motion for
`Joinder pursuant to 35 U.S.C. § 315(c) and 37 C.F.R. § 42.122(b), seeking to
`be joined as a party to Intel Corp. v. FG SRC LLC, Case IPR2020-01449
`(PTAB March 3, 2021) (“the Intel IPR”), which also concerns claims 1–19
`of the ’867 patent. Paper 3 (“Motion”). Patent Owner FG SRC LLC
`(“Patent Owner”) filed an Opposition to Petitioner’s Motion for Joinder and
`Motion for Additional Discovery. Paper 7 (“Opposition”).1 With our
`authorization, Petitioner filed a Reply to Patent Owner’s Opposition to
`Petitioner’s Motion for Joinder (Paper 9, “Reply”) and Patent Owner filed a
`Sur-reply in Support of Its Opposition to Petitioner’s Motion for Joinder
`(Paper 10, “Sur-Reply”). In addition, Patent Owner filed a Preliminary
`Response to the Petition. Paper 12 (“Prelim. Resp.”).
`We have jurisdiction under 35 U.S.C. §§ 6, 314 and 37 C.F.R. § 42.4.
`For the reasons discussed below, we determine institution of inter partes
`review is warranted on the same grounds instituted in the Intel IPR and grant
`Petitioner’s Motion for Joinder.
`II. BACKGROUND
`A. Real Parties in Interest
`Petitioner identifies itself as the sole real party in interest. Pet. 1.
`Patent Owner identifies FG SRC LLC as the sole real party in interest.
`Paper 5, 2.
`
`
`1 Patent Owner’s Motion for Additional Discovery was denied. See Paper
`11.
`
`2
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`B. Related Matters
`The parties advise that the ’867 patent is the subject of the following
`district court litigations:
`FG SRC LLC v. Intel Corporation, 6:20-cv-00315-ADA (W.D. Tex.)
`filed April 24, 2020 (“the related district court proceeding”);
`FG SRC LLC v. Xilinx, Inc., 1:20-cv-00601-LPS (D. Del), filed April
`30, 2020; and
`SRC Labs, LLC et al., v. Amazon Web Services, Inc., et al., 2:18-cv-
`00317-JLR (W.D. Wash.), filed February 26, 2018.
`Pet. 1–2; Paper 5, 2.
`The Parties also advise that the ’867 patent is currently pending in the
`Intel IPR, and Petitioner advises that the ’867 patent was the subject of
`IPR2019-00103 (institution denied on May 10, 2019). Pet. 2; Paper 5, 2.
`C. The ’867 Patent (Ex. 1001)
`The ’867 patent issued from Application No. 10/869,200 filed June
`16, 2004, and claims the benefit of Provisional Application No. 60/479,339,
`filed June 18, 2003. Ex. 1001, codes [21], [22], [60]. The ’867 patent is
`titled “System and Method of Enhancing Efficiency and Utilization of
`Memory Bandwidth in Reconfigurable Hardware” and is generally directed
`to “enhancing the efficiency and utilization of memory bandwidth in
`reconfigurable hardware” and “implementing explicit memory hierarchies in
`reconfigurable processors that make efficient use of off-board, on-board,
`on-chip storage and available algorithm locality.” Id. at code [57], 1:15–24.
`1. Background and Summary of the Problem
`The ’867 patent explains that microprocessors “have enjoyed annual
`performance gains averaging about 50% per year,” where most of the gains
`were attributable to higher clock processor speeds, more memory bandwidth,
`
`3
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`and increasing utilization of instruction level parallelism (“ILP”) at
`execution time. Id. at 1:26–30. However, as microprocessor speeds
`increased, designing memory hierarchies that could keep up became
`challenging. Id. at 1:31–33. Therefore, “there has been significant effort
`spent on the development of memory hierarchies that can maintain high
`bandwidth efficiency and utilization with faster microprocessors.” Id. at
`1:48–50.
`The ’867 explains that one approach to improving bandwidth
`efficiency and utilization in memory hierarchies is the utilization of cache
`memories. Id. at 1:51–53. In designing cache memories, there are a number
`of considerations to take into account, such as the width of the cache line,
`cache associativity, how cache lines are replaced due to a capacity or
`conflict miss, the write policy for the cache, and the size and speed of the
`cache. Id. at 1:59–3:15. For example, wide cache lines are more efficient
`for programs that exhibit a high degree of spatial locality (i.e., it is likely
`that other data within the same cache line will be needed). Id. at 1:64–2:4.
`However, narrow cache lines are more efficient for programs that have low
`levels of spatial locality. Id. at 2:4–7. The ’867 patent states that the various
`considerations and tradeoffs makes cache design challenging for a
`multipurpose computer that executes a wide variety of programs in that “it is
`very difficult to design a single cache structure that is optimized for many
`different programs.” Id. at 3:28–30. Cache designers try to derive the
`program behavior of the “average” program, and optimize the cache for the
`“average” program. Id. at 3:32–36. As a result, the cache is sub-optimal for
`most programs, because most programs that actually run on the
`microprocessor are not “average.” Id. at 3:36–39.
`
`4
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`2. The Claimed Invention of the ’867 Patent
`According to the ’867 patent, because of the foregoing issues, there
`was a growing need to develop improved memory hierarchies that limited
`overhead of a memory hierarchy without also reducing bandwidth efficiency
`and utilization. Id. at 3:57–60. To address this need, the ’867 patent
`describes a system including a memory hierarchy and a reconfigurable
`processor that includes a data prefetch unit. Id. at 4:4–10, 5:60–62, 6:9–13,
`7:34–48. The ’867 patent states that a “Reconfigurable Processor” is “a
`computing device that contains reconfigurable components such as FPGAs
`[(field programmable gate arrays)] and can, through reconfiguration,
`instantiate an algorithm as hardware.” Id. at 5:26–29. The ’867 patent states
`that a “Data prefetch Unit” is “a functional unit [a set of logic that performs
`a specific operation] that moves data between members of a memory
`hierarchy [a collection of memories],” where such “movement may be as
`simple as a copy, or as complex as an indirect indexed strided copy into a
`unit stride memory.” Id. at 5:34–43.
`Figure 1 of the ’867 patent, reproduced below, shows a reconfigurable
`processor (RP) 100 of the claimed invention. Id. at 4:38–40.
`
`5
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`
`
`Figure 1 depicts a reconfigurable processor (RP) 100. Id. at 4:38–40.
`Figure 1 depicts reconfigurable processor 100, which “may be
`implemented using field programmable gate arrays (FPGAs) or other
`reconfigurable logic devices, that can be configured and reconfigured to
`contain functional units and interconnecting circuits, and a memory
`hierarchy comprising on-board memory banks 104, on-chip block RAM 106,
`registers wires, and a connection 108 to external memory.” Id. at 6:5–11. In
`addition, “on-chip reconfigurable components 102 create memory structures
`such as registers, FIFOs, wires and arrays using block RAM.” Id. at 6:11–
`14. “Dual-ported memory 106 is shared between on-chip reconfigurable
`
`6
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`components 102.” Id. at 6:14–15. “The reconfigurable processor 100 also
`implements user-defined computational logic . . . constructed by
`programming an FPGA to implement a particular interconnection of
`computational functional units.” Id. at 6:15–19. “In a particular
`implementation, a number of RPs 100 are implemented within a memory
`subsystem of a conventional computer, such as on devices that are
`physically installed in dual inline memory module (DIMM) sockets of a
`computer.” Id. at 6:19–23. “In this manner the RPs 100 can be accessed by
`memory operations and so coexist well with a more conventional hardware
`platform.” Id. at 6:23–25. The ’867 patent explains that “[u]nlike
`conventional static hardware platforms . . . the memory hierarchy provided
`in a RP 100 is reconfigurable” and “through the use of data access units and
`associated memory hierarchy components, computational demands and
`memory bandwidth can be matched.” Id. at 7:17–22.
`One or more data prefetch units are used to improve the memory
`hierarchy and bandwidth efficiency and utilization. Id. at 3:58–60, 8:62–65.
`Fig. 4 of the ’867 patent, reproduced below, depicts a logic block 300 with
`an addition of a data prefetch unit 401. Id. at 4:44–46.
`
`7
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`
`
`
`Figure 4 illustrates a logic block 300 (a block composed of computational
`functional units capable of taking data and producing results with each clock
`pulse) with the addition of a data prefetch unit 401. Id. at 7:6–8, 7:34–35.
`
`Logic block 300 includes computational functional units
`(computational logic) 301, 302, and 303, a control, and data access
`functional units 403 that present data to computational logic 301, 302, and
`303. Id. at 7:25–48, Fig. 4. Data prefetch unit 401 moves data from one
`member of the memory hierarchy 305 to another 308 (a block RAM
`memory). Id. at 7:34–37, Fig. 4. Data prefetch unit 401 operates
`“independently of other functional units 301, 302, and 303 and can therefore
`operate prior to, in parallel with, or after computational logic,” this
`“independence of operation permit[ting] hiding the latency associated with
`obtaining data for use in computation.” Id. at 7:37–42. In addition, data
`
`8
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`prefetch unit 401 may be “operated independently of logic block 300 that
`uses prefetched data.” Id. at 7:45–48. Data prefetch unit 401 deposits data
`into the memory hierarchy, where computational logic 301, 302, and 303
`can access it through data access units. Id. at 7:42–44.
`The ’867 patent explains:
`An important feature of the present invention is that many
`types of data prefetch units can be defined so that the
`prefetch hardware can be configured to conform to the
`needs of the algorithms currently implemented by the
`computational logic. The specific characteristics of the
`prefetch can be matched with
`the needs of
`the
`computational logic and the format and location of data in
`the memory hierarchy.
`Id. at 7:49–55. The ’867 patent provides an example of configuring a data
`prefetch unit depending on the needs of the computational logic. Id. at 7:52–
`62, Figs. 9A–9B (showing an external memory organized into a 128 byte (16
`word) block structure that is optimized for stride 1 access of the cache, and
`explaining that a stride 128 access can result in an inefficient use of
`bandwidth from the memory, since an extra 120 bytes of data is moved for
`every 8 bytes of requested data yielding a 6.25% bandwidth efficiency).
`The ’867 patent also provides an example in which
`data prefetch units 601 are configured to communicate with an
`intelligent memory controller 603 in FIG. 6 and can extract only
`the desired 8 bytes of data, discard the remainder of the memory
`block, and transmit to the data prefetch unit only the requested
`portion of the stride 128 data. The prefetch units 601 then
`delivers that data to the appropriate memory components within
`the memory hierarchy of the logic block 300. . . . An onboard
`memory bank data access unit 303 then delivers the data to
`computational logic 301 when required. The data prefetch units
`[] couple with an intelligent memory controller . . . that supports
`a strided reference pattern, which yields a 100% bandwidth
`efficiency in contrast to the 6.25% efficiency.
`
`9
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`
`
`
`Id. at 8:3–21.
`D. Illustrative Claims
`Among the challenged claims, claims 1, 9, and 13 are independent.
`Independent claims 1, 9, and 13 are reproduced below, with brackets noting
`Petitioner’s identifiers.
`1. [preamble] A reconfigurable processor that instantiates
`an algorithm as hardware comprising:
`[1(a)] a first memory having a first characteristic memory
`bandwidth and/or memory utilization; and
`[1(b)] a data prefetch unit coupled to the first memory,
`[1(c)] wherein the data prefetch unit retrieves only computational
`data required by the algorithm from a second memory of second
`characteristic memory bandwidth and/or memory utilization and
`places the retrieved computational data in the first memory [1(d)]
`wherein the data prefetch unit operates independent of and in
`parallel with logic blocks using the computional[sic] data, and
`[1(e)] wherein at least the first memory and data prefetch unit are
`configured to conform to needs of the algorithm, and [1(f)] the
`data prefetch unit is configured to match format and location of
`data in the second memory.
`
`
`
` [preamble] A reconfigurable hardware system,
`9.
`comprising:
`[9(a)] a common memory; and
`[9(b)] one or more reconfigurable processors that can
`instantiate an algorithm as hardware coupled to the common
`memory, [9(c)] wherein at least one of the reconfigurable
`processors includes a data prefetch unit to read and write only
`data required for computations by the algorithm between the data
`prefetch unit and the common memory [9(d)] wherein the data
`prefetch unit operates independent of and in parallel with logic
`blocks using the computational data, and [9(e)] wherein the data
`prefetch unit is configured to conform to needs of the algorithm
`and [9(f)] match format and location of data in the common
`memory.
`
`10
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`
`
`
`13. [preamble] A method of transferring data comprising:
`[13(a)] transferring data between a memory and a data
`prefetch unit in a reconfigurable processor; and
`[13(b)] transferring the data between a computational unit
`and a data access unit, [13(c)] wherein the computational unit
`and the data access unit, and the data prefetch unit are configured
`to conform to needs of an algorithm implemented on the
`computational unit and transfer only data necessary for
`computations by the computational unit, and [13(d)] wherein the
`prefetch unit operates independent of and in parallel with the
`computational unit.
`Ex. 1001, 12:39–54; 13:13–26; 14:1–11.
`E. Evidence
`Petitioner relies on the following references (see Pet. 3–4).
`Reference Exhibit
`Patent/Printed Publication
`Zhang
`1003
`Xingbin Zhang et al., Architectural Adaptation
`for Application-Specific Locality Optimizations,
`published in the Proceedings of the International
`Conference on Computer Design - VLSI in
`Computers and Processors (IEEE, October 12–
`15, 1997), 150–156
`Rajesh Gupta, Architectural Adaptation in
`AMRM Machines, Proceedings of the IEEE
`Computer Society Workshop on VLSI 2000
`(IEEE, April 27–28, 2000), 75–79
`Andrew A. Chien et al., MORPH: A System
`Architecture for Robust High Performance
`Using Customization (An NSF 100 TeraOps
`Point Design Study), Proceedings of Frontiers
`’96 – The Sixth Symposium on the Frontiers of
`Massively Parallel Computing (IEEE, October
`27–31, 1996), 336–345
`
`
`
`11
`
`Gupta
`
`1004
`
`Chien
`
`1005
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`F. Prior Art and Asserted Grounds
`Petitioner asserts that claims 1–19 are unpatentable on the following
`grounds (Pet. 4):
`Claims Challenged
`1, 2, 4–8, 13–19
`3, 9–12
`
`References
`Zhang, Gupta
`Zhang, Gupta, Chien
`
`35 U.S.C. §
`103
`103
`
`
`
`III. ANALYSIS
`Petitioner states that “[t]he patentability analysis of this Petition is
`substantively equivalent to the petition instituted in IPR2020-01449.” Pet.
`1; see also id. at 4, 11 (“mirror-image petition”).2
`Patent Owner filed a Preliminary Response. Paper 12. The Parties
`have jointly requested that we strike Section IV on pages 2–7 of the
`Preliminary Response, which presents arguments that the Petition should be
`denied under § 314(a) based upon the related district court proceeding.
`Prelim. Resp. 2–7; see Paper 14 (“Joint Motion to Strike”).
`In the Joint Motion to Strike, the Parties state that “[t]he arguments
`for discretionary denial under Fintiv were mistakenly included due to a
`misunderstanding of the current facts” and the Parties “agree that there is no
`basis for a Fintiv denial because no district court is progressing towards
`adjudication of the ’867 patent’s validity.” Joint Motion to Strike 1. The
`Parties argue that there is good cause to strike Section IV because it will (1)
`clarify the record by eliminating erroneous facts; (2) conserve the Parties’
`
`
`2 Petitioner also preemptively addresses several discretionary considerations
`that are unique to the Petition. Pet. 1, 5–14. Patent Owner does not raise
`these discretionary arguments in its Preliminary Response. See generally
`Prelim. Resp. We, therefore, need not address these arguments in light of
`our determination to institute.
`
`12
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`resources; and (3) conserve the Board’s resources. Id. at 1. In addition, the
`Parties stipulate that “beyond Section IV, the arguments in Patent Owner’s
`Preliminary Response in this proceeding mirror those from the
`corresponding brief in the instituted Intel IPR (Case IPR2020-01449).” Id.
`We instituted inter partes review of claims 1–19 of the ’867 patent
`based on the petition filed in the Intel IPR on March 3, 2021. Intel IPR,
`Paper 13. We agree based on our independent review of the Petition, the
`petition filed in the Intel IPR, and the evidence relied upon in both petitions
`that the Petition is substantially the same. Compare Pet. 14–80, with Intel
`IPR, Paper 1 at 10–87. We further agree based on our independent review
`of the Preliminary Response, the preliminary response filed in the Intel IPR,
`and the evidence relied upon in both, that the Preliminary Response (aside
`from Section IV) is substantially the same. Compare Prelim. Resp. 7–59
`with Intel IPR, Paper 9 at 9–61. Based upon the Parties’ representations, we
`grant the Joint Motion to Strike.
`For the same reasons discussed in our Decision on Institution in the
`Intel IPR, we find Petitioner has demonstrated a reasonable likelihood of
`showing at least one claim of the ’867 patent is unpatentable. See Intel IPR,
`Paper 13. We, therefore, find the Petition warrants institution of inter partes
`review of all challenged claims on all grounds raised.
`IV. GRANT OF MOTION FOR JOINDER
`Joinder in inter partes review is governed by 35 U.S.C. § 315(c),
`which states:
`(c) JOINDER.—If the Director institutes an inter partes review,
`the Director, in his or her discretion, may join as a party to that
`inter partes review any person who properly files a petition
`under section 311 that the Director, after receiving a
`preliminary response under section 313 or the expiration of the
`
`13
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`time for filing such a response, determines warrants the
`institution of an inter parties review under section 314.
`
`Procedurally, a motion for joinder must be filed “no later than one month
`after the institution date of any inter partes review for which joinder is
`requested.” 37 C.F.R. § 42.122(b)(2019). Petitioner filed its Motion for
`Joinder on March 15, 2021, within one month of our March 3, 2021 decision
`instituting the Intel IPR that Petitioner seeks to join.
`
`As the moving party, Petitioner bears the burden of proving that it is
`entitled to the requested relief. 37 C.F.R. § 42.20(c). A motion for joinder
`should (1) set forth the reasons joinder is appropriate; (2) identify any new
`grounds of unpatentability asserted in the petition; and (3) explain what
`impact (if any) joinder would have on the trial schedule for the existing
`review. See PTAB E2E Frequently Asked Questions, Question H5.3 A
`motion for joinder should further (4) address specifically how briefing and
`discovery may be simplified. See Kyocera Corp. v. SoftView LLC,
`IPR2013-00004, Paper 15 at 4 (PTAB Apr. 24, 2013) (representative) (Order
`Authorizing Third Party to File Motion for Joinder).
`Petitioner argues joinder is appropriate because the Petition “is
`materially the same as the petition filed in the” Intel IPR because they both
`“challenge the same claims, on the same grounds, and rely on the same prior
`art and evidence, including an identical declaration from the same expert.”
`Motion 1; see also id. at 4–7. Further, Petitioner “agrees to proceed solely
`on the grounds, evidence, and arguments advanced, or that will be advanced,
`in the” Intel IPR. Id. at 1; see also id. at 6. Petitioner argues that joinder
`
`
`3 Available at https://www.uspto.gov/patents-application-process/patent-
`trial-and-appeal-board/ptab-e2e-frequently-asked-questions.
`
`14
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`will not impact the trial schedule of the Intel IPR or unduly complicate the
`proceeding because Petitioner “will act as an ‘understudy’ and will not
`assume an active role unless Intel ceases to participate.” Id. at 2; see also id.
`at 7–8. Petitioner states that it “will not seek additional depositions or
`deposition time.” Id. at 2. In addition, Petitioner contends that joinder will
`“help efficiently resolve the disputes among the parties” and “will narrow
`the issues in the co-pending district court actions.” Id. at 2. Petitioner
`further argues that joinder will not unduly prejudice any party. Id. at 2.
`In opposition, Patent Owner contends that joinder should be denied as
`time-barred under 35 U.S.C. § 315(b) because Petitioner failed to name
`Amazon as a real party in interest or privy. Opp. 5–7.4 In the Sur-Reply,
`however, Patent Owner concedes that a time-barred party may be joined to
`an existing IPR, and appears to redirect its argument to deficiencies in the
`Petition under § 312(a)(2).5 Sur-Reply 1–2, 10. In the alternative, Patent
`Owner requested additional discovery generally directed to whether Amazon
`should have been named as a real party in interest. Opp. 8–15.
`We have addressed Patent Owner’s arguments in the Order denying
`Patent Owner’s Motion for Additional Discovery. See Paper 11 at 4–8. As
`discussed therein, the time bar of § 315(b) does not preclude joinder. Id. at
`5–6; see 35 U.S.C. § 315(b)(“The time limitation set forth in the preceding
`sentence shall not apply to a request for joinder under subsection (c)”).
`
`
`
`4 It is undisputed that Amazon was served with a complaint for infringement
`of the ’867 patent more than one year before the Petition was filed. See Opp.
`2–3, 13; Reply 2.
`5 Patent Owner cites incorrectly 35 U.S.C. § 312(b)(2). Sur-Reply 2.
`
`15
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`Upon considering Petitioner’s arguments and the evidence presented,
`we are persuaded that it is appropriate under these circumstances to join
`Petitioner to the Intel IPR. Petitioner challenges the same claims that are
`challenged in the Intel IPR on the same grounds using the same prior art and
`evidence. See Mot. 1, 4–7. Petitioner “explicitly agrees” that it will take an
`“understudy” role in the Intel IPR and only assume an active role should
`Intel cease to participate. See Mot. 7–8. Petitioner has further shown that
`the trial schedule will not be affected by joinder. Id. at 8. Thus, joinder to
`the Intel IPR would result in the just, speedy, and inexpensive resolution of
`Petitioner’s challenge. See 37 C.F.R. § 42.1(b).
`Accordingly, for the reasons discussed above, we grant Petitioner’s
`Motion for Joinder and join Petitioner as a party to the Intel IPR.
`V. ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that pursuant to 35 U.S.C. § 314, inter partes review is
`instituted as to the challenged claims of the ’867 patent with respect to all
`grounds of unpatentability presented in the Petition; and
`FURTHER ORDERED that Petitioner’s Motion for Joinder with
`IPR2020-01449 is granted, and Petitioner hereby joined as petitioners in
`IPR2020-01449; and
`FURTHER ORDERED that the grounds on which trial in IPR2020-
`01449 were instituted are unchanged, and no other grounds are added in
`IPR2020-01449;
`FURTHER ORDERED that the Scheduling Order entered in
`IPR2020-01449 (Paper 14) and schedule changes agreed by the parties in
`IPR2020-01449 (pursuant to the Scheduling Order) shall govern the trial
`schedule in IPR2020-01449;
`
`16
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`FURTHER ORDERED that Petitioner’s role in IPR2020-01449 shall
`be limited as stated by Petitioner in the Motion for Joinder (Paper 3, 7–8)
`unless and until Intel is terminated from that proceeding;
`FURTHER ORDERED that the case caption in IPR2020-01449 shall
`be changed to reflect joinder of Xilinx, Inc. as a petitioner in accordance
`with the attached example; and
`FURTHER ORDERED that a copy of this Decision be entered into
`the record of IPR2020-01449;
`FURTHER ORDERED that the instant proceeding is terminated
`under 37 C.F.R. § 42.72 and all further filings shall be made in IPR2020-
`01449; and
`FURTHER ORDERED that the Joint Motion to Strike (Paper 14) is
`granted.
`
`
`
`17
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`For PETITIONER:
`
`David Hoffman
`Kenneth Darby
`FISH & RICHARDSON P.C.
`hoffman@fr.com
`kdarby@fr.com
`
`
`For PATENT OWNER:
`
`Jay Kesan
`DIMUROGINSBERG, PC
`DGKEYIP GROUP
`jay@jaykesan.com
`
`Ari Rafilson
`SHORE CHAN DEPUMPO LLP
`arafilson@shorechan.com
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`18
`
`

`

`IPR2021-00633
`Patent 7,149,867 B2
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION and XILINX, INC.,6
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`IPR2020-01449
`Patent 7,149,867 B2
`
`
`
`
`
`
`
`
`
`
`6 Xilinx, Inc. filed a motion for joinder and petition in IPR2021-00633,
`which were granted, and, therefore, has been joined as petitioner in this
`proceeding.
`
`19
`
`