Paper No. 12
`June 25, 2021
`
`
`
`IPR2021-00633
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`XILINX, LLC,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`
`
`
`
`
`
`Patent No. 7,149,867
`
`
`
`
`
`
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`
`
`
`
`
`
`PATENT OWNER FG SRC LLC’S PRELIMINARY RESPONSE TO
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,149,867
`
`

`

`
`
`V.
`
`TABLE OF CONTENTS
`
`INTRODUCTION ........................................................................................... 1
`I.
`RELATED PROCEEDINGS .......................................................................... 1
`II.
`SRC BACKGROUND .................................................................................... 2
`III.
`IV. THE BOARD SHOULD DENY INSTITUTION UNDER § 314(a) ............. 2
`A. All of the Fintiv Factors Favor Denial of Institution. ........................... 3
`B.
`Efficiency and Integrity of the System Are Best Served by
`Denying Institution. .............................................................................. 5
`TECHNOLOGY BACKGROUND ................................................................ 7
`A.
`Reconfigurable Processors and FPGAs. ............................................... 7
`B. Memory Hierarchies. ............................................................................ 8
`C.
`Prefetching. ........................................................................................... 9
`VI. THE ’867 PATENT ....................................................................................... 10
`A.
`The Invention Of The ’867 Patent. ..................................................... 11
`B.
`Prefetching. ......................................................................................... 14
`C.
`The ’867 Patent Discloses The Exact Technology Of Chien,
`Zhang, And Gupta In Its “Relevant Background” Discussion. .......... 15
`VII. THE ASSERTED PRIOR ART REFERENCES .......................................... 17
`A.
`Chien (Ex. 1005). ................................................................................ 18
`B.
`Zhang (Ex. 1003). ............................................................................... 20
`C.
`Gupta (Ex. 1004). ................................................................................ 22
`VIII. PETITIONER HAS FAILED TO MEET ITS BURDEN IN
`ESTABLISHING ZHANG, GUPTA, AND CHIEN AS PRINTED
`PUBLICATIONS .......................................................................................... 24
`A.
`Legal Standards for Establishing Printed Publication. ....................... 24
`
`

`

`
`
`B.
`
`X.
`
`Petitioner Has Not Met The Standards For Establishing Zhang,
`Gupta and Chien as Printed Publications. .......................................... 25
`1.
`Petitioner’s Conference Distribution Theory ........................... 26
`2.
`Petitioner’s IEEE Xplore Website Theory. .............................. 28
`3.
`Petitioner’s Online Library Records Theory. ........................... 30
`4.
`Each of Petitioner’s Grounds Therefore Fails. ......................... 33
`IX. PATENT OWNER’S CLAIM CONSTRUCTIONS .................................... 34
`A. Agreed Terms. ..................................................................................... 34
`B.
`Terms to Be Construed. ...................................................................... 35
`1.
`“retrieves only computational data required by the
`algorithm from a second memory… and places the
`retrieved computational data in the first memory” ................... 35
`“read and write only data required for computations by
`the algorithm between the data prefetch unit and the
`common memory” .................................................................... 36
`PETITIONER HAS FAILED TO DEMONSTRATE A
`REASONABLE LIKELIHOOD OF PREVAILING AS TO ANY
`CHALLENGED CLAIM .............................................................................. 36
`A. Ground 1: Claims 1-2, 4-8 And 13-19 Are Not Obvious Over
`Zhang And Gupta. ............................................................................... 36
`1.
`The combination does not render obvious a
`“reconfigurable processor that instantiates an algorithm
`as hardware.” ............................................................................ 37
`The combination does not render obvious a “data prefetch
`unit.” ......................................................................................... 40
`The combination does not render obvious a data prefetch
`unit “wherein the data prefetch unit retrieves only
`computational data required by the algorithm.” ....................... 41
`The combination does not render obvious a first memory
`and a data prefetch unit “wherein at least the first memory
`and data prefetch unit are configured to conform to needs
`of the algorithm.” ...................................................................... 44
`The combination does not render obvious a data prefetch
`unit “configured to match format and location of data in
`the second memory.” ................................................................ 49
`iii
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`2.
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`2.
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`3.
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`4.
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`5.
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`

`

`6.
`
`7.
`
`8.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`
`
`
`
`B.
`
`The combination does not render obvious a memory
`controller that “transmits only portions of data desired by
`the data prefetch unit and discards other portions of data
`prior to transmission of the data to the data prefetch unit.” ..... 50
`The combination does not render obvious a
`“reconfigurable processor” as required by claim 13. ............... 50
`The combination does not render obvious a
`reconfigurable processor “wherein the computational unit
`and the data access unit, and the data prefetch unit are
`configured to conform to needs of an algorithm
`implemented on the computational unit and transfer only
`data necessary for computations by the computational
`unit” as required by claim 13. ................................................... 51
`Ground 2: Claims 3 And 9-12 Are Not Obvious Over Zhang,
`Gupta, And Chien. .............................................................................. 52
`1.
`The combination does not render obvious a
`“reconfigurable processor[] that can instantiate an
`algorithm as hardware.” ............................................................ 52
`The combination does not render obvious a “data prefetch
`unit.” ......................................................................................... 53
`The combination does not render obvious “a data prefetch
`unit to read and write only data required for computations
`by the algorithm.” ..................................................................... 54
`The combination does not render obvious a data prefetch
`unit configured to “match format and location of data in
`the common memory.” ............................................................. 55
`The combination does not render obvious a memory
`controller that “transmits to the prefetch unit only data
`desired by the data prefetch unit as required by the
`algorithm.” ................................................................................ 55
`The combination does not render obvious a
`“reconfigurable processor [that] also includes a
`computational unit” as required by claim 11. ........................... 56
`XI. SECONDARY CONSIDERATIONS OF NON-OBVIOUSNESS .............. 56
`XII. CONCLUSION ............................................................................................. 59
`
`
`
`
`iv
`
`

`

`
`
`CASES:
`
`TABLE OF AUTHORITIES
`
`Acceleration Bay, LLC v. Activision Blizzard, Inc.,
`908 F.3d 765 (Fed. Cir. 2018) ..................................................................... 27, 29, 32
`Acme Scale Co. v. LTS Scale Co., LLC,
`615 F. App’x 673 (Fed. Cir. 2015) .......................................................................... 22
`Cuozzo Speed Techs. v. Lee,
`136 S. Ct. 2131 ............................................................................................................. 2
`Elan Pharm., Inc. v. Mayo Found. For Med. Educ. & Research,
`346 F.3d 1051 (Fed. Cir. 2003) ................................................................................ 22
`Intelligent Bio-Systems, Inc. v. Illumina Cambridge Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) ................................................................................ 36
`Jazz Pharm., Inc. v. Amneal Pharm., LLC,
`895 F.3d 1347 (Fed. Cir. 2018) ................................................................................ 27
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ............................................................. 36
`
`Samsung Elec. Co. v. Infobridge Pte. Ltd.,
`929 F.3d 1363 (Fed. Cir. 2019) ......................................................................... passim
`SRI Int’l, Inc. v. Internet Sec. Sys., Inc.,
`511 F.3d 1186 (Fed. Cir. 2008) ............................................................................... 27
`Solas OLED v. Dell Techs. Inc.,
`6-19-cv-00514-ADA, Text Order dated Jun. 23, 2020 (W.D. Tex.) ....................... 3
`
`Solas OLED v. Dell Techs. Inc.,
`6-19-cv-00515-ADA, Text Order dated Jun. 23, 2020 (W.D. Tex.) ....................... 3
`Voter Verified, Inc. v. Premier Election Solutions, Inc.,
`698 F.3d 1374 (Fed. Cir. 2012) ................................................................................ 32
`ADMINISTRATIVE ORDERS:
`
`Apple Inc. v. Fintiv, Inc.,
`Case IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) ............................... passim
`
`v
`
`

`

`
`
`General Plastic Indus. Co., Ltd. v. Canon Kabushiki Kaisha,
`Case IPR2016–01357, Paper 19 (PTAB Sept. 6, 2017) ......................................... 8
`Hulu, LLC v. Sound View Innovations, LLC,
`Case IPR2018-01039, Paper 29 (PTAB POP Dec. 20, 2019) ................. 27, 35, 36
`Mylan Pharms., Inc. v. Bayer Intellectual Property GMBH,
`Case IPR2018-01143, Paper 13 (PTAB Dec. 3, 2018) .............................................. 9
`NetApp, Inc. v. Realtime Data LLC,
`Case IPR2017-01195, Paper 9 (PTAB Oct. 12, 2017) ........................................... 8
`NHK Spring Co., Ltd v. Intri-Plex Techs., Inc.,
`Case IPR2018-00752, Paper 8 (PTAB Sept. 12, 2018) ......................................... 8, 9
`
`Philip Morris Prod., S.A. v. RAI Strategic Holdings, Inc.,
`Case IPR2020-00921, Paper 9 (PTAB Nov. 16, 2020) ................................ passim
`STATUTES:
`
`35 U.S.C. § 103 ........................................................................................................... 1, 36
`
`35 U.S.C. § 314 ........................................................................................................ 2, 9, 62
`
`REGULATIONS:
`
`37 C.F.R. § 42.100 ............................................................................................................ 6
`
`vi
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`

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`
`
`
`INTRODUCTION
`I.
`Patent Owner FG SRC LLC (hereinafter “SRC” or “Patent Owner”)
`
`respectfully submits this Patent Owner Preliminary Response to the Petition for Inter
`
`Partes Review dated March 15, 2021 (“Petition”) of U.S. Patent No. 7,149,867 (Ex.
`
`1001, “’867 patent”) filed by Xilinx, Inc. (“Xilinx” or “Petitioner”), which is a near
`
`identical copy of the Petition for Inter Partes Review dated August 10, 2020 (“Intel
`
`IPR”) of U.S. Patent No. 7,149,867 (Ex. 1001, “’867 patent”) filed by Intel
`
`Corporation (“Intel”). Petitioner also submitted a motion for joinder of the Intel IPR
`
`(Paper 3) which Patent Owner has opposed (Paper 7). Petitioner asserts that claims
`
`1-19 of the ’867 patent are unpatentable on two grounds based solely on 35 U.S.C.
`
`§ 103:
`
`Ground 1 – Claims 1-2, 4-8, 13-19 are unpatentable as obvious over
`
`Zhang in view of Gupta as understood by one of ordinary skill in the art.
`
`Ground 2 – Claims 3 and 9-12 are unpatentable as obvious over Zhang in
`
`view of Gupta and Chien as understood by one of ordinary skill in the art.
`
`This Preliminary Response is timely filed based on the Board’s November 10,
`
`2020 Order. See Paper 8.
`
`II. RELATED PROCEEDINGS
`Related Proceedings are listed in Paper 1, at 1-2.
`
`1
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`

`

`
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`III. SRC BACKGROUND
`Patent Owner’s predecessor, SRC Computers was founded in 1996 by Jon
`
`Huppenthal, Jim Guzy, and Seymore Robert Cray (hence SRC). Ex. 2005, ¶¶ 36-
`
`37; Ex. 2002. Mr. Cray—widely considered to be the father of supercomputing—
`
`designed a series of computers that for decades were the fastest in the world. Ex.
`
`2002; Ex. 2005, ¶ 40. SRC’s patent portfolio is a direct result of this work.
`
`IV. THE BOARD SHOULD DENY INSTITUTION UNDER § 314(a)
`The Board should exercise its discretion under 35 U.S.C. § 314(a) to deny
`
`Xilinx’s Petition. Petitioner concedes that all the claims that are at issue in the
`
`WDTX Action are also at issue here. Paper 1, at 4; Exs. 2004, 2005, 2018.
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`Accordingly, this proceeding would be duplicative of the related district court case
`
`involving the same parties and the same patent, and that case will outpace a final
`
`written decision in this proceeding.
`
`Section 314(a) provides the Director with discretion to deny a petition. See
`
`35 U.S.C. § 314(a); Cuozzo Speed Techs. v. Lee, 136 S. Ct. 2131, 2140 (“[T]he
`
`agency’s decision to deny a petition is a matter committed to the Patent Office’s
`
`discretion.”). When considering whether to exercise its discretion not to institute,
`
`the circumstances surrounding proceedings “related to the same patent, either at the
`
`Office, in the district courts, or the ITC” are considered. See Consolidated Trial
`
`Practice Guide (November 2019) at 58. Several factors inform that consideration:
`
`1. whether the court granted a stay or evidence exists that one may be granted
`if a proceeding is instituted;
`
`2
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`

`

`
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`2. proximity of the court’s trial date to the Board’s projected statutory
`deadline for a final written decision;
`3. investment in the parallel proceeding by the court and the parties;
`4. overlap between issues raised in the petition and in the parallel
`proceeding;
`5. whether the petitioner and the defendant in the parallel proceeding are the
`same party; and
`6. other circumstances that impact the Board’s exercise of discretion,
`including the merits.
`
`Apple Inc. v. Fintiv, Inc., IPR2020-00019, Paper 11, at 5-6 (PTAB Mar. 20, 2020)
`
`(precedential); Philip Morris Prod., S.A. v. RAI Strategic Holdings, Inc., IPR2020-
`
`00921, Paper 9, at 14-15 (PTAB Nov. 16, 2020). The Board must then take “a
`
`holistic view of whether efficiency and integrity of the system are best served by
`
`denying or instituting review.” Fintiv, IPR2020-0019, Paper 11, at 6.
`
`Applying the Fintiv analysis to the facts in this instance, Xilinx’s Petition must
`
`be denied.
`
`A. All of the Fintiv Factors Favor Denial of Institution.
`Regarding Fintiv Factor 1, Xilinx has not yet requested a stay and failed to
`
`provide any evidence demonstrating that the DDE Action would be stayed if this
`
`IPR is instituted. Paper 1, at 7. Thus, this factor weighs against institution. Xilinx
`
`has submitted no evidence that a stay may be granted if a proceeding is instituted.
`
`Fintiv Factor 2 is neutral because the trial in District Court is scheduled after
`
`the Final Written Decision would issue in this case.
`
`Regarding Fintiv Factor 3, Xilinx has already answered the complaint, the
`
`amended complaint, and the second amended complaint. The parties have already
`
`3
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`

`

`
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`exchanged infringement and invalidity contentions, technical and financial
`
`documents have been produced, claim construction proceedings are underway, and
`
`a Markman hearing has been scheduled. Ex. 2016. The claim construction standard
`
`is the same. Consolidated Trial Practice Guide at 70; 37 C.F.R. § 42.100(b). Thus,
`
`the Board will be duplicating the same claim construction efforts. Moreover, like
`
`the petitioner in Fintiv, Xilinx filed its petition between the initial case management
`
`proceedings and the Markman hearing. IPR2020-00019, Paper 15, at 9. Thus, this
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`factor favors denial. See id., at 13-14.
`
`Regarding Fintiv Factor 4, Petitioner’s narrow stipulation does not eliminate
`
`the possibility that substantially similar art and arguments will be raised by Petitioner
`
`in the WDTX Action. See Philip Morris, IPR2020-00921, Paper 9, at 19
`
`(considering Petitioner stipulation that “it will not pursue any IPR grounds in the
`
`EDVA case if the Board institutes”). Petitioner and its expert argue that the three
`
`references are related to the “same project,” and it has not committed to drop its
`
`reliance on that project. See, e.g. Ex. 1006, ¶ 122. This factor therefore favors
`
`denying institution. Fintiv, IPR2020-00019, Paper 15, at 15.
`
`Regarding Fintiv Factor 5, Petitioner concedes that it is the sole defendant in
`
`the WDTX Action. Paper 1, at 2. This factor therefore favors denying institution.
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`Fintiv, IPR2020-00019, Paper 15, at 15; Philip Morris, IPR2020-00921, Paper 9, at
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`20.
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`4
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`
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`Regarding Fintiv Factor 6, the merits of Xilinx’s petition are too weak to
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`overcome the remaining factors. For example, Petitioner has failed to establish with
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`particularity that any of the asserted non-patent references are printed publications
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`that were publicly available as to the critical date. See Section VIII., infra. Because
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`these are the only references cited, their failure to qualify as prior art dooms the
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`petition. This factor therefore favors denial. Fintiv, IPR2020-00019, Paper 15, at
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`15-17.
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`Finally, all arguments Xilinx presents have recently been rejected by the
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`Board. In Philip Morris, the petitioner argued that the Board should not exercise its
`
`discretion not to institute because a stay might be requested and granted, the trial
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`date was not set with certainty, the district court proceedings were at an early stage
`
`with little activity apart from filing of claim construction briefs, the petitioner
`
`provided a narrow stipulation as to the issues that it would not pursue in the district
`
`court if the IPR was instituted, and the Board found the merits of the petition to be
`
`strong. Id. These are the same arguments that Petitioner is presenting here. See
`
`Paper 1, at 6-7.
`
`Thus, all of the Fintiv factors favor discretionary denial in this case.
`
`B.
`
`Efficiency and Integrity of the System Are Best Served by
`Denying Institution.
`“In general, an anticipated district court trial date substantially in advance of a
`
`projected statutory deadline for the Board to issue a final decision increases the likelihood
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`5
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`
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`that the district court will reach a determination of the parties’ dispute as to the validity of
`
`the challenged claims before the Board will. Under such circumstances, the application
`
`of Office policy has often resulted in the denial of institution.” Philip Morris, IPR2020-
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`00921, Paper 9, at 28 (citations omitted).
`
`Here, there are no factors that favor institution. Even if the merits of the asserted
`
`grounds were to favor institution, “the efficiency and integrity of the system … taking into
`
`account the consistent application of Office policy” requires that institution be denied. Id.,
`
`at 28-29; see also NHK Spring Co., Ltd v. Intri-Plex Techs., Inc., Case IPR2018-00752,
`
`Paper 8, at 19-20 (PTAB Sept. 12, 2018); NetApp, Inc. v. Realtime Data LLC, Case
`
`IPR2017-01195, Paper 9, at 12-13 (PTAB Oct. 12, 2017).
`
`Finally, the AIA was designed to “limit unnecessary and counterproductive
`
`litigation costs.” H.R. Rep. No. 112-98, pt. 1, at 40 (2011), 2011 U.S.C.C.A.N. 69,
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`69; Consolidated Trial Practice Guide at 56. Given the substantial overlap between
`
`the district court action and this IPR, this proceeding is not an effective and
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`appropriate use of the Board’s resources and is contrary to the AIA’s overall goal to
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`“make the patent system more efficient by the use of post-grant review proceedings.”
`
`See General Plastic Industrial Co., Ltd. v. Canon Kabushiki Kaisha, Case IPR2016-
`
`01357, Paper 19, at 16-17 (PTAB Sept. 6, 2017) (precedential). IPRs are not a tool
`
`to delay prosecution for infringement. Thus, institution is not justified here. NHK
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`Spring, Paper 8, at 19-20; NetApp, Paper 8, at 12-13; see also Mylan Pharms., Inc.
`
`6
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`

`

`
`
`v. Bayer Intellectual Property GMBH, Case IPR2018-01143, Paper 13, at 12-14
`
`(PTAB Dec. 3, 2018).
`
`Accordingly, the Board should deny institution under § 314(a).
`
`V. TECHNOLOGY BACKGROUND
`A. Reconfigurable Processors and FPGAs.
`The ’867 patent relates to the use of reconfigurable processors, such as those
`
`made using FPGAs. Ex. 1001, 1:16-24, 5:26-29. An FPGA is a reprogrammable
`
`integrated circuit that contains an array of programmable logic blocks and memory
`
`elements connected via programmable interconnect. Ex. 2001, ¶ 54, Ex. 2010, ¶ 14.
`
`A user can program an FPGA to perform a specific function by configuring the logic
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`blocks and interconnect. This enables the user to create a hardware accelerated
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`implementation of an algorithm by programming the FPGA in a manner that
`
`efficiently executes the algorithm. Id. In other words, with a reconfigurable
`
`processor such as an FPGA, the hardware can adapt to the algorithm. An FPGA is
`
`configured by loading a file called a bitstream into the FPGA. Id. Reconfigurable
`
`processors instantiate hardware to directly perform the required task, and do not rely
`
`on “instructions” the way a general-purpose CPU does. For this reason, the term
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`“instruction” does not have a plain and ordinary meaning with respect to
`
`reconfigurable processors. Id.
`
`In contrast, a CPU executes an algorithm by performing a sequence of
`
`instructions that implement the algorithm. Ex. 2001, ¶ 55, Ex. 2010, ¶ 15. A
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`7
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`
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`different algorithm can be implemented on the CPU by changing the instruction
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`sequence. Id. The CPU is flexible; it can implement almost any algorithm. Id. But
`
`because the CPU hardware is fixed, it cannot be customized towards the needs of
`
`any particular algorithm like an FPGA. Id. These customizations allow FPGA
`
`implementations to be orders of magnitude more efficient than implementing that
`
`algorithm as software on a CPU. Id.
`
`B. Memory Hierarchies.
`Computing systems including CPUs and FPGAs typically employ a memory
`
`hierarchy, which combines different types of memories in an attempt to ensure that
`
`data required for computation is available as needed. Ex. 2001, ¶ 125, Ex. 2010,
`
`¶ 18. There is a general trade-off between memory size and bandwidth. Id. In
`
`general, larger memories have lower bandwidth, i.e., they can store a lot of data but
`
`the rate at which they can transfer this data (bits/second) is low. Id. Smaller
`
`memories have much higher bandwidth. Id. Thus, memory systems commonly use
`
`hierarchies of progressively faster (higher bandwidth) but smaller size. Id.
`
`The ’867 patent discusses memory throughout the claims and specification.
`
`For example, Claim 1 recites moving data from a “second memory” to a “first
`
`memory” within a memory hierarchy. This is akin to the concepts described above,
`
`in which data can be moved from slower, larger memory (e.g., a second memory) to
`
`quicker, smaller memory (e.g., a first memory). Ex. 2001, ¶ 127, Ex. 2010, ¶¶ 20-
`
`21.
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`8
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`
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`The invention of the ’867 patent specifically “relates to implementing explicit
`
`memory hierarchies in reconfigurable processors that make efficient use of off-
`
`board, on-board, on-chip storage and available algorithm locality. These explicit
`
`memory hierarchies avoid many of the tradeoffs and complexities found in the
`
`traditional [implicit] memory hierarchies of microprocessors.” Ex. 1001, 1:18-24.
`
`Implicit memory devices encompass a family of processing elements that are
`
`all implicitly controlled and typically are made up of fixed logic that is not altered
`
`by the user. These devices execute software-directed instructions on a step-by-step
`
`basis in fixed logic having predetermined interconnections and functionality. Ex.
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`2001, ¶ 121.
`
`Explicit memory devices, on the other hand, are Direct Execution Logic
`
`(DEL) and comprise a family of components that are explicitly controlled and are
`
`typically reconfigurable. This set of elements enables a program to establish an
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`optimized interconnection among the selected functional units in order to implement
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`a desired computational, pre-fetch and/or data access functionality for maximizing
`
`the parallelism inherent in the particular code. Id., ¶ 29.
`
`Prefetching.
`C.
`A simple (unoptimized) memory system would have a processor that requests
`
`data when it is required for computation. Ex. 2001, ¶ 56, Ex. 2010, ¶ 22. This can
`
`be problematic especially if the data resides in off-chip memory, which has a large
`
`latency or large number of cycles (e.g., hundreds or more) to retrieve the data. Id.
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`9
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`This requires the computational unit to stall or wait while the data is being loaded.
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`Id. This problem is addressed by a “prefetch unit”, which fetches needed data before
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`it is needed by the processor.
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`Prefetching initiates a request for data before that data is required. In an ideal
`
`case, the prefetch data arrives no later than when it is required. Ex. 2001, ¶ 56, Ex.
`
`2010, ¶ 26. Generally speaking, there are two ways of prefetching data: 1)
`
`dynamically and 2) statically. Id. Dynamic prefetching attempts to guess what
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`future data is required by looking at past data access requests. Id. For example, a
`
`dynamic prefetch unit may see a request for some data and prefetch the next N data
`
`elements located spatially nearby to the initial data (with the hopes that the algorithm
`
`will request this data in the future). Id. Static prefetching techniques insert explicit
`
`prefetch instructions into the computer system, e.g., a compiler will analyze the
`
`algorithm and insert prefetch data fetches before the data is computed upon. Id.
`
`There are many types of prefetching techniques, and customizing the prefetching
`
`technique to the algorithm can provide significant overall performance benefits. Id.
`
`VI. THE ’867 PATENT
`The field of the invention of the ’867 patent is reconfigurable hardware. Ex.
`
`1001, 1:16-18. “More specifically, the invention relates to implementing explicit
`
`memory hierarchies in reconfigurable processors that make efficient use of off-
`
`board, on-board, on-chip storage and available algorithm locality. These explicit
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`10
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`
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`memory hierarchies avoid many of the tradeoffs and complexities found in the
`
`traditional [implicit] memory hierarchies of microprocessors.”
`
`A. The Invention Of The ’867 Patent.
`To improve upon the limitations of the prior art, the ’867 patent discloses a
`
`flexible yet efficient fully reconfigurable hardware system consisting of
`
`computational units, data prefetch units, data access units, and memory. Ex. 1001,
`
`Abstract. The parts are fully reconfigurable, meaning they can be configured as
`
`needed for a particular algorithm. Id. Once properly configured, the data prefetch
`
`unit retrieves data from a memory and supplies the data through a data access unit
`
`to the computational units in a way optimally adapted to the needs of the particular
`
`algorithm. Id.
`
`Computer programs are a collection of algorithms that interact to implement
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`desired functionality. Ex. 1001, 6:32-34. In the prior art, use of static computing
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`hardware resources (e.g., a conventional microprocessor), required the computer
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`program to be adapted to run on the particular hardware platform. Ex. 1001, 6:40-
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`42. “In this manner, the computer program is adapted to conform to the limitations
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`of the static hardware platform.” Id., 6:42-43.
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`The ’867 patent effectively flips the paradigm and allows software written in
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`a human readable high-level language to be compiled into direct execution logic
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`(DEL). The reconfigurable processor is then configured with the DEL. Ex. 1001,
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`6:52-54. “In this manner, the hardware resources are essentially adapted to conform
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`to the program rather than the program being adapted to conform to the hardware
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`resources.” Ex. 1001, 6:54-57.
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`Figure 1 represents a reconfigurable processor (RP):
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`Ex. 1001, Fig. 1.
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`The ’867 patent further recognized that “[h]igh memory bandwidth efficiency
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`is achieved when only data required for computation is moved within the memory
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`hierarchy.” Ex. 1001, 7:23-25. The ’867 patent further teaches use of a data prefetch
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`unit that “operates independently of other functional units. . . . This independence
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`of operation permits hiding the latency associated with obtaining data for use in
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`computation.” Ex. 1001, 7:36:42. A RP using a reconfigurable data prefetch unit is
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`illustrated in figure 4:
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`Ex. 1001, Fig. 4 (emphasis added). The data prefetch unit is reconfigurable and can
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`thus be adapted to the particular needs of a given program:
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`An important feature of the present invention is that many types of
`data prefetch units can be defined so that the prefetch hardware can be
`configured to conform to the needs of the algorithms currently
`implemented by the computational logic. The specific characteristics
`of the prefetch can be matched with the needs of the computational
`logic and the format and location of data in the memory hierarchy.
`Id., 7:49:55. Similarly, the memory hierarchy is reconfigurable and can also be
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`adapted to the particular needs of a given program:
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`Unlike conventional static hardware platforms, however, the memory
`hierarchy provided in a RP 100 is reconfigurable. In accordance with
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`the present invention, through the use of data access units and
`associated memory hierarchy components, computational demands
`and memory bandwidth can be matched.
`Id., 7:17:22 (emphasis added). The advantages achieved by the paradigm shift of
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`the ’867 patent are tremendous and enable a programmable memory mechanism
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`with up to 100% bandwidth efficiency and 100% bandwidth utilization:
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`The scaleable, programmable memory mechanisms enabled by the
`present invention are available to exploit available algorithm locality
`and thereby achieve up to 100% bandwidth efficiency. In addition,
`the scaleable computational resources can be leveraged to attain
`100% bandwidth utilization.
`Id., 12:18-29 (emphasis added). The ’867 patent was truly a pioneer patent, well
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`ahead of its time.
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`Prefetching.
`B.
`Prefetching is a key concept in the ’867 patent as every claim requires a “data
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`prefetch unit” which prefetches data from a second or common memory and
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`“operates independent of and in parallel with logic blocks using the [computational
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`data].” The purpose of prefetching data is to ensure that it is available when it is
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`needed in order to reduce latency. Ex. 2001, ¶ 56. Thus, the data prefetch unit must
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`be configured to know in advance what data to prefetch. Id.
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`The data prefetch unit specifically seeks to reduce the overhead involved in
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`prefetching data by avoiding transferring unnecessary data between memories, i.e.,
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`the prefetch unit copies only the data which are to be used in upcoming
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`computations. E.g., Ex. 1001, Claim 1. The patent is clear in that the data
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`prefetching unit moves computational data between two memories in a memory
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`hierarchy. E.g., Ex. 1001, Claim 1. The data prefetch unit “conforms to the needs
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`of the algorithm” to improve the performance of reconfigurable processor and
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`overall computing system.
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`C. The ’867 Patent Discloses The Exact Technology Of Chien, Zhang,
`And Gupta In Its “Relevant Background” Discussion.
`Chien, Zhang and Gupta present nothing more than prior art that was
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`overcome in the prosecution of the ’867 patent. Ex. 2001, ¶ 60. The ’867 patent
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`particularly focused on the challenge of designing memory hierarchies that could
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`keep up with ever increasing processor speeds. Ex. 1001, 1:32-35.
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`Two measures of the gap between the microprocessor and memory
`hierarchy are bandwidth efficiency and bandwidth utilization.
`Bandwidth efficiency refers to the ability to exploit available locality
`in a program or algorithm. In the ideal situation, when there is
`maximum bandwidth efficiency, all available locality is utilized.
`Bandwidth utilization refers to the amount of memory bandwidth
`that is utilized during a calculation. Maximum bandwidth utilization
`occurs when all available memory bandwidth is utilized.
`Id., 1:34-39 (emphasis added). “There has been significant effort spent on the
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`development of memory hierarchies that can maintain high bandwid